1 /*
2 * arch/arm/mach-at91/at91sam9260.c
3 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13 #include <linux/module.h>
14
15 #include <asm/proc-fns.h>
16 #include <asm/irq.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/cpu.h>
21 #include <mach/at91_dbgu.h>
22 #include <mach/at91sam9260.h>
23 #include <mach/at91_pmc.h>
24 #include <mach/at91_rstc.h>
25
26 #include "soc.h"
27 #include "generic.h"
28 #include "clock.h"
29 #include "sam9_smc.h"
30
31 /* --------------------------------------------------------------------
32 * Clocks
33 * -------------------------------------------------------------------- */
34
35 /*
36 * The peripheral clocks.
37 */
38 static struct clk pioA_clk = {
39 .name = "pioA_clk",
40 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
41 .type = CLK_TYPE_PERIPHERAL,
42 };
43 static struct clk pioB_clk = {
44 .name = "pioB_clk",
45 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
46 .type = CLK_TYPE_PERIPHERAL,
47 };
48 static struct clk pioC_clk = {
49 .name = "pioC_clk",
50 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
51 .type = CLK_TYPE_PERIPHERAL,
52 };
53 static struct clk adc_clk = {
54 .name = "adc_clk",
55 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
56 .type = CLK_TYPE_PERIPHERAL,
57 };
58 static struct clk usart0_clk = {
59 .name = "usart0_clk",
60 .pmc_mask = 1 << AT91SAM9260_ID_US0,
61 .type = CLK_TYPE_PERIPHERAL,
62 };
63 static struct clk usart1_clk = {
64 .name = "usart1_clk",
65 .pmc_mask = 1 << AT91SAM9260_ID_US1,
66 .type = CLK_TYPE_PERIPHERAL,
67 };
68 static struct clk usart2_clk = {
69 .name = "usart2_clk",
70 .pmc_mask = 1 << AT91SAM9260_ID_US2,
71 .type = CLK_TYPE_PERIPHERAL,
72 };
73 static struct clk mmc_clk = {
74 .name = "mci_clk",
75 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
76 .type = CLK_TYPE_PERIPHERAL,
77 };
78 static struct clk udc_clk = {
79 .name = "udc_clk",
80 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
81 .type = CLK_TYPE_PERIPHERAL,
82 };
83 static struct clk twi_clk = {
84 .name = "twi_clk",
85 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
86 .type = CLK_TYPE_PERIPHERAL,
87 };
88 static struct clk spi0_clk = {
89 .name = "spi0_clk",
90 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
91 .type = CLK_TYPE_PERIPHERAL,
92 };
93 static struct clk spi1_clk = {
94 .name = "spi1_clk",
95 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
96 .type = CLK_TYPE_PERIPHERAL,
97 };
98 static struct clk ssc_clk = {
99 .name = "ssc_clk",
100 .pmc_mask = 1 << AT91SAM9260_ID_SSC,
101 .type = CLK_TYPE_PERIPHERAL,
102 };
103 static struct clk tc0_clk = {
104 .name = "tc0_clk",
105 .pmc_mask = 1 << AT91SAM9260_ID_TC0,
106 .type = CLK_TYPE_PERIPHERAL,
107 };
108 static struct clk tc1_clk = {
109 .name = "tc1_clk",
110 .pmc_mask = 1 << AT91SAM9260_ID_TC1,
111 .type = CLK_TYPE_PERIPHERAL,
112 };
113 static struct clk tc2_clk = {
114 .name = "tc2_clk",
115 .pmc_mask = 1 << AT91SAM9260_ID_TC2,
116 .type = CLK_TYPE_PERIPHERAL,
117 };
118 static struct clk ohci_clk = {
119 .name = "ohci_clk",
120 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
121 .type = CLK_TYPE_PERIPHERAL,
122 };
123 static struct clk macb_clk = {
124 .name = "pclk",
125 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
126 .type = CLK_TYPE_PERIPHERAL,
127 };
128 static struct clk isi_clk = {
129 .name = "isi_clk",
130 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
131 .type = CLK_TYPE_PERIPHERAL,
132 };
133 static struct clk usart3_clk = {
134 .name = "usart3_clk",
135 .pmc_mask = 1 << AT91SAM9260_ID_US3,
136 .type = CLK_TYPE_PERIPHERAL,
137 };
138 static struct clk usart4_clk = {
139 .name = "usart4_clk",
140 .pmc_mask = 1 << AT91SAM9260_ID_US4,
141 .type = CLK_TYPE_PERIPHERAL,
142 };
143 static struct clk usart5_clk = {
144 .name = "usart5_clk",
145 .pmc_mask = 1 << AT91SAM9260_ID_US5,
146 .type = CLK_TYPE_PERIPHERAL,
147 };
148 static struct clk tc3_clk = {
149 .name = "tc3_clk",
150 .pmc_mask = 1 << AT91SAM9260_ID_TC3,
151 .type = CLK_TYPE_PERIPHERAL,
152 };
153 static struct clk tc4_clk = {
154 .name = "tc4_clk",
155 .pmc_mask = 1 << AT91SAM9260_ID_TC4,
156 .type = CLK_TYPE_PERIPHERAL,
157 };
158 static struct clk tc5_clk = {
159 .name = "tc5_clk",
160 .pmc_mask = 1 << AT91SAM9260_ID_TC5,
161 .type = CLK_TYPE_PERIPHERAL,
162 };
163
164 static struct clk *periph_clocks[] __initdata = {
165 &pioA_clk,
166 &pioB_clk,
167 &pioC_clk,
168 &adc_clk,
169 &usart0_clk,
170 &usart1_clk,
171 &usart2_clk,
172 &mmc_clk,
173 &udc_clk,
174 &twi_clk,
175 &spi0_clk,
176 &spi1_clk,
177 &ssc_clk,
178 &tc0_clk,
179 &tc1_clk,
180 &tc2_clk,
181 &ohci_clk,
182 &macb_clk,
183 &isi_clk,
184 &usart3_clk,
185 &usart4_clk,
186 &usart5_clk,
187 &tc3_clk,
188 &tc4_clk,
189 &tc5_clk,
190 // irq0 .. irq2
191 };
192
193 static struct clk_lookup periph_clocks_lookups[] = {
194 /* One additional fake clock for macb_hclk */
195 CLKDEV_CON_ID("hclk", &macb_clk),
196 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
197 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
198 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
199 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
200 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
201 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
202 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
203 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
204 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
205 /* more usart lookup table for DT entries */
206 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
207 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
209 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
210 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
211 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
212 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
213 /* more tc lookup table for DT entries */
214 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
215 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
216 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
217 CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
218 CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
219 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
220 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
221 /* fake hclk clock */
222 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
223 CLKDEV_CON_ID("pioA", &pioA_clk),
224 CLKDEV_CON_ID("pioB", &pioB_clk),
225 CLKDEV_CON_ID("pioC", &pioC_clk),
226 };
227
228 static struct clk_lookup usart_clocks_lookups[] = {
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
236 };
237
238 /*
239 * The two programmable clocks.
240 * You must configure pin multiplexing to bring these signals out.
241 */
242 static struct clk pck0 = {
243 .name = "pck0",
244 .pmc_mask = AT91_PMC_PCK0,
245 .type = CLK_TYPE_PROGRAMMABLE,
246 .id = 0,
247 };
248 static struct clk pck1 = {
249 .name = "pck1",
250 .pmc_mask = AT91_PMC_PCK1,
251 .type = CLK_TYPE_PROGRAMMABLE,
252 .id = 1,
253 };
254
at91sam9260_register_clocks(void)255 static void __init at91sam9260_register_clocks(void)
256 {
257 int i;
258
259 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
260 clk_register(periph_clocks[i]);
261
262 clkdev_add_table(periph_clocks_lookups,
263 ARRAY_SIZE(periph_clocks_lookups));
264 clkdev_add_table(usart_clocks_lookups,
265 ARRAY_SIZE(usart_clocks_lookups));
266
267 clk_register(&pck0);
268 clk_register(&pck1);
269 }
270
271 static struct clk_lookup console_clock_lookup;
272
at91sam9260_set_console_clock(int id)273 void __init at91sam9260_set_console_clock(int id)
274 {
275 if (id >= ARRAY_SIZE(usart_clocks_lookups))
276 return;
277
278 console_clock_lookup.con_id = "usart";
279 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
280 clkdev_add(&console_clock_lookup);
281 }
282
283 /* --------------------------------------------------------------------
284 * GPIO
285 * -------------------------------------------------------------------- */
286
287 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
288 {
289 .id = AT91SAM9260_ID_PIOA,
290 .regbase = AT91SAM9260_BASE_PIOA,
291 }, {
292 .id = AT91SAM9260_ID_PIOB,
293 .regbase = AT91SAM9260_BASE_PIOB,
294 }, {
295 .id = AT91SAM9260_ID_PIOC,
296 .regbase = AT91SAM9260_BASE_PIOC,
297 }
298 };
299
300 /* --------------------------------------------------------------------
301 * AT91SAM9260 processor initialization
302 * -------------------------------------------------------------------- */
303
at91sam9xe_map_io(void)304 static void __init at91sam9xe_map_io(void)
305 {
306 unsigned long sram_size;
307
308 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
309 case AT91_CIDR_SRAMSIZ_32K:
310 sram_size = 2 * SZ_16K;
311 break;
312 case AT91_CIDR_SRAMSIZ_16K:
313 default:
314 sram_size = SZ_16K;
315 }
316
317 at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
318 }
319
at91sam9260_map_io(void)320 static void __init at91sam9260_map_io(void)
321 {
322 if (cpu_is_at91sam9xe())
323 at91sam9xe_map_io();
324 else if (cpu_is_at91sam9g20())
325 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
326 else
327 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
328 }
329
at91sam9260_ioremap_registers(void)330 static void __init at91sam9260_ioremap_registers(void)
331 {
332 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
333 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
334 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
335 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
336 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
337 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
338 }
339
at91sam9260_initialize(void)340 static void __init at91sam9260_initialize(void)
341 {
342 arm_pm_idle = at91sam9_idle;
343 arm_pm_restart = at91sam9_alt_restart;
344 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
345 | (1 << AT91SAM9260_ID_IRQ2);
346
347 /* Register GPIO subsystem */
348 at91_gpio_init(at91sam9260_gpio, 3);
349 }
350
351 /* --------------------------------------------------------------------
352 * Interrupt initialization
353 * -------------------------------------------------------------------- */
354
355 /*
356 * The default interrupt priority levels (0 = lowest, 7 = highest).
357 */
358 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
359 7, /* Advanced Interrupt Controller */
360 7, /* System Peripherals */
361 1, /* Parallel IO Controller A */
362 1, /* Parallel IO Controller B */
363 1, /* Parallel IO Controller C */
364 0, /* Analog-to-Digital Converter */
365 5, /* USART 0 */
366 5, /* USART 1 */
367 5, /* USART 2 */
368 0, /* Multimedia Card Interface */
369 2, /* USB Device Port */
370 6, /* Two-Wire Interface */
371 5, /* Serial Peripheral Interface 0 */
372 5, /* Serial Peripheral Interface 1 */
373 5, /* Serial Synchronous Controller */
374 0,
375 0,
376 0, /* Timer Counter 0 */
377 0, /* Timer Counter 1 */
378 0, /* Timer Counter 2 */
379 2, /* USB Host port */
380 3, /* Ethernet */
381 0, /* Image Sensor Interface */
382 5, /* USART 3 */
383 5, /* USART 4 */
384 5, /* USART 5 */
385 0, /* Timer Counter 3 */
386 0, /* Timer Counter 4 */
387 0, /* Timer Counter 5 */
388 0, /* Advanced Interrupt Controller */
389 0, /* Advanced Interrupt Controller */
390 0, /* Advanced Interrupt Controller */
391 };
392
393 struct at91_init_soc __initdata at91sam9260_soc = {
394 .map_io = at91sam9260_map_io,
395 .default_irq_priority = at91sam9260_default_irq_priority,
396 .ioremap_registers = at91sam9260_ioremap_registers,
397 .register_clocks = at91sam9260_register_clocks,
398 .init = at91sam9260_initialize,
399 };
400