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1 /*
2  * arch/arm/mach-at91/at91sam9263.c
3  *
4  *  Copyright (C) 2007 Atmel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  */
12 
13 #include <linux/module.h>
14 
15 #include <asm/proc-fns.h>
16 #include <asm/irq.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/at91sam9263.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23 
24 #include "soc.h"
25 #include "generic.h"
26 #include "clock.h"
27 #include "sam9_smc.h"
28 
29 /* --------------------------------------------------------------------
30  *  Clocks
31  * -------------------------------------------------------------------- */
32 
33 /*
34  * The peripheral clocks.
35  */
36 static struct clk pioA_clk = {
37 	.name		= "pioA_clk",
38 	.pmc_mask	= 1 << AT91SAM9263_ID_PIOA,
39 	.type		= CLK_TYPE_PERIPHERAL,
40 };
41 static struct clk pioB_clk = {
42 	.name		= "pioB_clk",
43 	.pmc_mask	= 1 << AT91SAM9263_ID_PIOB,
44 	.type		= CLK_TYPE_PERIPHERAL,
45 };
46 static struct clk pioCDE_clk = {
47 	.name		= "pioCDE_clk",
48 	.pmc_mask	= 1 << AT91SAM9263_ID_PIOCDE,
49 	.type		= CLK_TYPE_PERIPHERAL,
50 };
51 static struct clk usart0_clk = {
52 	.name		= "usart0_clk",
53 	.pmc_mask	= 1 << AT91SAM9263_ID_US0,
54 	.type		= CLK_TYPE_PERIPHERAL,
55 };
56 static struct clk usart1_clk = {
57 	.name		= "usart1_clk",
58 	.pmc_mask	= 1 << AT91SAM9263_ID_US1,
59 	.type		= CLK_TYPE_PERIPHERAL,
60 };
61 static struct clk usart2_clk = {
62 	.name		= "usart2_clk",
63 	.pmc_mask	= 1 << AT91SAM9263_ID_US2,
64 	.type		= CLK_TYPE_PERIPHERAL,
65 };
66 static struct clk mmc0_clk = {
67 	.name		= "mci0_clk",
68 	.pmc_mask	= 1 << AT91SAM9263_ID_MCI0,
69 	.type		= CLK_TYPE_PERIPHERAL,
70 };
71 static struct clk mmc1_clk = {
72 	.name		= "mci1_clk",
73 	.pmc_mask	= 1 << AT91SAM9263_ID_MCI1,
74 	.type		= CLK_TYPE_PERIPHERAL,
75 };
76 static struct clk can_clk = {
77 	.name		= "can_clk",
78 	.pmc_mask	= 1 << AT91SAM9263_ID_CAN,
79 	.type		= CLK_TYPE_PERIPHERAL,
80 };
81 static struct clk twi_clk = {
82 	.name		= "twi_clk",
83 	.pmc_mask	= 1 << AT91SAM9263_ID_TWI,
84 	.type		= CLK_TYPE_PERIPHERAL,
85 };
86 static struct clk spi0_clk = {
87 	.name		= "spi0_clk",
88 	.pmc_mask	= 1 << AT91SAM9263_ID_SPI0,
89 	.type		= CLK_TYPE_PERIPHERAL,
90 };
91 static struct clk spi1_clk = {
92 	.name		= "spi1_clk",
93 	.pmc_mask	= 1 << AT91SAM9263_ID_SPI1,
94 	.type		= CLK_TYPE_PERIPHERAL,
95 };
96 static struct clk ssc0_clk = {
97 	.name		= "ssc0_clk",
98 	.pmc_mask	= 1 << AT91SAM9263_ID_SSC0,
99 	.type		= CLK_TYPE_PERIPHERAL,
100 };
101 static struct clk ssc1_clk = {
102 	.name		= "ssc1_clk",
103 	.pmc_mask	= 1 << AT91SAM9263_ID_SSC1,
104 	.type		= CLK_TYPE_PERIPHERAL,
105 };
106 static struct clk ac97_clk = {
107 	.name		= "ac97_clk",
108 	.pmc_mask	= 1 << AT91SAM9263_ID_AC97C,
109 	.type		= CLK_TYPE_PERIPHERAL,
110 };
111 static struct clk tcb_clk = {
112 	.name		= "tcb_clk",
113 	.pmc_mask	= 1 << AT91SAM9263_ID_TCB,
114 	.type		= CLK_TYPE_PERIPHERAL,
115 };
116 static struct clk pwm_clk = {
117 	.name		= "pwm_clk",
118 	.pmc_mask	= 1 << AT91SAM9263_ID_PWMC,
119 	.type		= CLK_TYPE_PERIPHERAL,
120 };
121 static struct clk macb_clk = {
122 	.name		= "pclk",
123 	.pmc_mask	= 1 << AT91SAM9263_ID_EMAC,
124 	.type		= CLK_TYPE_PERIPHERAL,
125 };
126 static struct clk dma_clk = {
127 	.name		= "dma_clk",
128 	.pmc_mask	= 1 << AT91SAM9263_ID_DMA,
129 	.type		= CLK_TYPE_PERIPHERAL,
130 };
131 static struct clk twodge_clk = {
132 	.name		= "2dge_clk",
133 	.pmc_mask	= 1 << AT91SAM9263_ID_2DGE,
134 	.type		= CLK_TYPE_PERIPHERAL,
135 };
136 static struct clk udc_clk = {
137 	.name		= "udc_clk",
138 	.pmc_mask	= 1 << AT91SAM9263_ID_UDP,
139 	.type		= CLK_TYPE_PERIPHERAL,
140 };
141 static struct clk isi_clk = {
142 	.name		= "isi_clk",
143 	.pmc_mask	= 1 << AT91SAM9263_ID_ISI,
144 	.type		= CLK_TYPE_PERIPHERAL,
145 };
146 static struct clk lcdc_clk = {
147 	.name		= "lcdc_clk",
148 	.pmc_mask	= 1 << AT91SAM9263_ID_LCDC,
149 	.type		= CLK_TYPE_PERIPHERAL,
150 };
151 static struct clk ohci_clk = {
152 	.name		= "ohci_clk",
153 	.pmc_mask	= 1 << AT91SAM9263_ID_UHP,
154 	.type		= CLK_TYPE_PERIPHERAL,
155 };
156 
157 static struct clk *periph_clocks[] __initdata = {
158 	&pioA_clk,
159 	&pioB_clk,
160 	&pioCDE_clk,
161 	&usart0_clk,
162 	&usart1_clk,
163 	&usart2_clk,
164 	&mmc0_clk,
165 	&mmc1_clk,
166 	&can_clk,
167 	&twi_clk,
168 	&spi0_clk,
169 	&spi1_clk,
170 	&ssc0_clk,
171 	&ssc1_clk,
172 	&ac97_clk,
173 	&tcb_clk,
174 	&pwm_clk,
175 	&macb_clk,
176 	&twodge_clk,
177 	&udc_clk,
178 	&isi_clk,
179 	&lcdc_clk,
180 	&dma_clk,
181 	&ohci_clk,
182 	// irq0 .. irq1
183 };
184 
185 static struct clk_lookup periph_clocks_lookups[] = {
186 	/* One additional fake clock for macb_hclk */
187 	CLKDEV_CON_ID("hclk", &macb_clk),
188 	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
189 	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
190 	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
191 	CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
192 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
193 	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
194 	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
195 	/* fake hclk clock */
196 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
197 	CLKDEV_CON_ID("pioA", &pioA_clk),
198 	CLKDEV_CON_ID("pioB", &pioB_clk),
199 	CLKDEV_CON_ID("pioC", &pioCDE_clk),
200 	CLKDEV_CON_ID("pioD", &pioCDE_clk),
201 	CLKDEV_CON_ID("pioE", &pioCDE_clk),
202 };
203 
204 static struct clk_lookup usart_clocks_lookups[] = {
205 	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
206 	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
207 	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
208 	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
209 };
210 
211 /*
212  * The four programmable clocks.
213  * You must configure pin multiplexing to bring these signals out.
214  */
215 static struct clk pck0 = {
216 	.name		= "pck0",
217 	.pmc_mask	= AT91_PMC_PCK0,
218 	.type		= CLK_TYPE_PROGRAMMABLE,
219 	.id		= 0,
220 };
221 static struct clk pck1 = {
222 	.name		= "pck1",
223 	.pmc_mask	= AT91_PMC_PCK1,
224 	.type		= CLK_TYPE_PROGRAMMABLE,
225 	.id		= 1,
226 };
227 static struct clk pck2 = {
228 	.name		= "pck2",
229 	.pmc_mask	= AT91_PMC_PCK2,
230 	.type		= CLK_TYPE_PROGRAMMABLE,
231 	.id		= 2,
232 };
233 static struct clk pck3 = {
234 	.name		= "pck3",
235 	.pmc_mask	= AT91_PMC_PCK3,
236 	.type		= CLK_TYPE_PROGRAMMABLE,
237 	.id		= 3,
238 };
239 
at91sam9263_register_clocks(void)240 static void __init at91sam9263_register_clocks(void)
241 {
242 	int i;
243 
244 	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
245 		clk_register(periph_clocks[i]);
246 
247 	clkdev_add_table(periph_clocks_lookups,
248 			 ARRAY_SIZE(periph_clocks_lookups));
249 	clkdev_add_table(usart_clocks_lookups,
250 			 ARRAY_SIZE(usart_clocks_lookups));
251 
252 	clk_register(&pck0);
253 	clk_register(&pck1);
254 	clk_register(&pck2);
255 	clk_register(&pck3);
256 }
257 
258 static struct clk_lookup console_clock_lookup;
259 
at91sam9263_set_console_clock(int id)260 void __init at91sam9263_set_console_clock(int id)
261 {
262 	if (id >= ARRAY_SIZE(usart_clocks_lookups))
263 		return;
264 
265 	console_clock_lookup.con_id = "usart";
266 	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
267 	clkdev_add(&console_clock_lookup);
268 }
269 
270 /* --------------------------------------------------------------------
271  *  GPIO
272  * -------------------------------------------------------------------- */
273 
274 static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
275 	{
276 		.id		= AT91SAM9263_ID_PIOA,
277 		.regbase	= AT91SAM9263_BASE_PIOA,
278 	}, {
279 		.id		= AT91SAM9263_ID_PIOB,
280 		.regbase	= AT91SAM9263_BASE_PIOB,
281 	}, {
282 		.id		= AT91SAM9263_ID_PIOCDE,
283 		.regbase	= AT91SAM9263_BASE_PIOC,
284 	}, {
285 		.id		= AT91SAM9263_ID_PIOCDE,
286 		.regbase	= AT91SAM9263_BASE_PIOD,
287 	}, {
288 		.id		= AT91SAM9263_ID_PIOCDE,
289 		.regbase	= AT91SAM9263_BASE_PIOE,
290 	}
291 };
292 
293 /* --------------------------------------------------------------------
294  *  AT91SAM9263 processor initialization
295  * -------------------------------------------------------------------- */
296 
at91sam9263_map_io(void)297 static void __init at91sam9263_map_io(void)
298 {
299 	at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
300 	at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
301 }
302 
at91sam9263_ioremap_registers(void)303 static void __init at91sam9263_ioremap_registers(void)
304 {
305 	at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
306 	at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
307 	at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
308 	at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
309 	at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
310 	at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
311 	at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
312 	at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
313 }
314 
at91sam9263_initialize(void)315 static void __init at91sam9263_initialize(void)
316 {
317 	arm_pm_idle = at91sam9_idle;
318 	arm_pm_restart = at91sam9_alt_restart;
319 	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
320 
321 	/* Register GPIO subsystem */
322 	at91_gpio_init(at91sam9263_gpio, 5);
323 }
324 
325 /* --------------------------------------------------------------------
326  *  Interrupt initialization
327  * -------------------------------------------------------------------- */
328 
329 /*
330  * The default interrupt priority levels (0 = lowest, 7 = highest).
331  */
332 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
333 	7,	/* Advanced Interrupt Controller (FIQ) */
334 	7,	/* System Peripherals */
335 	1,	/* Parallel IO Controller A */
336 	1,	/* Parallel IO Controller B */
337 	1,	/* Parallel IO Controller C, D and E */
338 	0,
339 	0,
340 	5,	/* USART 0 */
341 	5,	/* USART 1 */
342 	5,	/* USART 2 */
343 	0,	/* Multimedia Card Interface 0 */
344 	0,	/* Multimedia Card Interface 1 */
345 	3,	/* CAN */
346 	6,	/* Two-Wire Interface */
347 	5,	/* Serial Peripheral Interface 0 */
348 	5,	/* Serial Peripheral Interface 1 */
349 	4,	/* Serial Synchronous Controller 0 */
350 	4,	/* Serial Synchronous Controller 1 */
351 	5,	/* AC97 Controller */
352 	0,	/* Timer Counter 0, 1 and 2 */
353 	0,	/* Pulse Width Modulation Controller */
354 	3,	/* Ethernet */
355 	0,
356 	0,	/* 2D Graphic Engine */
357 	2,	/* USB Device Port */
358 	0,	/* Image Sensor Interface */
359 	3,	/* LDC Controller */
360 	0,	/* DMA Controller */
361 	0,
362 	2,	/* USB Host port */
363 	0,	/* Advanced Interrupt Controller (IRQ0) */
364 	0,	/* Advanced Interrupt Controller (IRQ1) */
365 };
366 
367 struct at91_init_soc __initdata at91sam9263_soc = {
368 	.map_io = at91sam9263_map_io,
369 	.default_irq_priority = at91sam9263_default_irq_priority,
370 	.ioremap_registers = at91sam9263_ioremap_registers,
371 	.register_clocks = at91sam9263_register_clocks,
372 	.init = at91sam9263_initialize,
373 };
374