1 /*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12 #include <linux/module.h>
13
14 #include <asm/proc-fns.h>
15 #include <asm/irq.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <asm/system_misc.h>
19 #include <mach/cpu.h>
20 #include <mach/at91_dbgu.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91_pmc.h>
23 #include <mach/at91_rstc.h>
24
25 #include "soc.h"
26 #include "generic.h"
27 #include "clock.h"
28 #include "sam9_smc.h"
29
30 /* --------------------------------------------------------------------
31 * Clocks
32 * -------------------------------------------------------------------- */
33
34 /*
35 * The peripheral clocks.
36 */
37 static struct clk pioA_clk = {
38 .name = "pioA_clk",
39 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
40 .type = CLK_TYPE_PERIPHERAL,
41 };
42 static struct clk pioB_clk = {
43 .name = "pioB_clk",
44 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
45 .type = CLK_TYPE_PERIPHERAL,
46 };
47 static struct clk pioC_clk = {
48 .name = "pioC_clk",
49 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
50 .type = CLK_TYPE_PERIPHERAL,
51 };
52 static struct clk pioD_clk = {
53 .name = "pioD_clk",
54 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
55 .type = CLK_TYPE_PERIPHERAL,
56 };
57 static struct clk usart0_clk = {
58 .name = "usart0_clk",
59 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
60 .type = CLK_TYPE_PERIPHERAL,
61 };
62 static struct clk usart1_clk = {
63 .name = "usart1_clk",
64 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
65 .type = CLK_TYPE_PERIPHERAL,
66 };
67 static struct clk usart2_clk = {
68 .name = "usart2_clk",
69 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
70 .type = CLK_TYPE_PERIPHERAL,
71 };
72 static struct clk usart3_clk = {
73 .name = "usart3_clk",
74 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
75 .type = CLK_TYPE_PERIPHERAL,
76 };
77 static struct clk mmc_clk = {
78 .name = "mci_clk",
79 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
80 .type = CLK_TYPE_PERIPHERAL,
81 };
82 static struct clk twi0_clk = {
83 .name = "twi0_clk",
84 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
85 .type = CLK_TYPE_PERIPHERAL,
86 };
87 static struct clk twi1_clk = {
88 .name = "twi1_clk",
89 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
90 .type = CLK_TYPE_PERIPHERAL,
91 };
92 static struct clk spi_clk = {
93 .name = "spi_clk",
94 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
95 .type = CLK_TYPE_PERIPHERAL,
96 };
97 static struct clk ssc0_clk = {
98 .name = "ssc0_clk",
99 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
100 .type = CLK_TYPE_PERIPHERAL,
101 };
102 static struct clk ssc1_clk = {
103 .name = "ssc1_clk",
104 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
105 .type = CLK_TYPE_PERIPHERAL,
106 };
107 static struct clk tc0_clk = {
108 .name = "tc0_clk",
109 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
110 .type = CLK_TYPE_PERIPHERAL,
111 };
112 static struct clk tc1_clk = {
113 .name = "tc1_clk",
114 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
115 .type = CLK_TYPE_PERIPHERAL,
116 };
117 static struct clk tc2_clk = {
118 .name = "tc2_clk",
119 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
120 .type = CLK_TYPE_PERIPHERAL,
121 };
122 static struct clk pwm_clk = {
123 .name = "pwm_clk",
124 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
125 .type = CLK_TYPE_PERIPHERAL,
126 };
127 static struct clk tsc_clk = {
128 .name = "tsc_clk",
129 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
130 .type = CLK_TYPE_PERIPHERAL,
131 };
132 static struct clk dma_clk = {
133 .name = "dma_clk",
134 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
135 .type = CLK_TYPE_PERIPHERAL,
136 };
137 static struct clk udphs_clk = {
138 .name = "udphs_clk",
139 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
140 .type = CLK_TYPE_PERIPHERAL,
141 };
142 static struct clk lcdc_clk = {
143 .name = "lcdc_clk",
144 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
145 .type = CLK_TYPE_PERIPHERAL,
146 };
147 static struct clk ac97_clk = {
148 .name = "ac97_clk",
149 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
150 .type = CLK_TYPE_PERIPHERAL,
151 };
152
153 static struct clk *periph_clocks[] __initdata = {
154 &pioA_clk,
155 &pioB_clk,
156 &pioC_clk,
157 &pioD_clk,
158 &usart0_clk,
159 &usart1_clk,
160 &usart2_clk,
161 &usart3_clk,
162 &mmc_clk,
163 &twi0_clk,
164 &twi1_clk,
165 &spi_clk,
166 &ssc0_clk,
167 &ssc1_clk,
168 &tc0_clk,
169 &tc1_clk,
170 &tc2_clk,
171 &pwm_clk,
172 &tsc_clk,
173 &dma_clk,
174 &udphs_clk,
175 &lcdc_clk,
176 &ac97_clk,
177 // irq0
178 };
179
180 static struct clk_lookup periph_clocks_lookups[] = {
181 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
182 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
183 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
184 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
185 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
186 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
187 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
188 CLKDEV_CON_ID("pioA", &pioA_clk),
189 CLKDEV_CON_ID("pioB", &pioB_clk),
190 CLKDEV_CON_ID("pioC", &pioC_clk),
191 CLKDEV_CON_ID("pioD", &pioD_clk),
192 };
193
194 static struct clk_lookup usart_clocks_lookups[] = {
195 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
196 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
197 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
198 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
199 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
200 };
201
202 /*
203 * The two programmable clocks.
204 * You must configure pin multiplexing to bring these signals out.
205 */
206 static struct clk pck0 = {
207 .name = "pck0",
208 .pmc_mask = AT91_PMC_PCK0,
209 .type = CLK_TYPE_PROGRAMMABLE,
210 .id = 0,
211 };
212 static struct clk pck1 = {
213 .name = "pck1",
214 .pmc_mask = AT91_PMC_PCK1,
215 .type = CLK_TYPE_PROGRAMMABLE,
216 .id = 1,
217 };
218
at91sam9rl_register_clocks(void)219 static void __init at91sam9rl_register_clocks(void)
220 {
221 int i;
222
223 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
224 clk_register(periph_clocks[i]);
225
226 clkdev_add_table(periph_clocks_lookups,
227 ARRAY_SIZE(periph_clocks_lookups));
228 clkdev_add_table(usart_clocks_lookups,
229 ARRAY_SIZE(usart_clocks_lookups));
230
231 clk_register(&pck0);
232 clk_register(&pck1);
233 }
234
235 static struct clk_lookup console_clock_lookup;
236
at91sam9rl_set_console_clock(int id)237 void __init at91sam9rl_set_console_clock(int id)
238 {
239 if (id >= ARRAY_SIZE(usart_clocks_lookups))
240 return;
241
242 console_clock_lookup.con_id = "usart";
243 console_clock_lookup.clk = usart_clocks_lookups[id].clk;
244 clkdev_add(&console_clock_lookup);
245 }
246
247 /* --------------------------------------------------------------------
248 * GPIO
249 * -------------------------------------------------------------------- */
250
251 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
252 {
253 .id = AT91SAM9RL_ID_PIOA,
254 .regbase = AT91SAM9RL_BASE_PIOA,
255 }, {
256 .id = AT91SAM9RL_ID_PIOB,
257 .regbase = AT91SAM9RL_BASE_PIOB,
258 }, {
259 .id = AT91SAM9RL_ID_PIOC,
260 .regbase = AT91SAM9RL_BASE_PIOC,
261 }, {
262 .id = AT91SAM9RL_ID_PIOD,
263 .regbase = AT91SAM9RL_BASE_PIOD,
264 }
265 };
266
267 /* --------------------------------------------------------------------
268 * AT91SAM9RL processor initialization
269 * -------------------------------------------------------------------- */
270
at91sam9rl_map_io(void)271 static void __init at91sam9rl_map_io(void)
272 {
273 unsigned long sram_size;
274
275 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
276 case AT91_CIDR_SRAMSIZ_32K:
277 sram_size = 2 * SZ_16K;
278 break;
279 case AT91_CIDR_SRAMSIZ_16K:
280 default:
281 sram_size = SZ_16K;
282 }
283
284 /* Map SRAM */
285 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
286 }
287
at91sam9rl_ioremap_registers(void)288 static void __init at91sam9rl_ioremap_registers(void)
289 {
290 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
291 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
292 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
293 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
294 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
295 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
296 }
297
at91sam9rl_initialize(void)298 static void __init at91sam9rl_initialize(void)
299 {
300 arm_pm_idle = at91sam9_idle;
301 arm_pm_restart = at91sam9_alt_restart;
302 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
303
304 /* Register GPIO subsystem */
305 at91_gpio_init(at91sam9rl_gpio, 4);
306 }
307
308 /* --------------------------------------------------------------------
309 * Interrupt initialization
310 * -------------------------------------------------------------------- */
311
312 /*
313 * The default interrupt priority levels (0 = lowest, 7 = highest).
314 */
315 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
316 7, /* Advanced Interrupt Controller */
317 7, /* System Peripherals */
318 1, /* Parallel IO Controller A */
319 1, /* Parallel IO Controller B */
320 1, /* Parallel IO Controller C */
321 1, /* Parallel IO Controller D */
322 5, /* USART 0 */
323 5, /* USART 1 */
324 5, /* USART 2 */
325 5, /* USART 3 */
326 0, /* Multimedia Card Interface */
327 6, /* Two-Wire Interface 0 */
328 6, /* Two-Wire Interface 1 */
329 5, /* Serial Peripheral Interface */
330 4, /* Serial Synchronous Controller 0 */
331 4, /* Serial Synchronous Controller 1 */
332 0, /* Timer Counter 0 */
333 0, /* Timer Counter 1 */
334 0, /* Timer Counter 2 */
335 0,
336 0, /* Touch Screen Controller */
337 0, /* DMA Controller */
338 2, /* USB Device High speed port */
339 2, /* LCD Controller */
340 6, /* AC97 Controller */
341 0,
342 0,
343 0,
344 0,
345 0,
346 0,
347 0, /* Advanced Interrupt Controller */
348 };
349
350 struct at91_init_soc __initdata at91sam9rl_soc = {
351 .map_io = at91sam9rl_map_io,
352 .default_irq_priority = at91sam9rl_default_irq_priority,
353 .ioremap_registers = at91sam9rl_ioremap_registers,
354 .register_clocks = at91sam9rl_register_clocks,
355 .init = at91sam9rl_initialize,
356 };
357