1 /*
2 * linux/arch/arm/mach-at91/board-yl-9200.c
3 *
4 * Adapted from various board files in arch/arm/mach-at91
5 *
6 * Modifications for YL-9200 platform:
7 * Copyright (C) 2007 S. Birtles
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/types.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
27 #include <linux/mm.h>
28 #include <linux/module.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/platform_device.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/ads7846.h>
33 #include <linux/mtd/physmap.h>
34 #include <linux/gpio_keys.h>
35 #include <linux/input.h>
36
37 #include <asm/setup.h>
38 #include <asm/mach-types.h>
39 #include <asm/irq.h>
40
41 #include <asm/mach/arch.h>
42 #include <asm/mach/map.h>
43 #include <asm/mach/irq.h>
44
45 #include <mach/hardware.h>
46 #include <mach/board.h>
47 #include <mach/at91rm9200_mc.h>
48 #include <mach/at91_ramc.h>
49 #include <mach/cpu.h>
50
51 #include "generic.h"
52
53
yl9200_init_early(void)54 static void __init yl9200_init_early(void)
55 {
56 /* Set cpu type: PQFP */
57 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
58
59 /* Initialize processor: 18.432 MHz crystal */
60 at91_initialize(18432000);
61
62 /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
63 at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
64
65 /* DBGU on ttyS0. (Rx & Tx only) */
66 at91_register_uart(0, 0, 0);
67
68 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
69 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
70 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
71 | ATMEL_UART_RI);
72
73 /* USART0 on ttyS2. (Rx & Tx only to JP3) */
74 at91_register_uart(AT91RM9200_ID_US0, 2, 0);
75
76 /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
77 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
78
79 /* set serial console to ttyS0 (ie, DBGU) */
80 at91_set_serial_console(0);
81 }
82
83 /*
84 * LEDs
85 */
86 static struct gpio_led yl9200_leds[] = {
87 { /* D2 */
88 .name = "led2",
89 .gpio = AT91_PIN_PB17,
90 .active_low = 1,
91 .default_trigger = "timer",
92 },
93 { /* D3 */
94 .name = "led3",
95 .gpio = AT91_PIN_PB16,
96 .active_low = 1,
97 .default_trigger = "heartbeat",
98 },
99 { /* D4 */
100 .name = "led4",
101 .gpio = AT91_PIN_PB15,
102 .active_low = 1,
103 },
104 { /* D5 */
105 .name = "led5",
106 .gpio = AT91_PIN_PB8,
107 .active_low = 1,
108 }
109 };
110
111 /*
112 * Ethernet
113 */
114 static struct macb_platform_data __initdata yl9200_eth_data = {
115 .phy_irq_pin = AT91_PIN_PB28,
116 .is_rmii = 1,
117 };
118
119 /*
120 * USB Host
121 */
122 static struct at91_usbh_data __initdata yl9200_usbh_data = {
123 .ports = 1, /* PQFP version of AT91RM9200 */
124 .vbus_pin = {-EINVAL, -EINVAL},
125 .overcurrent_pin= {-EINVAL, -EINVAL},
126 };
127
128 /*
129 * USB Device
130 */
131 static struct at91_udc_data __initdata yl9200_udc_data = {
132 .pullup_pin = AT91_PIN_PC4,
133 .vbus_pin = AT91_PIN_PC5,
134 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
135
136 };
137
138 /*
139 * MMC
140 */
141 static struct at91_mmc_data __initdata yl9200_mmc_data = {
142 .det_pin = AT91_PIN_PB9,
143 .wire4 = 1,
144 .wp_pin = -EINVAL,
145 .vcc_pin = -EINVAL,
146 };
147
148 /*
149 * NAND Flash
150 */
151 static struct mtd_partition __initdata yl9200_nand_partition[] = {
152 {
153 .name = "AT91 NAND partition 1, boot",
154 .offset = 0,
155 .size = SZ_256K
156 },
157 {
158 .name = "AT91 NAND partition 2, kernel",
159 .offset = MTDPART_OFS_NXTBLK,
160 .size = (2 * SZ_1M) - SZ_256K
161 },
162 {
163 .name = "AT91 NAND partition 3, filesystem",
164 .offset = MTDPART_OFS_NXTBLK,
165 .size = 14 * SZ_1M
166 },
167 {
168 .name = "AT91 NAND partition 4, storage",
169 .offset = MTDPART_OFS_NXTBLK,
170 .size = SZ_16M
171 },
172 {
173 .name = "AT91 NAND partition 5, ext-fs",
174 .offset = MTDPART_OFS_NXTBLK,
175 .size = SZ_32M
176 }
177 };
178
179 static struct atmel_nand_data __initdata yl9200_nand_data = {
180 .ale = 6,
181 .cle = 7,
182 .det_pin = -EINVAL,
183 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
184 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
185 .ecc_mode = NAND_ECC_SOFT,
186 .parts = yl9200_nand_partition,
187 .num_parts = ARRAY_SIZE(yl9200_nand_partition),
188 };
189
190 /*
191 * NOR Flash
192 */
193 #define YL9200_FLASH_BASE AT91_CHIPSELECT_0
194 #define YL9200_FLASH_SIZE SZ_16M
195
196 static struct mtd_partition yl9200_flash_partitions[] = {
197 {
198 .name = "Bootloader",
199 .offset = 0,
200 .size = SZ_256K,
201 .mask_flags = MTD_WRITEABLE, /* force read-only */
202 },
203 {
204 .name = "Kernel",
205 .offset = MTDPART_OFS_NXTBLK,
206 .size = (2 * SZ_1M) - SZ_256K
207 },
208 {
209 .name = "Filesystem",
210 .offset = MTDPART_OFS_NXTBLK,
211 .size = MTDPART_SIZ_FULL
212 }
213 };
214
215 static struct physmap_flash_data yl9200_flash_data = {
216 .width = 2,
217 .parts = yl9200_flash_partitions,
218 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
219 };
220
221 static struct resource yl9200_flash_resources[] = {
222 {
223 .start = YL9200_FLASH_BASE,
224 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
225 .flags = IORESOURCE_MEM,
226 }
227 };
228
229 static struct platform_device yl9200_flash = {
230 .name = "physmap-flash",
231 .id = 0,
232 .dev = {
233 .platform_data = &yl9200_flash_data,
234 },
235 .resource = yl9200_flash_resources,
236 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
237 };
238
239 /*
240 * I2C (TWI)
241 */
242 static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
243 { /* EEPROM */
244 I2C_BOARD_INFO("24c128", 0x50),
245 }
246 };
247
248 /*
249 * GPIO Buttons
250 */
251 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
252 static struct gpio_keys_button yl9200_buttons[] = {
253 {
254 .gpio = AT91_PIN_PA24,
255 .code = BTN_2,
256 .desc = "SW2",
257 .active_low = 1,
258 .wakeup = 1,
259 },
260 {
261 .gpio = AT91_PIN_PB1,
262 .code = BTN_3,
263 .desc = "SW3",
264 .active_low = 1,
265 .wakeup = 1,
266 },
267 {
268 .gpio = AT91_PIN_PB2,
269 .code = BTN_4,
270 .desc = "SW4",
271 .active_low = 1,
272 .wakeup = 1,
273 },
274 {
275 .gpio = AT91_PIN_PB6,
276 .code = BTN_5,
277 .desc = "SW5",
278 .active_low = 1,
279 .wakeup = 1,
280 }
281 };
282
283 static struct gpio_keys_platform_data yl9200_button_data = {
284 .buttons = yl9200_buttons,
285 .nbuttons = ARRAY_SIZE(yl9200_buttons),
286 };
287
288 static struct platform_device yl9200_button_device = {
289 .name = "gpio-keys",
290 .id = -1,
291 .num_resources = 0,
292 .dev = {
293 .platform_data = &yl9200_button_data,
294 }
295 };
296
yl9200_add_device_buttons(void)297 static void __init yl9200_add_device_buttons(void)
298 {
299 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
300 at91_set_deglitch(AT91_PIN_PA24, 1);
301 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
302 at91_set_deglitch(AT91_PIN_PB1, 1);
303 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
304 at91_set_deglitch(AT91_PIN_PB2, 1);
305 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
306 at91_set_deglitch(AT91_PIN_PB6, 1);
307
308 /* Enable buttons (Sheet 5) */
309 at91_set_gpio_output(AT91_PIN_PB7, 1);
310
311 platform_device_register(&yl9200_button_device);
312 }
313 #else
yl9200_add_device_buttons(void)314 static void __init yl9200_add_device_buttons(void) {}
315 #endif
316
317 /*
318 * Touchscreen
319 */
320 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
ads7843_pendown_state(void)321 static int ads7843_pendown_state(void)
322 {
323 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
324 }
325
326 static struct ads7846_platform_data ads_info = {
327 .model = 7843,
328 .x_min = 150,
329 .x_max = 3830,
330 .y_min = 190,
331 .y_max = 3830,
332 .vref_delay_usecs = 100,
333
334 /* For a 8" touch-screen */
335 // .x_plate_ohms = 603,
336 // .y_plate_ohms = 332,
337
338 /* For a 10.4" touch-screen */
339 // .x_plate_ohms = 611,
340 // .y_plate_ohms = 325,
341
342 .x_plate_ohms = 576,
343 .y_plate_ohms = 366,
344
345 .pressure_max = 15000, /* generally nonsense on the 7843 */
346 .debounce_max = 1,
347 .debounce_rep = 0,
348 .debounce_tol = (~0),
349 .get_pendown_state = ads7843_pendown_state,
350 };
351
yl9200_add_device_ts(void)352 static void __init yl9200_add_device_ts(void)
353 {
354 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
355 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
356 }
357 #else
yl9200_add_device_ts(void)358 static void __init yl9200_add_device_ts(void) {}
359 #endif
360
361 /*
362 * SPI devices
363 */
364 static struct spi_board_info yl9200_spi_devices[] = {
365 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
366 { /* Touchscreen */
367 .modalias = "ads7846",
368 .chip_select = 0,
369 .max_speed_hz = 5000 * 26,
370 .platform_data = &ads_info,
371 .irq = AT91_PIN_PB11,
372 },
373 #endif
374 { /* CAN */
375 .modalias = "mcp2510",
376 .chip_select = 1,
377 .max_speed_hz = 25000 * 26,
378 .irq = AT91_PIN_PC0,
379 }
380 };
381
382 /*
383 * LCD / VGA
384 *
385 * EPSON S1D13806 FB (discontinued chip)
386 * EPSON S1D13506 FB
387 */
388 #if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
389 #include <video/s1d13xxxfb.h>
390
391
yl9200_init_video(void)392 static void yl9200_init_video(void)
393 {
394 /* NWAIT Signal */
395 at91_set_A_periph(AT91_PIN_PC6, 0);
396
397 /* Initialization of the Static Memory Controller for Chip Select 2 */
398 at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
399 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
400 | AT91_SMC_TDF_(0x100) /* float time */
401 );
402 }
403
404 static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
405 {
406 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
407 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
408 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
409 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
410 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
411 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
412 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
413 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
414 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
415 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
416 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
417 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
418 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
419 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
420 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
421 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
422 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
423 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
424 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
425 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
426 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
427 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
428 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
429 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
430 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
431 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
432 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
433 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
434 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
435 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
436 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
437 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
438 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
439 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
440 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
441 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
442 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
443 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
444 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
445 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
446 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
447 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
448 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
449 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
450 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
451 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
452 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
453 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
454 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
455 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
456 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
457 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
458 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
459 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
460 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
461 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
462 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
463 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
464 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
465 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
466 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
467 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
468 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
469 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
470 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
471 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
472 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
473 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
474 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
475 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
476 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
477 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
478 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
479 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
480 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
481 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
482 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
483 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
484 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
485 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
486 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
487 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
488 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
489 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
490 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
491 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
492 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
493 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
494 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
495 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
496 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
497 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
498 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
499 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
500 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
501 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
502 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
503 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
504 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
505 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
506 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
507 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
508 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
509 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
510 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
511 };
512
513 static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
514 .initregs = yl9200_s1dfb_initregs,
515 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
516 .platform_init_video = yl9200_init_video,
517 };
518
519 #define YL9200_FB_REG_BASE AT91_CHIPSELECT_7
520 #define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M
521 #define YL9200_FB_VMEM_SIZE SZ_2M
522
523 static struct resource yl9200_s1dfb_resource[] = {
524 [0] = { /* video mem */
525 .name = "s1d13xxxfb memory",
526 .start = YL9200_FB_VMEM_BASE,
527 .end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
528 .flags = IORESOURCE_MEM,
529 },
530 [1] = { /* video registers */
531 .name = "s1d13xxxfb registers",
532 .start = YL9200_FB_REG_BASE,
533 .end = YL9200_FB_REG_BASE + SZ_512 -1,
534 .flags = IORESOURCE_MEM,
535 },
536 };
537
538 static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
539
540 static struct platform_device yl9200_s1dfb_device = {
541 .name = "s1d13806fb",
542 .id = -1,
543 .dev = {
544 .dma_mask = &s1dfb_dmamask,
545 .coherent_dma_mask = DMA_BIT_MASK(32),
546 .platform_data = &yl9200_s1dfb_pdata,
547 },
548 .resource = yl9200_s1dfb_resource,
549 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
550 };
551
yl9200_add_device_video(void)552 void __init yl9200_add_device_video(void)
553 {
554 platform_device_register(&yl9200_s1dfb_device);
555 }
556 #else
yl9200_add_device_video(void)557 void __init yl9200_add_device_video(void) {}
558 #endif
559
560
yl9200_board_init(void)561 static void __init yl9200_board_init(void)
562 {
563 /* Serial */
564 at91_add_device_serial();
565 /* Ethernet */
566 at91_add_device_eth(&yl9200_eth_data);
567 /* USB Host */
568 at91_add_device_usbh(&yl9200_usbh_data);
569 /* USB Device */
570 at91_add_device_udc(&yl9200_udc_data);
571 /* I2C */
572 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
573 /* MMC */
574 at91_add_device_mmc(0, &yl9200_mmc_data);
575 /* NAND */
576 at91_add_device_nand(&yl9200_nand_data);
577 /* NOR Flash */
578 platform_device_register(&yl9200_flash);
579 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
580 /* SPI */
581 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
582 /* Touchscreen */
583 yl9200_add_device_ts();
584 #endif
585 /* LEDs. */
586 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
587 /* Push Buttons */
588 yl9200_add_device_buttons();
589 /* VGA */
590 yl9200_add_device_video();
591 }
592
593 MACHINE_START(YL9200, "uCdragon YL-9200")
594 /* Maintainer: S.Birtles */
595 .timer = &at91rm9200_timer,
596 .map_io = at91_map_io,
597 .init_early = yl9200_init_early,
598 .init_irq = at91_init_irq_default,
599 .init_machine = yl9200_board_init,
600 MACHINE_END
601