1 /* 2 * arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h 3 * 4 * Copyright (C) 2007 Atmel Corporation 5 * 6 * Memory Controllers (MATRIX, EBI) - System peripherals registers. 7 * Based on AT91SAM9RL datasheet revision A. (Preliminary) 8 * 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License. See the file COPYING in the main directory of this archive for 11 * more details. 12 */ 13 14 #ifndef AT91SAM9RL_MATRIX_H 15 #define AT91SAM9RL_MATRIX_H 16 17 #define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ 18 #define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ 19 #define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ 20 #define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ 21 #define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ 22 #define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ 23 #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 24 #define AT91_MATRIX_ULBT_INFINITE (0 << 0) 25 #define AT91_MATRIX_ULBT_SINGLE (1 << 0) 26 #define AT91_MATRIX_ULBT_FOUR (2 << 0) 27 #define AT91_MATRIX_ULBT_EIGHT (3 << 0) 28 #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 29 30 #define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ 31 #define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ 32 #define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ 33 #define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ 34 #define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ 35 #define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */ 36 #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 37 #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 38 #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 39 #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 40 #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 41 #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ 42 #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ 43 #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 44 #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 45 46 #define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ 47 #define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ 48 #define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ 49 #define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ 50 #define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ 51 #define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */ 52 #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 53 #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 54 #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 55 #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ 56 #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 57 #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 58 59 #define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ 60 #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 61 #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 62 #define AT91_MATRIX_RCB2 (1 << 2) 63 #define AT91_MATRIX_RCB3 (1 << 3) 64 #define AT91_MATRIX_RCB4 (1 << 4) 65 #define AT91_MATRIX_RCB5 (1 << 5) 66 67 #define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */ 68 #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 69 #define AT91_MATRIX_ITCM_0 (0 << 0) 70 #define AT91_MATRIX_ITCM_16 (5 << 0) 71 #define AT91_MATRIX_ITCM_32 (6 << 0) 72 #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ 73 #define AT91_MATRIX_DTCM_0 (0 << 4) 74 #define AT91_MATRIX_DTCM_16 (5 << 4) 75 #define AT91_MATRIX_DTCM_32 (6 << 4) 76 77 #define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */ 78 #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 79 #define AT91_MATRIX_CS1A_SMC (0 << 1) 80 #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 81 #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ 82 #define AT91_MATRIX_CS3A_SMC (0 << 3) 83 #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) 84 #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ 85 #define AT91_MATRIX_CS4A_SMC (0 << 4) 86 #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) 87 #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ 88 #define AT91_MATRIX_CS5A_SMC (0 << 5) 89 #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 90 #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ 91 #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ 92 #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) 93 #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) 94 95 96 #endif 97