1 /* linux/arch/arm/mach-exynos4/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 #include <linux/dma-mapping.h>
25 #include <linux/amba/bus.h>
26 #include <linux/amba/pl330.h>
27 #include <linux/of.h>
28
29 #include <asm/irq.h>
30 #include <plat/devs.h>
31 #include <plat/irqs.h>
32 #include <plat/cpu.h>
33
34 #include <mach/map.h>
35 #include <mach/irqs.h>
36 #include <mach/dma.h>
37
38 static u8 exynos4210_pdma0_peri[] = {
39 DMACH_PCM0_RX,
40 DMACH_PCM0_TX,
41 DMACH_PCM2_RX,
42 DMACH_PCM2_TX,
43 DMACH_MSM_REQ0,
44 DMACH_MSM_REQ2,
45 DMACH_SPI0_RX,
46 DMACH_SPI0_TX,
47 DMACH_SPI2_RX,
48 DMACH_SPI2_TX,
49 DMACH_I2S0S_TX,
50 DMACH_I2S0_RX,
51 DMACH_I2S0_TX,
52 DMACH_I2S2_RX,
53 DMACH_I2S2_TX,
54 DMACH_UART0_RX,
55 DMACH_UART0_TX,
56 DMACH_UART2_RX,
57 DMACH_UART2_TX,
58 DMACH_UART4_RX,
59 DMACH_UART4_TX,
60 DMACH_SLIMBUS0_RX,
61 DMACH_SLIMBUS0_TX,
62 DMACH_SLIMBUS2_RX,
63 DMACH_SLIMBUS2_TX,
64 DMACH_SLIMBUS4_RX,
65 DMACH_SLIMBUS4_TX,
66 DMACH_AC97_MICIN,
67 DMACH_AC97_PCMIN,
68 DMACH_AC97_PCMOUT,
69 };
70
71 static u8 exynos4212_pdma0_peri[] = {
72 DMACH_PCM0_RX,
73 DMACH_PCM0_TX,
74 DMACH_PCM2_RX,
75 DMACH_PCM2_TX,
76 DMACH_MIPI_HSI0,
77 DMACH_MIPI_HSI1,
78 DMACH_SPI0_RX,
79 DMACH_SPI0_TX,
80 DMACH_SPI2_RX,
81 DMACH_SPI2_TX,
82 DMACH_I2S0S_TX,
83 DMACH_I2S0_RX,
84 DMACH_I2S0_TX,
85 DMACH_I2S2_RX,
86 DMACH_I2S2_TX,
87 DMACH_UART0_RX,
88 DMACH_UART0_TX,
89 DMACH_UART2_RX,
90 DMACH_UART2_TX,
91 DMACH_UART4_RX,
92 DMACH_UART4_TX,
93 DMACH_SLIMBUS0_RX,
94 DMACH_SLIMBUS0_TX,
95 DMACH_SLIMBUS2_RX,
96 DMACH_SLIMBUS2_TX,
97 DMACH_SLIMBUS4_RX,
98 DMACH_SLIMBUS4_TX,
99 DMACH_AC97_MICIN,
100 DMACH_AC97_PCMIN,
101 DMACH_AC97_PCMOUT,
102 DMACH_MIPI_HSI4,
103 DMACH_MIPI_HSI5,
104 };
105
106 struct dma_pl330_platdata exynos4_pdma0_pdata;
107
108 static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
109 EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
110
111 static u8 exynos4210_pdma1_peri[] = {
112 DMACH_PCM0_RX,
113 DMACH_PCM0_TX,
114 DMACH_PCM1_RX,
115 DMACH_PCM1_TX,
116 DMACH_MSM_REQ1,
117 DMACH_MSM_REQ3,
118 DMACH_SPI1_RX,
119 DMACH_SPI1_TX,
120 DMACH_I2S0S_TX,
121 DMACH_I2S0_RX,
122 DMACH_I2S0_TX,
123 DMACH_I2S1_RX,
124 DMACH_I2S1_TX,
125 DMACH_UART0_RX,
126 DMACH_UART0_TX,
127 DMACH_UART1_RX,
128 DMACH_UART1_TX,
129 DMACH_UART3_RX,
130 DMACH_UART3_TX,
131 DMACH_SLIMBUS1_RX,
132 DMACH_SLIMBUS1_TX,
133 DMACH_SLIMBUS3_RX,
134 DMACH_SLIMBUS3_TX,
135 DMACH_SLIMBUS5_RX,
136 DMACH_SLIMBUS5_TX,
137 };
138
139 static u8 exynos4212_pdma1_peri[] = {
140 DMACH_PCM0_RX,
141 DMACH_PCM0_TX,
142 DMACH_PCM1_RX,
143 DMACH_PCM1_TX,
144 DMACH_MIPI_HSI2,
145 DMACH_MIPI_HSI3,
146 DMACH_SPI1_RX,
147 DMACH_SPI1_TX,
148 DMACH_I2S0S_TX,
149 DMACH_I2S0_RX,
150 DMACH_I2S0_TX,
151 DMACH_I2S1_RX,
152 DMACH_I2S1_TX,
153 DMACH_UART0_RX,
154 DMACH_UART0_TX,
155 DMACH_UART1_RX,
156 DMACH_UART1_TX,
157 DMACH_UART3_RX,
158 DMACH_UART3_TX,
159 DMACH_SLIMBUS1_RX,
160 DMACH_SLIMBUS1_TX,
161 DMACH_SLIMBUS3_RX,
162 DMACH_SLIMBUS3_TX,
163 DMACH_SLIMBUS5_RX,
164 DMACH_SLIMBUS5_TX,
165 DMACH_SLIMBUS0AUX_RX,
166 DMACH_SLIMBUS0AUX_TX,
167 DMACH_SPDIF,
168 DMACH_MIPI_HSI6,
169 DMACH_MIPI_HSI7,
170 };
171
172 static struct dma_pl330_platdata exynos4_pdma1_pdata;
173
174 static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
175 EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
176
177 static u8 mdma_peri[] = {
178 DMACH_MTOM_0,
179 DMACH_MTOM_1,
180 DMACH_MTOM_2,
181 DMACH_MTOM_3,
182 DMACH_MTOM_4,
183 DMACH_MTOM_5,
184 DMACH_MTOM_6,
185 DMACH_MTOM_7,
186 };
187
188 static struct dma_pl330_platdata exynos4_mdma1_pdata = {
189 .nr_valid_peri = ARRAY_SIZE(mdma_peri),
190 .peri_id = mdma_peri,
191 };
192
193 static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
194 EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
195
exynos4_dma_init(void)196 static int __init exynos4_dma_init(void)
197 {
198 if (of_have_populated_dt())
199 return 0;
200
201 if (soc_is_exynos4210()) {
202 exynos4_pdma0_pdata.nr_valid_peri =
203 ARRAY_SIZE(exynos4210_pdma0_peri);
204 exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
205 exynos4_pdma1_pdata.nr_valid_peri =
206 ARRAY_SIZE(exynos4210_pdma1_peri);
207 exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
208 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
209 exynos4_pdma0_pdata.nr_valid_peri =
210 ARRAY_SIZE(exynos4212_pdma0_peri);
211 exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
212 exynos4_pdma1_pdata.nr_valid_peri =
213 ARRAY_SIZE(exynos4212_pdma1_peri);
214 exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
215 }
216
217 dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
218 dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
219 amba_device_register(&exynos4_pdma0_device, &iomem_resource);
220
221 dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
222 dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
223 amba_device_register(&exynos4_pdma1_device, &iomem_resource);
224
225 dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
226 amba_device_register(&exynos4_mdma1_device, &iomem_resource);
227
228 return 0;
229 }
230 arch_initcall(exynos4_dma_init);
231