1 /* linux/arch/arm/mach-exynos4/pm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4210 - Power Management support
7 *
8 * Based on arch/arm/mach-s3c2410/pm.c
9 * Copyright (c) 2006 Simtec Electronics
10 * Ben Dooks <ben@simtec.co.uk>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/init.h>
18 #include <linux/suspend.h>
19 #include <linux/syscore_ops.h>
20 #include <linux/io.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23
24 #include <asm/cacheflush.h>
25 #include <asm/hardware/cache-l2x0.h>
26 #include <asm/smp_scu.h>
27
28 #include <plat/cpu.h>
29 #include <plat/pm.h>
30 #include <plat/pll.h>
31 #include <plat/regs-srom.h>
32
33 #include <mach/regs-irq.h>
34 #include <mach/regs-gpio.h>
35 #include <mach/regs-clock.h>
36 #include <mach/regs-pmu.h>
37 #include <mach/pm-core.h>
38 #include <mach/pmu.h>
39
40 static struct sleep_save exynos4_set_clksrc[] = {
41 { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
42 { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
43 { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
44 { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
45 { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
46 { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
47 { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
48 { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
49 { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
50 };
51
52 static struct sleep_save exynos4210_set_clksrc[] = {
53 { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
54 };
55
56 static struct sleep_save exynos4_epll_save[] = {
57 SAVE_ITEM(EXYNOS4_EPLL_CON0),
58 SAVE_ITEM(EXYNOS4_EPLL_CON1),
59 };
60
61 static struct sleep_save exynos4_vpll_save[] = {
62 SAVE_ITEM(EXYNOS4_VPLL_CON0),
63 SAVE_ITEM(EXYNOS4_VPLL_CON1),
64 };
65
66 static struct sleep_save exynos4_core_save[] = {
67 /* GIC side */
68 SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
69 SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
70 SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
71 SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
72 SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
73 SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
74 SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
75 SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
76 SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
77 SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
78 SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
79 SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
80 SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
81 SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
82 SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
83 SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
84 SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
85 SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
86 SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
87 SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
88 SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
89 SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
90 SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
91 SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
92 SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
93 SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
94 SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
95 SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
96 SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
97 SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
98 SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
99 SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
100 SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
101 SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
102 SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
103 SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
104 SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
105 SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
106
107 SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
108 SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
109 SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
110 SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
111 SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
112 SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
113 SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
114 SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
115 SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
116 SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
117 SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
118 SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
119 SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
120 SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
121 SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
122 SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
123 SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
124 SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
125 SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
126 SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
127 SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
128 SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
129 SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
130 SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
131
132 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
133 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
134 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
135 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
136 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
137 SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
138
139 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
140 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
141 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
142 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
143 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
144 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
145 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
146 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
147 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
148 SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
149
150 /* SROM side */
151 SAVE_ITEM(S5P_SROM_BW),
152 SAVE_ITEM(S5P_SROM_BC0),
153 SAVE_ITEM(S5P_SROM_BC1),
154 SAVE_ITEM(S5P_SROM_BC2),
155 SAVE_ITEM(S5P_SROM_BC3),
156 };
157
158
159 /* For Cortex-A9 Diagnostic and Power control register */
160 static unsigned int save_arm_register[2];
161
exynos4_cpu_suspend(unsigned long arg)162 static int exynos4_cpu_suspend(unsigned long arg)
163 {
164 outer_flush_all();
165
166 /* issue the standby signal into the pm unit. */
167 cpu_do_idle();
168
169 /* we should never get past here */
170 panic("sleep resumed to originator?");
171 }
172
exynos4_pm_prepare(void)173 static void exynos4_pm_prepare(void)
174 {
175 u32 tmp;
176
177 s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
178 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
179 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
180
181 tmp = __raw_readl(S5P_INFORM1);
182
183 /* Set value of power down register for sleep mode */
184
185 exynos4_sys_powerdown_conf(SYS_SLEEP);
186 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
187
188 /* ensure at least INFORM0 has the resume address */
189
190 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
191
192 /* Before enter central sequence mode, clock src register have to set */
193
194 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
195
196 if (soc_is_exynos4210())
197 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
198
199 }
200
exynos4_pm_add(struct device * dev,struct subsys_interface * sif)201 static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif)
202 {
203 pm_cpu_prep = exynos4_pm_prepare;
204 pm_cpu_sleep = exynos4_cpu_suspend;
205
206 return 0;
207 }
208
209 static unsigned long pll_base_rate;
210
exynos4_restore_pll(void)211 static void exynos4_restore_pll(void)
212 {
213 unsigned long pll_con, locktime, lockcnt;
214 unsigned long pll_in_rate;
215 unsigned int p_div, epll_wait = 0, vpll_wait = 0;
216
217 if (pll_base_rate == 0)
218 return;
219
220 pll_in_rate = pll_base_rate;
221
222 /* EPLL */
223 pll_con = exynos4_epll_save[0].val;
224
225 if (pll_con & (1 << 31)) {
226 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
227 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
228
229 pll_in_rate /= 1000000;
230
231 locktime = (3000 / pll_in_rate) * p_div;
232 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
233
234 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
235
236 s3c_pm_do_restore_core(exynos4_epll_save,
237 ARRAY_SIZE(exynos4_epll_save));
238 epll_wait = 1;
239 }
240
241 pll_in_rate = pll_base_rate;
242
243 /* VPLL */
244 pll_con = exynos4_vpll_save[0].val;
245
246 if (pll_con & (1 << 31)) {
247 pll_in_rate /= 1000000;
248 /* 750us */
249 locktime = 750;
250 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
251
252 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
253
254 s3c_pm_do_restore_core(exynos4_vpll_save,
255 ARRAY_SIZE(exynos4_vpll_save));
256 vpll_wait = 1;
257 }
258
259 /* Wait PLL locking */
260
261 do {
262 if (epll_wait) {
263 pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
264 if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
265 epll_wait = 0;
266 }
267
268 if (vpll_wait) {
269 pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
270 if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
271 vpll_wait = 0;
272 }
273 } while (epll_wait || vpll_wait);
274 }
275
276 static struct subsys_interface exynos4_pm_interface = {
277 .name = "exynos4_pm",
278 .subsys = &exynos4_subsys,
279 .add_dev = exynos4_pm_add,
280 };
281
exynos4_pm_drvinit(void)282 static __init int exynos4_pm_drvinit(void)
283 {
284 struct clk *pll_base;
285 unsigned int tmp;
286
287 s3c_pm_init();
288
289 /* All wakeup disable */
290
291 tmp = __raw_readl(S5P_WAKEUP_MASK);
292 tmp |= ((0xFF << 8) | (0x1F << 1));
293 __raw_writel(tmp, S5P_WAKEUP_MASK);
294
295 pll_base = clk_get(NULL, "xtal");
296
297 if (!IS_ERR(pll_base)) {
298 pll_base_rate = clk_get_rate(pll_base);
299 clk_put(pll_base);
300 }
301
302 return subsys_interface_register(&exynos4_pm_interface);
303 }
304 arch_initcall(exynos4_pm_drvinit);
305
exynos4_pm_suspend(void)306 static int exynos4_pm_suspend(void)
307 {
308 unsigned long tmp;
309
310 /* Setting Central Sequence Register for power down mode */
311
312 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
313 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
314 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
315
316 if (soc_is_exynos4212()) {
317 tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
318 tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
319 S5P_USE_STANDBYWFE_ISP_ARM);
320 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
321 }
322
323 /* Save Power control register */
324 asm ("mrc p15, 0, %0, c15, c0, 0"
325 : "=r" (tmp) : : "cc");
326 save_arm_register[0] = tmp;
327
328 /* Save Diagnostic register */
329 asm ("mrc p15, 0, %0, c15, c0, 1"
330 : "=r" (tmp) : : "cc");
331 save_arm_register[1] = tmp;
332
333 return 0;
334 }
335
exynos4_pm_resume(void)336 static void exynos4_pm_resume(void)
337 {
338 unsigned long tmp;
339
340 /*
341 * If PMU failed while entering sleep mode, WFI will be
342 * ignored by PMU and then exiting cpu_do_idle().
343 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
344 * in this situation.
345 */
346 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
347 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
348 tmp |= S5P_CENTRAL_LOWPWR_CFG;
349 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
350 /* No need to perform below restore code */
351 goto early_wakeup;
352 }
353 /* Restore Power control register */
354 tmp = save_arm_register[0];
355 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
356 : : "r" (tmp)
357 : "cc");
358
359 /* Restore Diagnostic register */
360 tmp = save_arm_register[1];
361 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
362 : : "r" (tmp)
363 : "cc");
364
365 /* For release retention */
366
367 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
368 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
369 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
370 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
371 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
372 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
373 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
374
375 s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
376
377 exynos4_restore_pll();
378
379 #ifdef CONFIG_SMP
380 scu_enable(S5P_VA_SCU);
381 #endif
382
383 early_wakeup:
384 return;
385 }
386
387 static struct syscore_ops exynos4_pm_syscore_ops = {
388 .suspend = exynos4_pm_suspend,
389 .resume = exynos4_pm_resume,
390 };
391
exynos4_pm_syscore_init(void)392 static __init int exynos4_pm_syscore_init(void)
393 {
394 register_syscore_ops(&exynos4_pm_syscore_ops);
395 return 0;
396 }
397 arch_initcall(exynos4_pm_syscore_init);
398