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1 /*
2  * arch/arm/mach-ixp2000/ixdp2800.c
3  *
4  * IXDP2800 platform support
5  *
6  * Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
7  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8  *
9  * Copyright (C) 2002 Intel Corp.
10  * Copyright (C) 2003-2004 MontaVista Software, Inc.
11  *
12  *  This program is free software; you can redistribute  it and/or modify it
13  *  under  the terms of  the GNU General  Public License as published by the
14  *  Free Software Foundation;  either version 2 of the  License, or (at your
15  *  option) any later version.
16  */
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/mm.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/device.h>
23 #include <linux/bitops.h>
24 #include <linux/pci.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/io.h>
28 
29 #include <asm/irq.h>
30 #include <asm/pgtable.h>
31 #include <asm/page.h>
32 #include <mach/hardware.h>
33 #include <asm/mach-types.h>
34 
35 #include <asm/mach/pci.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach/time.h>
39 #include <asm/mach/flash.h>
40 #include <asm/mach/arch.h>
41 
42 /*************************************************************************
43  * IXDP2800 timer tick
44  *************************************************************************/
45 
ixdp2800_timer_init(void)46 static void __init ixdp2800_timer_init(void)
47 {
48 	ixp2000_init_time(50000000);
49 }
50 
51 static struct sys_timer ixdp2800_timer = {
52 	.init		= ixdp2800_timer_init,
53 	.offset		= ixp2000_gettimeoffset,
54 };
55 
56 /*************************************************************************
57  * IXDP2800 PCI
58  *************************************************************************/
ixdp2800_slave_disable_pci_master(void)59 static void __init ixdp2800_slave_disable_pci_master(void)
60 {
61 	*IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
62 }
63 
ixdp2800_master_wait_for_slave(void)64 static void __init ixdp2800_master_wait_for_slave(void)
65 {
66 	volatile u32 *addr;
67 
68 	printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure "
69 			 "its BAR sizes\n");
70 
71 	addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
72 					PCI_BASE_ADDRESS_1);
73 	do {
74 		*addr = 0xffffffff;
75 		cpu_relax();
76 	} while (*addr != 0xfe000008);
77 
78 	addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
79 					PCI_BASE_ADDRESS_2);
80 	do {
81 		*addr = 0xffffffff;
82 		cpu_relax();
83 	} while (*addr != 0xc0000008);
84 
85 	/*
86 	 * Configure the slave's SDRAM BAR by hand.
87 	 */
88 	*addr = 0x40000008;
89 }
90 
ixdp2800_slave_wait_for_master_enable(void)91 static void __init ixdp2800_slave_wait_for_master_enable(void)
92 {
93 	printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n");
94 
95 	while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0)
96 		cpu_relax();
97 }
98 
ixdp2800_pci_preinit(void)99 void __init ixdp2800_pci_preinit(void)
100 {
101 	printk("ixdp2x00_pci_preinit called\n");
102 
103 	*IXP2000_PCI_ADDR_EXT = 0x0001e000;
104 
105 	if (!ixdp2x00_master_npu())
106 		ixdp2800_slave_disable_pci_master();
107 
108 	*IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
109 	*IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
110 
111 	ixp2000_pci_preinit();
112 
113 	if (ixdp2x00_master_npu()) {
114 		/*
115 		 * Wait until the slave set its SRAM/SDRAM BAR sizes
116 		 * correctly before we proceed to scan and enumerate
117 		 * the bus.
118 		 */
119 		ixdp2800_master_wait_for_slave();
120 
121 		/*
122 		 * We configure the SDRAM BARs by hand because they
123 		 * are 1G and fall outside of the regular allocated
124 		 * PCI address space.
125 		 */
126 		*IXP2000_PCI_SDRAM_BAR = 0x00000008;
127 	} else {
128 		/*
129 		 * Wait for the master to complete scanning the bus
130 		 * and assigning resources before we proceed to scan
131 		 * the bus ourselves.  Set pci=firmware to honor the
132 		 * master's resource assignment.
133 		 */
134 		ixdp2800_slave_wait_for_master_enable();
135 		pcibios_setup("firmware");
136 	}
137 }
138 
139 /*
140  * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside
141  * of the regular PCI window, because there's only 512M of outbound PCI
142  * memory window on each IXP, while we need 1G for each of the BARs.
143  */
ixp2800_pci_fixup(struct pci_dev * dev)144 static void __devinit ixp2800_pci_fixup(struct pci_dev *dev)
145 {
146 	if (machine_is_ixdp2800()) {
147 		dev->resource[2].start = 0;
148 		dev->resource[2].end   = 0;
149 		dev->resource[2].flags = 0;
150 	}
151 }
152 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup);
153 
ixdp2800_pci_setup(int nr,struct pci_sys_data * sys)154 static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
155 {
156 	sys->mem_offset = 0x00000000;
157 
158 	ixp2000_pci_setup(nr, sys);
159 
160 	return 1;
161 }
162 
ixdp2800_pci_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)163 static int __init ixdp2800_pci_map_irq(const struct pci_dev *dev, u8 slot,
164 	u8 pin)
165 {
166 	if (ixdp2x00_master_npu()) {
167 
168 		/*
169 		 * Root bus devices.  Slave NPU is only one with interrupt.
170 		 * Everything else, we just return -1 which is invalid.
171 		 */
172 		if(!dev->bus->self) {
173 			if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
174 				return IRQ_IXDP2800_INGRESS_NPU;
175 
176 			return -1;
177 		}
178 
179 		/*
180 		 * Bridge behind the PMC slot.
181 		 */
182 		if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
183 			dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
184 			!dev->bus->parent->self->bus->parent)
185 				  return IRQ_IXDP2800_PMC;
186 
187 		/*
188 		 * Device behind the first bridge
189 		 */
190 		if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
191 			switch(dev->devfn) {
192 				case IXDP2X00_PMC_DEVFN:
193 					return IRQ_IXDP2800_PMC;
194 
195 				case IXDP2800_MASTER_ENET_DEVFN:
196 					return IRQ_IXDP2800_EGRESS_ENET;
197 
198 				case IXDP2800_SWITCH_FABRIC_DEVFN:
199 					return IRQ_IXDP2800_FABRIC;
200 			}
201 		}
202 
203 		return -1;
204 	} else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
205 }
206 
ixdp2800_master_enable_slave(void)207 static void __init ixdp2800_master_enable_slave(void)
208 {
209 	volatile u32 *addr;
210 
211 	printk(KERN_INFO "IXDP2800: enabling slave NPU\n");
212 
213 	addr = (volatile u32 *)ixp2000_pci_config_addr(0,
214 					IXDP2X00_SLAVE_NPU_DEVFN,
215 					PCI_COMMAND);
216 
217 	*addr |= PCI_COMMAND_MASTER;
218 }
219 
ixdp2800_master_wait_for_slave_bus_scan(void)220 static void __init ixdp2800_master_wait_for_slave_bus_scan(void)
221 {
222 	volatile u32 *addr;
223 
224 	printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n");
225 
226 	addr = (volatile u32 *)ixp2000_pci_config_addr(0,
227 					IXDP2X00_SLAVE_NPU_DEVFN,
228 					PCI_COMMAND);
229 	while ((*addr & PCI_COMMAND_MEMORY) == 0)
230 		cpu_relax();
231 }
232 
ixdp2800_slave_signal_bus_scan_completion(void)233 static void __init ixdp2800_slave_signal_bus_scan_completion(void)
234 {
235 	printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n");
236 	*IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY;
237 }
238 
ixdp2800_pci_postinit(void)239 static void __init ixdp2800_pci_postinit(void)
240 {
241 	if (!ixdp2x00_master_npu()) {
242 		ixdp2x00_slave_pci_postinit();
243 		ixdp2800_slave_signal_bus_scan_completion();
244 	}
245 }
246 
247 struct __initdata hw_pci ixdp2800_pci __initdata = {
248 	.nr_controllers	= 1,
249 	.setup		= ixdp2800_pci_setup,
250 	.preinit	= ixdp2800_pci_preinit,
251 	.postinit	= ixdp2800_pci_postinit,
252 	.scan		= ixp2000_pci_scan_bus,
253 	.map_irq	= ixdp2800_pci_map_irq,
254 };
255 
ixdp2800_pci_init(void)256 int __init ixdp2800_pci_init(void)
257 {
258 	if (machine_is_ixdp2800()) {
259 		struct pci_dev *dev;
260 
261 		pci_common_init(&ixdp2800_pci);
262 		if (ixdp2x00_master_npu()) {
263 			dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
264 			pci_stop_and_remove_bus_device(dev);
265 			pci_dev_put(dev);
266 
267 			ixdp2800_master_enable_slave();
268 			ixdp2800_master_wait_for_slave_bus_scan();
269 		} else {
270 			dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN);
271 			pci_stop_and_remove_bus_device(dev);
272 			pci_dev_put(dev);
273 		}
274 	}
275 
276 	return 0;
277 }
278 
279 subsys_initcall(ixdp2800_pci_init);
280 
ixdp2800_init_irq(void)281 void __init ixdp2800_init_irq(void)
282 {
283 	ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
284 }
285 
286 MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
287 	/* Maintainer: MontaVista Software, Inc. */
288 	.atag_offset	= 0x100,
289 	.map_io		= ixdp2x00_map_io,
290 	.init_irq	= ixdp2800_init_irq,
291 	.timer		= &ixdp2800_timer,
292 	.init_machine	= ixdp2x00_init_machine,
293 	.restart	= ixp2000_restart,
294 MACHINE_END
295 
296