1 /*
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23
24 #include <asm/mach/time.h>
25 #include <asm/hardware/gic.h>
26 #include <asm/localtimer.h>
27 #include <asm/sched_clock.h>
28
29 #include <mach/msm_iomap.h>
30 #include <mach/cpu.h>
31 #include <mach/board.h>
32
33 #define TIMER_MATCH_VAL 0x0000
34 #define TIMER_COUNT_VAL 0x0004
35 #define TIMER_ENABLE 0x0008
36 #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
37 #define TIMER_ENABLE_EN BIT(0)
38 #define TIMER_CLEAR 0x000C
39 #define DGT_CLK_CTL 0x0034
40 #define DGT_CLK_CTL_DIV_4 0x3
41
42 #define GPT_HZ 32768
43
44 #define MSM_DGT_SHIFT 5
45
46 static void __iomem *event_base;
47
msm_timer_interrupt(int irq,void * dev_id)48 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
49 {
50 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
51 /* Stop the timer tick */
52 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
54 ctrl &= ~TIMER_ENABLE_EN;
55 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
56 }
57 evt->event_handler(evt);
58 return IRQ_HANDLED;
59 }
60
msm_timer_set_next_event(unsigned long cycles,struct clock_event_device * evt)61 static int msm_timer_set_next_event(unsigned long cycles,
62 struct clock_event_device *evt)
63 {
64 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
65
66 writel_relaxed(0, event_base + TIMER_CLEAR);
67 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
68 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
69 return 0;
70 }
71
msm_timer_set_mode(enum clock_event_mode mode,struct clock_event_device * evt)72 static void msm_timer_set_mode(enum clock_event_mode mode,
73 struct clock_event_device *evt)
74 {
75 u32 ctrl;
76
77 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
78 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
79
80 switch (mode) {
81 case CLOCK_EVT_MODE_RESUME:
82 case CLOCK_EVT_MODE_PERIODIC:
83 break;
84 case CLOCK_EVT_MODE_ONESHOT:
85 /* Timer is enabled in set_next_event */
86 break;
87 case CLOCK_EVT_MODE_UNUSED:
88 case CLOCK_EVT_MODE_SHUTDOWN:
89 break;
90 }
91 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
92 }
93
94 static struct clock_event_device msm_clockevent = {
95 .name = "gp_timer",
96 .features = CLOCK_EVT_FEAT_ONESHOT,
97 .rating = 200,
98 .set_next_event = msm_timer_set_next_event,
99 .set_mode = msm_timer_set_mode,
100 };
101
102 static union {
103 struct clock_event_device *evt;
104 struct clock_event_device __percpu **percpu_evt;
105 } msm_evt;
106
107 static void __iomem *source_base;
108
msm_read_timer_count(struct clocksource * cs)109 static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
110 {
111 return readl_relaxed(source_base + TIMER_COUNT_VAL);
112 }
113
msm_read_timer_count_shift(struct clocksource * cs)114 static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
115 {
116 /*
117 * Shift timer count down by a constant due to unreliable lower bits
118 * on some targets.
119 */
120 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
121 }
122
123 static struct clocksource msm_clocksource = {
124 .name = "dg_timer",
125 .rating = 300,
126 .read = msm_read_timer_count,
127 .mask = CLOCKSOURCE_MASK(32),
128 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
129 };
130
131 #ifdef CONFIG_LOCAL_TIMERS
msm_local_timer_setup(struct clock_event_device * evt)132 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
133 {
134 /* Use existing clock_event for cpu 0 */
135 if (!smp_processor_id())
136 return 0;
137
138 writel_relaxed(0, event_base + TIMER_ENABLE);
139 writel_relaxed(0, event_base + TIMER_CLEAR);
140 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
141 evt->irq = msm_clockevent.irq;
142 evt->name = "local_timer";
143 evt->features = msm_clockevent.features;
144 evt->rating = msm_clockevent.rating;
145 evt->set_mode = msm_timer_set_mode;
146 evt->set_next_event = msm_timer_set_next_event;
147 evt->shift = msm_clockevent.shift;
148 evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
149 evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
150 evt->min_delta_ns = clockevent_delta2ns(4, evt);
151
152 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
153 clockevents_register_device(evt);
154 enable_percpu_irq(evt->irq, 0);
155 return 0;
156 }
157
msm_local_timer_stop(struct clock_event_device * evt)158 static void msm_local_timer_stop(struct clock_event_device *evt)
159 {
160 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
161 disable_percpu_irq(evt->irq);
162 }
163
164 static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
165 .setup = msm_local_timer_setup,
166 .stop = msm_local_timer_stop,
167 };
168 #endif /* CONFIG_LOCAL_TIMERS */
169
msm_sched_clock_read(void)170 static notrace u32 msm_sched_clock_read(void)
171 {
172 return msm_clocksource.read(&msm_clocksource);
173 }
174
msm_timer_init(void)175 static void __init msm_timer_init(void)
176 {
177 struct clock_event_device *ce = &msm_clockevent;
178 struct clocksource *cs = &msm_clocksource;
179 int res;
180 u32 dgt_hz;
181
182 if (cpu_is_msm7x01()) {
183 event_base = MSM_CSR_BASE;
184 source_base = MSM_CSR_BASE + 0x10;
185 dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
186 cs->read = msm_read_timer_count_shift;
187 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
188 } else if (cpu_is_msm7x30()) {
189 event_base = MSM_CSR_BASE + 0x04;
190 source_base = MSM_CSR_BASE + 0x24;
191 dgt_hz = 24576000 / 4;
192 } else if (cpu_is_qsd8x50()) {
193 event_base = MSM_CSR_BASE;
194 source_base = MSM_CSR_BASE + 0x10;
195 dgt_hz = 19200000 / 4;
196 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
197 event_base = MSM_TMR_BASE + 0x04;
198 /* Use CPU0's timer as the global clock source. */
199 source_base = MSM_TMR0_BASE + 0x24;
200 dgt_hz = 27000000 / 4;
201 writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
202 } else
203 BUG();
204
205 writel_relaxed(0, event_base + TIMER_ENABLE);
206 writel_relaxed(0, event_base + TIMER_CLEAR);
207 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
208 ce->cpumask = cpumask_of(0);
209
210 ce->irq = INT_GP_TIMER_EXP;
211 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
212 if (cpu_is_msm8x60() || cpu_is_msm8960()) {
213 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
214 if (!msm_evt.percpu_evt) {
215 pr_err("memory allocation failed for %s\n", ce->name);
216 goto err;
217 }
218 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
219 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
220 ce->name, msm_evt.percpu_evt);
221 if (!res) {
222 enable_percpu_irq(ce->irq, 0);
223 #ifdef CONFIG_LOCAL_TIMERS
224 local_timer_register(&msm_local_timer_ops);
225 #endif
226 }
227 } else {
228 msm_evt.evt = ce;
229 res = request_irq(ce->irq, msm_timer_interrupt,
230 IRQF_TIMER | IRQF_NOBALANCING |
231 IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
232 }
233
234 if (res)
235 pr_err("request_irq failed for %s\n", ce->name);
236 err:
237 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
238 res = clocksource_register_hz(cs, dgt_hz);
239 if (res)
240 pr_err("clocksource_register failed\n");
241 setup_sched_clock(msm_sched_clock_read,
242 cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
243 }
244
245 struct sys_timer msm_timer = {
246 .init = msm_timer_init
247 };
248