1 /*
2 * arch/arm/mach-pnx4008/irq.c
3 *
4 * PNX4008 IRQ controller driver
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code received from Philips:
9 * Copyright (C) 2003 Philips Semiconductors
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/list.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/device.h>
25 #include <linux/irq.h>
26 #include <linux/io.h>
27 #include <mach/hardware.h>
28 #include <asm/setup.h>
29 #include <asm/pgtable.h>
30 #include <asm/page.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/irq.h>
33 #include <asm/mach/map.h>
34 #include <mach/irq.h>
35
36 static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
37
pnx4008_mask_irq(struct irq_data * d)38 static void pnx4008_mask_irq(struct irq_data *d)
39 {
40 __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */
41 }
42
pnx4008_unmask_irq(struct irq_data * d)43 static void pnx4008_unmask_irq(struct irq_data *d)
44 {
45 __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */
46 }
47
pnx4008_mask_ack_irq(struct irq_data * d)48 static void pnx4008_mask_ack_irq(struct irq_data *d)
49 {
50 __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */
51 __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */
52 }
53
pnx4008_set_irq_type(struct irq_data * d,unsigned int type)54 static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
55 {
56 switch (type) {
57 case IRQ_TYPE_EDGE_RISING:
58 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
59 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
60 irq_set_handler(d->irq, handle_edge_irq);
61 break;
62 case IRQ_TYPE_EDGE_FALLING:
63 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
64 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
65 irq_set_handler(d->irq, handle_edge_irq);
66 break;
67 case IRQ_TYPE_LEVEL_LOW:
68 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
69 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
70 irq_set_handler(d->irq, handle_level_irq);
71 break;
72 case IRQ_TYPE_LEVEL_HIGH:
73 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
74 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
75 irq_set_handler(d->irq, handle_level_irq);
76 break;
77
78 /* IRQ_TYPE_EDGE_BOTH is not supported */
79 default:
80 printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
81 return -1;
82 }
83 return 0;
84 }
85
86 static struct irq_chip pnx4008_irq_chip = {
87 .irq_ack = pnx4008_mask_ack_irq,
88 .irq_mask = pnx4008_mask_irq,
89 .irq_unmask = pnx4008_unmask_irq,
90 .irq_set_type = pnx4008_set_irq_type,
91 };
92
pnx4008_init_irq(void)93 void __init pnx4008_init_irq(void)
94 {
95 unsigned int i;
96
97 /* configure IRQ's */
98 for (i = 0; i < NR_IRQS; i++) {
99 set_irq_flags(i, IRQF_VALID);
100 irq_set_chip(i, &pnx4008_irq_chip);
101 pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
102 }
103
104 /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
105 pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
106 pnx4008_irq_type[SUB1_IRQ_N]);
107 pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
108 pnx4008_irq_type[SUB2_IRQ_N]);
109 pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
110 pnx4008_irq_type[SUB1_FIQ_N]);
111 pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
112 pnx4008_irq_type[SUB2_FIQ_N]);
113
114 /* mask all others */
115 __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
116 (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
117 INTC_ER(MAIN_BASE_INT));
118 __raw_writel(0, INTC_ER(SIC1_BASE_INT));
119 __raw_writel(0, INTC_ER(SIC2_BASE_INT));
120 }
121
122