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1 /* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
2  *
3  * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
4  * Copyright 2008 Openmoko, Inc.
5  * Copyright 2008 Simtec Electronics
6  *	Ben Dooks <ben@simtec.co.uk>
7  *	http://armlinux.simtec.co.uk/
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13 */
14 
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/fb.h>
18 #include <linux/gpio.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/dm9000.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/serial_core.h>
25 #include <linux/types.h>
26 
27 #include <asm/hardware/vic.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
31 
32 #include <mach/map.h>
33 #include <mach/regs-gpio.h>
34 #include <mach/regs-modem.h>
35 #include <mach/regs-srom.h>
36 
37 #include <plat/adc.h>
38 #include <plat/cpu.h>
39 #include <plat/devs.h>
40 #include <plat/fb.h>
41 #include <plat/nand.h>
42 #include <plat/regs-serial.h>
43 #include <plat/ts.h>
44 #include <plat/regs-fb-v4.h>
45 
46 #include <video/platform_lcd.h>
47 
48 #include "common.h"
49 
50 #define UCON S3C2410_UCON_DEFAULT
51 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
52 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
53 
54 static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
55 	[0] = {
56 		.hwport	= 0,
57 		.flags	= 0,
58 		.ucon	= UCON,
59 		.ulcon	= ULCON,
60 		.ufcon	= UFCON,
61 	},
62 	[1] = {
63 		.hwport	= 1,
64 		.flags	= 0,
65 		.ucon	= UCON,
66 		.ulcon	= ULCON,
67 		.ufcon	= UFCON,
68 	},
69 	[2] = {
70 		.hwport	= 2,
71 		.flags	= 0,
72 		.ucon	= UCON,
73 		.ulcon	= ULCON,
74 		.ufcon	= UFCON,
75 	},
76 	[3] = {
77 		.hwport	= 3,
78 		.flags	= 0,
79 		.ucon	= UCON,
80 		.ulcon	= ULCON,
81 		.ufcon	= UFCON,
82 	},
83 };
84 
85 /* DM9000AEP 10/100 ethernet controller */
86 
87 static struct resource mini6410_dm9k_resource[] = {
88 	[0] = {
89 		.start	= S3C64XX_PA_XM0CSN1,
90 		.end	= S3C64XX_PA_XM0CSN1 + 1,
91 		.flags	= IORESOURCE_MEM
92 	},
93 	[1] = {
94 		.start	= S3C64XX_PA_XM0CSN1 + 4,
95 		.end	= S3C64XX_PA_XM0CSN1 + 5,
96 		.flags	= IORESOURCE_MEM
97 	},
98 	[2] = {
99 		.start	= S3C_EINT(7),
100 		.end	= S3C_EINT(7),
101 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
102 	}
103 };
104 
105 static struct dm9000_plat_data mini6410_dm9k_pdata = {
106 	.flags		= (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
107 };
108 
109 static struct platform_device mini6410_device_eth = {
110 	.name		= "dm9000",
111 	.id		= -1,
112 	.num_resources	= ARRAY_SIZE(mini6410_dm9k_resource),
113 	.resource	= mini6410_dm9k_resource,
114 	.dev		= {
115 		.platform_data	= &mini6410_dm9k_pdata,
116 	},
117 };
118 
119 static struct mtd_partition mini6410_nand_part[] = {
120 	[0] = {
121 		.name	= "uboot",
122 		.size	= SZ_1M,
123 		.offset	= 0,
124 	},
125 	[1] = {
126 		.name	= "kernel",
127 		.size	= SZ_2M,
128 		.offset	= SZ_1M,
129 	},
130 	[2] = {
131 		.name	= "rootfs",
132 		.size	= MTDPART_SIZ_FULL,
133 		.offset	= SZ_1M + SZ_2M,
134 	},
135 };
136 
137 static struct s3c2410_nand_set mini6410_nand_sets[] = {
138 	[0] = {
139 		.name		= "nand",
140 		.nr_chips	= 1,
141 		.nr_partitions	= ARRAY_SIZE(mini6410_nand_part),
142 		.partitions	= mini6410_nand_part,
143 	},
144 };
145 
146 static struct s3c2410_platform_nand mini6410_nand_info = {
147 	.tacls		= 25,
148 	.twrph0		= 55,
149 	.twrph1		= 40,
150 	.nr_sets	= ARRAY_SIZE(mini6410_nand_sets),
151 	.sets		= mini6410_nand_sets,
152 };
153 
154 static struct s3c_fb_pd_win mini6410_fb_win[] = {
155 	{
156 		.win_mode	= {	/* 4.3" 480x272 */
157 			.left_margin	= 3,
158 			.right_margin	= 2,
159 			.upper_margin	= 1,
160 			.lower_margin	= 1,
161 			.hsync_len	= 40,
162 			.vsync_len	= 1,
163 			.xres		= 480,
164 			.yres		= 272,
165 		},
166 		.max_bpp	= 32,
167 		.default_bpp	= 16,
168 	}, {
169 		.win_mode	= {	/* 7.0" 800x480 */
170 			.left_margin	= 8,
171 			.right_margin	= 13,
172 			.upper_margin	= 7,
173 			.lower_margin	= 5,
174 			.hsync_len	= 3,
175 			.vsync_len	= 1,
176 			.xres		= 800,
177 			.yres		= 480,
178 		},
179 		.max_bpp	= 32,
180 		.default_bpp	= 16,
181 	},
182 };
183 
184 static struct s3c_fb_platdata mini6410_lcd_pdata __initdata = {
185 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
186 	.win[0]		= &mini6410_fb_win[0],
187 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
188 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
189 };
190 
mini6410_lcd_power_set(struct plat_lcd_data * pd,unsigned int power)191 static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
192 				   unsigned int power)
193 {
194 	if (power)
195 		gpio_direction_output(S3C64XX_GPE(0), 1);
196 	else
197 		gpio_direction_output(S3C64XX_GPE(0), 0);
198 }
199 
200 static struct plat_lcd_data mini6410_lcd_power_data = {
201 	.set_power	= mini6410_lcd_power_set,
202 };
203 
204 static struct platform_device mini6410_lcd_powerdev = {
205 	.name			= "platform-lcd",
206 	.dev.parent		= &s3c_device_fb.dev,
207 	.dev.platform_data	= &mini6410_lcd_power_data,
208 };
209 
210 static struct platform_device *mini6410_devices[] __initdata = {
211 	&mini6410_device_eth,
212 	&s3c_device_hsmmc0,
213 	&s3c_device_hsmmc1,
214 	&s3c_device_ohci,
215 	&s3c_device_nand,
216 	&s3c_device_fb,
217 	&mini6410_lcd_powerdev,
218 	&s3c_device_adc,
219 	&s3c_device_ts,
220 };
221 
mini6410_map_io(void)222 static void __init mini6410_map_io(void)
223 {
224 	u32 tmp;
225 
226 	s3c64xx_init_io(NULL, 0);
227 	s3c24xx_init_clocks(12000000);
228 	s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
229 
230 	/* set the LCD type */
231 	tmp = __raw_readl(S3C64XX_SPCON);
232 	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
233 	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
234 	__raw_writel(tmp, S3C64XX_SPCON);
235 
236 	/* remove the LCD bypass */
237 	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
238 	tmp &= ~MIFPCON_LCD_BYPASS;
239 	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
240 }
241 
242 /*
243  * mini6410_features string
244  *
245  * 0-9 LCD configuration
246  *
247  */
248 static char mini6410_features_str[12] __initdata = "0";
249 
mini6410_features_setup(char * str)250 static int __init mini6410_features_setup(char *str)
251 {
252 	if (str)
253 		strlcpy(mini6410_features_str, str,
254 			sizeof(mini6410_features_str));
255 	return 1;
256 }
257 
258 __setup("mini6410=", mini6410_features_setup);
259 
260 #define FEATURE_SCREEN (1 << 0)
261 
262 struct mini6410_features_t {
263 	int done;
264 	int lcd_index;
265 };
266 
mini6410_parse_features(struct mini6410_features_t * features,const char * features_str)267 static void mini6410_parse_features(
268 		struct mini6410_features_t *features,
269 		const char *features_str)
270 {
271 	const char *fp = features_str;
272 
273 	features->done = 0;
274 	features->lcd_index = 0;
275 
276 	while (*fp) {
277 		char f = *fp++;
278 
279 		switch (f) {
280 		case '0'...'9':	/* tft screen */
281 			if (features->done & FEATURE_SCREEN) {
282 				printk(KERN_INFO "MINI6410: '%c' ignored, "
283 					"screen type already set\n", f);
284 			} else {
285 				int li = f - '0';
286 				if (li >= ARRAY_SIZE(mini6410_fb_win))
287 					printk(KERN_INFO "MINI6410: '%c' out "
288 						"of range LCD mode\n", f);
289 				else {
290 					features->lcd_index = li;
291 				}
292 			}
293 			features->done |= FEATURE_SCREEN;
294 			break;
295 		}
296 	}
297 }
298 
mini6410_machine_init(void)299 static void __init mini6410_machine_init(void)
300 {
301 	u32 cs1;
302 	struct mini6410_features_t features = { 0 };
303 
304 	printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
305 			mini6410_features_str);
306 
307 	/* Parse the feature string */
308 	mini6410_parse_features(&features, mini6410_features_str);
309 
310 	mini6410_lcd_pdata.win[0] = &mini6410_fb_win[features.lcd_index];
311 
312 	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
313 		mini6410_lcd_pdata.win[0]->win_mode.xres,
314 		mini6410_lcd_pdata.win[0]->win_mode.yres);
315 
316 	s3c_nand_set_platdata(&mini6410_nand_info);
317 	s3c_fb_set_platdata(&mini6410_lcd_pdata);
318 	s3c24xx_ts_set_platdata(NULL);
319 
320 	/* configure nCS1 width to 16 bits */
321 
322 	cs1 = __raw_readl(S3C64XX_SROM_BW) &
323 		~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
324 	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
325 		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
326 		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
327 			S3C64XX_SROM_BW__NCS1__SHIFT;
328 	__raw_writel(cs1, S3C64XX_SROM_BW);
329 
330 	/* set timing for nCS1 suitable for ethernet chip */
331 
332 	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
333 		(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
334 		(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
335 		(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
336 		(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
337 		(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
338 		(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
339 
340 	gpio_request(S3C64XX_GPF(15), "LCD power");
341 	gpio_request(S3C64XX_GPE(0), "LCD power");
342 
343 	platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
344 }
345 
346 MACHINE_START(MINI6410, "MINI6410")
347 	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
348 	.atag_offset	= 0x100,
349 	.init_irq	= s3c6410_init_irq,
350 	.handle_irq	= vic_handle_irq,
351 	.map_io		= mini6410_map_io,
352 	.init_machine	= mini6410_machine_init,
353 	.timer		= &s3c24xx_timer,
354 	.restart	= s3c64xx_restart,
355 MACHINE_END
356