1 /* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h 2 * 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * S5P64X0 - GPIO register definitions 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #ifndef __ASM_ARCH_REGS_GPIO_H 14 #define __ASM_ARCH_REGS_GPIO_H __FILE__ 15 16 #include <mach/map.h> 17 18 /* Base addresses for each of the banks */ 19 20 #define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000) 21 #define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020) 22 #define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040) 23 #define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0) 24 #define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0) 25 #define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0) 26 #define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100) 27 #define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120) 28 #define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830) 29 #define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160) 30 #define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290) 31 32 #define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060) 33 #define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140) 34 #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) 35 #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) 36 37 #define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0) 38 #define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0) 39 #define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0) 40 #define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0) 41 42 #define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0) 43 #define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4) 44 #define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0) 45 #define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4) 46 47 #define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200) 48 #define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220) 49 #define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240) 50 51 /* External interrupt control registers for group0 */ 52 53 #define EINT0CON0_OFFSET (0x900) 54 #define EINT0FLTCON0_OFFSET (0x910) 55 #define EINT0FLTCON1_OFFSET (0x914) 56 #define EINT0MASK_OFFSET (0x920) 57 #define EINT0PEND_OFFSET (0x924) 58 59 #define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET) 60 #define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET) 61 #define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET) 62 #define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET) 63 #define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET) 64 65 #define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930) 66 #define S5P64X0_SLPEN_USE_xSLP (1 << 0) 67 68 #endif /* __ASM_ARCH_REGS_GPIO_H */ 69