1 /* linux/arch/arm/mach-s5pv210/mach-torbreck.c
2 *
3 * Copyright (c) 2010 aESOP Community
4 * http://www.aesop.or.kr/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/serial_core.h>
16
17 #include <asm/hardware/vic.h>
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/setup.h>
21 #include <asm/mach-types.h>
22
23 #include <mach/map.h>
24 #include <mach/regs-clock.h>
25
26 #include <plat/regs-serial.h>
27 #include <plat/devs.h>
28 #include <plat/cpu.h>
29 #include <plat/iic.h>
30 #include <plat/s5p-time.h>
31
32 #include "common.h"
33
34 /* Following are default values for UCON, ULCON and UFCON UART registers */
35 #define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
36 S3C2410_UCON_RXILEVEL | \
37 S3C2410_UCON_TXIRQMODE | \
38 S3C2410_UCON_RXIRQMODE | \
39 S3C2410_UCON_RXFIFO_TOI | \
40 S3C2443_UCON_RXERR_IRQEN)
41
42 #define TORBRECK_ULCON_DEFAULT S3C2410_LCON_CS8
43
44 #define TORBRECK_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
45 S5PV210_UFCON_TXTRIG4 | \
46 S5PV210_UFCON_RXTRIG4)
47
48 static struct s3c2410_uartcfg torbreck_uartcfgs[] __initdata = {
49 [0] = {
50 .hwport = 0,
51 .flags = 0,
52 .ucon = TORBRECK_UCON_DEFAULT,
53 .ulcon = TORBRECK_ULCON_DEFAULT,
54 .ufcon = TORBRECK_UFCON_DEFAULT,
55 },
56 [1] = {
57 .hwport = 1,
58 .flags = 0,
59 .ucon = TORBRECK_UCON_DEFAULT,
60 .ulcon = TORBRECK_ULCON_DEFAULT,
61 .ufcon = TORBRECK_UFCON_DEFAULT,
62 },
63 [2] = {
64 .hwport = 2,
65 .flags = 0,
66 .ucon = TORBRECK_UCON_DEFAULT,
67 .ulcon = TORBRECK_ULCON_DEFAULT,
68 .ufcon = TORBRECK_UFCON_DEFAULT,
69 },
70 [3] = {
71 .hwport = 3,
72 .flags = 0,
73 .ucon = TORBRECK_UCON_DEFAULT,
74 .ulcon = TORBRECK_ULCON_DEFAULT,
75 .ufcon = TORBRECK_UFCON_DEFAULT,
76 },
77 };
78
79 static struct platform_device *torbreck_devices[] __initdata = {
80 &s5pv210_device_iis0,
81 &s3c_device_cfcon,
82 &s3c_device_hsmmc0,
83 &s3c_device_hsmmc1,
84 &s3c_device_hsmmc2,
85 &s3c_device_hsmmc3,
86 &s3c_device_i2c0,
87 &s3c_device_i2c1,
88 &s3c_device_i2c2,
89 &s3c_device_rtc,
90 &s3c_device_wdt,
91 };
92
93 static struct i2c_board_info torbreck_i2c_devs0[] __initdata = {
94 /* To Be Updated */
95 };
96
97 static struct i2c_board_info torbreck_i2c_devs1[] __initdata = {
98 /* To Be Updated */
99 };
100
101 static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
102 /* To Be Updated */
103 };
104
torbreck_map_io(void)105 static void __init torbreck_map_io(void)
106 {
107 s5pv210_init_io(NULL, 0);
108 s3c24xx_init_clocks(24000000);
109 s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
110 s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
111 }
112
torbreck_machine_init(void)113 static void __init torbreck_machine_init(void)
114 {
115 s3c_i2c0_set_platdata(NULL);
116 s3c_i2c1_set_platdata(NULL);
117 s3c_i2c2_set_platdata(NULL);
118 i2c_register_board_info(0, torbreck_i2c_devs0,
119 ARRAY_SIZE(torbreck_i2c_devs0));
120 i2c_register_board_info(1, torbreck_i2c_devs1,
121 ARRAY_SIZE(torbreck_i2c_devs1));
122 i2c_register_board_info(2, torbreck_i2c_devs2,
123 ARRAY_SIZE(torbreck_i2c_devs2));
124
125 platform_add_devices(torbreck_devices, ARRAY_SIZE(torbreck_devices));
126 }
127
128 MACHINE_START(TORBRECK, "TORBRECK")
129 /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
130 .atag_offset = 0x100,
131 .init_irq = s5pv210_init_irq,
132 .handle_irq = vic_handle_irq,
133 .map_io = torbreck_map_io,
134 .init_machine = torbreck_machine_init,
135 .timer = &s5p_timer,
136 .restart = s5pv210_restart,
137 MACHINE_END
138