1 /*
2 * linux/arch/arm/mach-sa1100/irq.c
3 *
4 * Copyright (C) 1999-2001 Nicolas Pitre
5 *
6 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/ioport.h>
17 #include <linux/syscore_ops.h>
18
19 #include <mach/hardware.h>
20 #include <mach/irqs.h>
21 #include <asm/mach/irq.h>
22
23 #include "generic.h"
24
25
26 /*
27 * SA1100 GPIO edge detection for IRQs:
28 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
29 * Use this instead of directly setting GRER/GFER.
30 */
31 static int GPIO_IRQ_rising_edge;
32 static int GPIO_IRQ_falling_edge;
33 static int GPIO_IRQ_mask = (1 << 11) - 1;
34
35 /*
36 * To get the GPIO number from an IRQ number
37 */
38 #define GPIO_11_27_IRQ(i) ((i) - 21)
39 #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
40
sa1100_gpio_type(struct irq_data * d,unsigned int type)41 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
42 {
43 unsigned int mask;
44
45 if (d->irq <= 10)
46 mask = 1 << d->irq;
47 else
48 mask = GPIO11_27_MASK(d->irq);
49
50 if (type == IRQ_TYPE_PROBE) {
51 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
52 return 0;
53 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
54 }
55
56 if (type & IRQ_TYPE_EDGE_RISING) {
57 GPIO_IRQ_rising_edge |= mask;
58 } else
59 GPIO_IRQ_rising_edge &= ~mask;
60 if (type & IRQ_TYPE_EDGE_FALLING) {
61 GPIO_IRQ_falling_edge |= mask;
62 } else
63 GPIO_IRQ_falling_edge &= ~mask;
64
65 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
66 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
67
68 return 0;
69 }
70
71 /*
72 * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
73 */
sa1100_low_gpio_ack(struct irq_data * d)74 static void sa1100_low_gpio_ack(struct irq_data *d)
75 {
76 GEDR = (1 << d->irq);
77 }
78
sa1100_low_gpio_mask(struct irq_data * d)79 static void sa1100_low_gpio_mask(struct irq_data *d)
80 {
81 ICMR &= ~(1 << d->irq);
82 }
83
sa1100_low_gpio_unmask(struct irq_data * d)84 static void sa1100_low_gpio_unmask(struct irq_data *d)
85 {
86 ICMR |= 1 << d->irq;
87 }
88
sa1100_low_gpio_wake(struct irq_data * d,unsigned int on)89 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
90 {
91 if (on)
92 PWER |= 1 << d->irq;
93 else
94 PWER &= ~(1 << d->irq);
95 return 0;
96 }
97
98 static struct irq_chip sa1100_low_gpio_chip = {
99 .name = "GPIO-l",
100 .irq_ack = sa1100_low_gpio_ack,
101 .irq_mask = sa1100_low_gpio_mask,
102 .irq_unmask = sa1100_low_gpio_unmask,
103 .irq_set_type = sa1100_gpio_type,
104 .irq_set_wake = sa1100_low_gpio_wake,
105 };
106
107 /*
108 * IRQ11 (GPIO11 through 27) handler. We enter here with the
109 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
110 * and call the handler.
111 */
112 static void
sa1100_high_gpio_handler(unsigned int irq,struct irq_desc * desc)113 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
114 {
115 unsigned int mask;
116
117 mask = GEDR & 0xfffff800;
118 do {
119 /*
120 * clear down all currently active IRQ sources.
121 * We will be processing them all.
122 */
123 GEDR = mask;
124
125 irq = IRQ_GPIO11;
126 mask >>= 11;
127 do {
128 if (mask & 1)
129 generic_handle_irq(irq);
130 mask >>= 1;
131 irq++;
132 } while (mask);
133
134 mask = GEDR & 0xfffff800;
135 } while (mask);
136 }
137
138 /*
139 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
140 * In addition, the IRQs are all collected up into one bit in the
141 * interrupt controller registers.
142 */
sa1100_high_gpio_ack(struct irq_data * d)143 static void sa1100_high_gpio_ack(struct irq_data *d)
144 {
145 unsigned int mask = GPIO11_27_MASK(d->irq);
146
147 GEDR = mask;
148 }
149
sa1100_high_gpio_mask(struct irq_data * d)150 static void sa1100_high_gpio_mask(struct irq_data *d)
151 {
152 unsigned int mask = GPIO11_27_MASK(d->irq);
153
154 GPIO_IRQ_mask &= ~mask;
155
156 GRER &= ~mask;
157 GFER &= ~mask;
158 }
159
sa1100_high_gpio_unmask(struct irq_data * d)160 static void sa1100_high_gpio_unmask(struct irq_data *d)
161 {
162 unsigned int mask = GPIO11_27_MASK(d->irq);
163
164 GPIO_IRQ_mask |= mask;
165
166 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
167 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
168 }
169
sa1100_high_gpio_wake(struct irq_data * d,unsigned int on)170 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
171 {
172 if (on)
173 PWER |= GPIO11_27_MASK(d->irq);
174 else
175 PWER &= ~GPIO11_27_MASK(d->irq);
176 return 0;
177 }
178
179 static struct irq_chip sa1100_high_gpio_chip = {
180 .name = "GPIO-h",
181 .irq_ack = sa1100_high_gpio_ack,
182 .irq_mask = sa1100_high_gpio_mask,
183 .irq_unmask = sa1100_high_gpio_unmask,
184 .irq_set_type = sa1100_gpio_type,
185 .irq_set_wake = sa1100_high_gpio_wake,
186 };
187
188 /*
189 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
190 * this is for internal IRQs i.e. from 11 to 31.
191 */
sa1100_mask_irq(struct irq_data * d)192 static void sa1100_mask_irq(struct irq_data *d)
193 {
194 ICMR &= ~(1 << d->irq);
195 }
196
sa1100_unmask_irq(struct irq_data * d)197 static void sa1100_unmask_irq(struct irq_data *d)
198 {
199 ICMR |= (1 << d->irq);
200 }
201
202 /*
203 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
204 */
sa1100_set_wake(struct irq_data * d,unsigned int on)205 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
206 {
207 if (d->irq == IRQ_RTCAlrm) {
208 if (on)
209 PWER |= PWER_RTC;
210 else
211 PWER &= ~PWER_RTC;
212 return 0;
213 }
214 return -EINVAL;
215 }
216
217 static struct irq_chip sa1100_normal_chip = {
218 .name = "SC",
219 .irq_ack = sa1100_mask_irq,
220 .irq_mask = sa1100_mask_irq,
221 .irq_unmask = sa1100_unmask_irq,
222 .irq_set_wake = sa1100_set_wake,
223 };
224
225 static struct resource irq_resource =
226 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
227
228 static struct sa1100irq_state {
229 unsigned int saved;
230 unsigned int icmr;
231 unsigned int iclr;
232 unsigned int iccr;
233 } sa1100irq_state;
234
sa1100irq_suspend(void)235 static int sa1100irq_suspend(void)
236 {
237 struct sa1100irq_state *st = &sa1100irq_state;
238
239 st->saved = 1;
240 st->icmr = ICMR;
241 st->iclr = ICLR;
242 st->iccr = ICCR;
243
244 /*
245 * Disable all GPIO-based interrupts.
246 */
247 ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
248 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
249 IC_GPIO1|IC_GPIO0);
250
251 /*
252 * Set the appropriate edges for wakeup.
253 */
254 GRER = PWER & GPIO_IRQ_rising_edge;
255 GFER = PWER & GPIO_IRQ_falling_edge;
256
257 /*
258 * Clear any pending GPIO interrupts.
259 */
260 GEDR = GEDR;
261
262 return 0;
263 }
264
sa1100irq_resume(void)265 static void sa1100irq_resume(void)
266 {
267 struct sa1100irq_state *st = &sa1100irq_state;
268
269 if (st->saved) {
270 ICCR = st->iccr;
271 ICLR = st->iclr;
272
273 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
274 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
275
276 ICMR = st->icmr;
277 }
278 }
279
280 static struct syscore_ops sa1100irq_syscore_ops = {
281 .suspend = sa1100irq_suspend,
282 .resume = sa1100irq_resume,
283 };
284
sa1100irq_init_devicefs(void)285 static int __init sa1100irq_init_devicefs(void)
286 {
287 register_syscore_ops(&sa1100irq_syscore_ops);
288 return 0;
289 }
290
291 device_initcall(sa1100irq_init_devicefs);
292
sa1100_init_irq(void)293 void __init sa1100_init_irq(void)
294 {
295 unsigned int irq;
296
297 request_resource(&iomem_resource, &irq_resource);
298
299 /* disable all IRQs */
300 ICMR = 0;
301
302 /* all IRQs are IRQ, not FIQ */
303 ICLR = 0;
304
305 /* clear all GPIO edge detects */
306 GFER = 0;
307 GRER = 0;
308 GEDR = -1;
309
310 /*
311 * Whatever the doc says, this has to be set for the wait-on-irq
312 * instruction to work... on a SA1100 rev 9 at least.
313 */
314 ICCR = 1;
315
316 for (irq = 0; irq <= 10; irq++) {
317 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
318 handle_edge_irq);
319 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
320 }
321
322 for (irq = 12; irq <= 31; irq++) {
323 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
324 handle_level_irq);
325 set_irq_flags(irq, IRQF_VALID);
326 }
327
328 for (irq = 32; irq <= 48; irq++) {
329 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
330 handle_edge_irq);
331 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
332 }
333
334 /*
335 * Install handler for GPIO 11-27 edge detect interrupts
336 */
337 irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
338 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
339
340 sa1100_init_gpio();
341 }
342