1 /*
2 * sh7367 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/sh_intc.h>
25 #include <mach/intc.h>
26 #include <mach/irqs.h>
27 #include <asm/mach-types.h>
28 #include <asm/mach/arch.h>
29
30 enum {
31 UNUSED_INTCA = 0,
32 ENABLED,
33 DISABLED,
34
35 /* interrupt sources INTCA */
36 DIRC,
37 CRYPT1_ERR, CRYPT2_STD,
38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
39 ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX,
40 ETM11_ACQCMP, ETM11_FULL,
41 MFI_MFIM, MFI_MFIS,
42 BBIF1, BBIF2,
43 USBDMAC_USHDMI,
44 USBHS_USHI0, USBHS_USHI1,
45 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
46 KEYSC_KEY,
47 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
48 MSIOF2, MSIOF1,
49 SCIFA4, SCIFA5, SCIFB,
50 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
51 SDHI0,
52 SDHI1,
53 MSU_MSU, MSU_MSU2,
54 IREM,
55 SIU,
56 SPU,
57 IRDA,
58 TPU0, TPU1, TPU2, TPU3, TPU4,
59 LCRC,
60 PINT1, PINT2,
61 TTI20,
62 MISTY,
63 DDM,
64 SDHI2,
65 RWDT0, RWDT1,
66 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
67 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
72
73 /* interrupt groups INTCA */
74 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
75 ETM11, ARM11, USBHS, FLCTL, IIC1
76 };
77
78 static struct intc_vect intca_vectors[] __initdata = {
79 INTC_VECT(DIRC, 0x0560),
80 INTC_VECT(CRYPT1_ERR, 0x05e0),
81 INTC_VECT(CRYPT2_STD, 0x0700),
82 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
83 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
84 INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840),
85 INTC_VECT(ARM11_COMMRX, 0x0860),
86 INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0),
87 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
88 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
89 INTC_VECT(USBDMAC_USHDMI, 0x0a00),
90 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
91 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
92 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
93 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
94 INTC_VECT(KEYSC_KEY, 0x0be0),
95 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
96 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
97 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
98 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
99 INTC_VECT(SCIFB, 0x0d60),
100 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
101 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
102 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
103 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
104 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
105 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
106 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
107 INTC_VECT(IREM, 0x0f60),
108 INTC_VECT(SIU, 0x0fa0),
109 INTC_VECT(SPU, 0x0fc0),
110 INTC_VECT(IRDA, 0x0480),
111 INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
112 INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
113 INTC_VECT(TPU4, 0x0520),
114 INTC_VECT(LCRC, 0x0540),
115 INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020),
116 INTC_VECT(TTI20, 0x1100),
117 INTC_VECT(MISTY, 0x1120),
118 INTC_VECT(DDM, 0x1140),
119 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
120 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
121 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
122 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
123 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
124 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
125 INTC_VECT(DMAC_2_DADERR, 0x20c0),
126 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
127 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
128 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
129 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
130 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
131 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
132 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
133 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
134 };
135
136 static struct intc_group intca_groups[] __initdata = {
137 INTC_GROUP(DMAC_1, DMAC_1_DEI0,
138 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
139 INTC_GROUP(DMAC_2, DMAC_2_DEI4,
140 DMAC_2_DEI5, DMAC_2_DADERR),
141 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
142 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
143 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
144 DMAC2_2_DEI5, DMAC2_2_DADERR),
145 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
146 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
147 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
148 DMAC3_2_DEI5, DMAC3_2_DADERR),
149 INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL),
150 INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX),
151 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
152 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
153 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
154 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
155 };
156
157 static struct intc_mask_reg intca_mask_registers[] __initdata = {
158 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
159 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
160 ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
161 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
162 { CRYPT1_ERR, CRYPT2_STD, DIRC, 0,
163 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
164 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
165 { PINT1, PINT2, 0, 0,
166 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
167 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
168 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
169 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
170 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
171 { DDM, 0, 0, 0,
172 0, 0, ETM11_FULL, ETM11_ACQCMP } },
173 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
174 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
175 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
176 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
177 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
178 0, 0, MSIOF2, 0 } },
179 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
180 { DISABLED, ENABLED, ENABLED, ENABLED,
181 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
182 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
183 { DISABLED, ENABLED, ENABLED, ENABLED,
184 TTI20, USBDMAC_USHDMI, SPU, SIU } },
185 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
186 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
187 CMT2, USBHS_USHI1, USBHS_USHI0, 0 } },
188 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
189 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
190 0, 0, 0, 0 } },
191 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
192 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
193 LCRC, MSU_MSU2, IREM, MSU_MSU } },
194 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
195 { 0, 0, TPU0, TPU1,
196 TPU2, TPU3, TPU4, 0 } },
197 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
198 { DISABLED, ENABLED, ENABLED, ENABLED,
199 MISTY, CMT3, RWDT1, RWDT0 } },
200 };
201
202 static struct intc_prio_reg intca_prio_registers[] __initdata = {
203 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
204 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
205 { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
206 CMT1_CMT11, ARM11 } },
207 { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2,
208 CMT1_CMT12, TPU4 } },
209 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
210 MFI_MFIM, USBHS } },
211 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
212 0, CMT1_CMT10 } },
213 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
214 SCIFA2, SCIFA3 } },
215 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
216 FLCTL, SDHI0 } },
217 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
218 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } },
219 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } },
220 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
221 { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
222 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } },
223 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
224 };
225
226 static struct intc_desc intca_desc __initdata = {
227 .name = "sh7367-intca",
228 .force_enable = ENABLED,
229 .force_disable = DISABLED,
230 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
231 intca_mask_registers, intca_prio_registers,
232 NULL, NULL),
233 };
234
235 INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
236 INTC_VECT, "sh7367-intca-irq-pins");
237
238 enum {
239 UNUSED_INTCS = 0,
240
241 INTCS,
242
243 /* interrupt sources INTCS */
244 VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
245 VIO3_VOU,
246 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
247 VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
248 VPU,
249 SGX530,
250 _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
251 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
252 IPMMU_IPMMUB, IPMMU_IPMMUS,
253 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
254 MSIOF,
255 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
256 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
257 CMT,
258 TSIF,
259 IPMMUI,
260 MVI3,
261 ICB,
262 PEP,
263 ASA,
264 BEM,
265 VE2HO,
266 HQE,
267 JPEG,
268 LCDC,
269
270 /* interrupt groups INTCS */
271 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
272 };
273
274 static struct intc_vect intcs_vectors[] = {
275 INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
276 INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
277 INTCS_VECT(VIO3_VOU, 0x780),
278 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
279 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
280 INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
281 INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
282 INTCS_VECT(VPU, 0x980),
283 INTCS_VECT(SGX530, 0x9e0),
284 INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
285 INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
286 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
287 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
288 INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
289 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
290 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
291 INTCS_VECT(MSIOF, 0xd20),
292 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
293 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
294 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
295 INTCS_VECT(TMU_TUNI2, 0xec0),
296 INTCS_VECT(CMT, 0xf00),
297 INTCS_VECT(TSIF, 0xf20),
298 INTCS_VECT(IPMMUI, 0xf60),
299 INTCS_VECT(MVI3, 0x420),
300 INTCS_VECT(ICB, 0x480),
301 INTCS_VECT(PEP, 0x4a0),
302 INTCS_VECT(ASA, 0x4c0),
303 INTCS_VECT(BEM, 0x4e0),
304 INTCS_VECT(VE2HO, 0x520),
305 INTCS_VECT(HQE, 0x540),
306 INTCS_VECT(JPEG, 0x560),
307 INTCS_VECT(LCDC, 0x580),
308
309 INTC_VECT(INTCS, 0xf80),
310 };
311
312 static struct intc_group intcs_groups[] __initdata = {
313 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
314 _2DDMAC_2DDM2, _2DDMAC_2DDM3),
315 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
316 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
317 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
318 INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
319 INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
320 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
321 INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
322 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
323 };
324
325 static struct intc_mask_reg intcs_mask_registers[] = {
326 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
327 { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
328 VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
329 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
330 { VIO3_VOU, 0, VE2HO, VPU,
331 0, 0, 0, 0 } },
332 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
333 { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
334 BEM, ASA, PEP, ICB } },
335 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
336 { 0, 0, MVI3, 0,
337 JPEG, HQE, 0, LCDC } },
338 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
339 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
340 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
341 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
342 { 0, 0, MSIOF, 0,
343 SGX530, 0, 0, 0 } },
344 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
345 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
346 0, 0, 0, 0 } },
347 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
348 { 0, 0, 0, CMT,
349 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
350 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
351 { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
352 0, 0, 0, 0 } },
353 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
354 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
355 0, 0, IPMMUI, TSIF } },
356 { 0xffd20104, 0, 16, /* INTAMASK */
357 { 0, 0, 0, 0, 0, 0, 0, 0,
358 0, 0, 0, 0, 0, 0, 0, INTCS } },
359 };
360
361 /* Priority is needed for INTCA to receive the INTCS interrupt */
362 static struct intc_prio_reg intcs_prio_registers[] = {
363 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
364 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
365 { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
366 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
367 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
368 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
369 TMU_TUNI2, 0 } },
370 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
371 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
372 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
373 { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
374 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
375 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
376 };
377
378 static struct resource intcs_resources[] __initdata = {
379 [0] = {
380 .start = 0xffd20000,
381 .end = 0xffd2ffff,
382 .flags = IORESOURCE_MEM,
383 }
384 };
385
386 static struct intc_desc intcs_desc __initdata = {
387 .name = "sh7367-intcs",
388 .resource = intcs_resources,
389 .num_resources = ARRAY_SIZE(intcs_resources),
390 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
391 intcs_prio_registers, NULL, NULL),
392 };
393
intcs_demux(unsigned int irq,struct irq_desc * desc)394 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
395 {
396 void __iomem *reg = (void *)irq_get_handler_data(irq);
397 unsigned int evtcodeas = ioread32(reg);
398
399 generic_handle_irq(intcs_evt2irq(evtcodeas));
400 }
401
sh7367_init_irq(void)402 void __init sh7367_init_irq(void)
403 {
404 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
405
406 register_intc_controller(&intca_desc);
407 register_intc_controller(&intca_irq_pins_desc);
408 register_intc_controller(&intcs_desc);
409
410 /* demux using INTEVTSA */
411 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
412 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
413 }
414