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1/*
2 *  linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
3 *
4 *  Copyright (C) 1999-2001 ARM Limited
5 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
6 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm926.
25 *
26 *  CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
27 */
28#include <linux/linkage.h>
29#include <linux/init.h>
30#include <asm/assembler.h>
31#include <asm/hwcap.h>
32#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h>
34#include <asm/page.h>
35#include <asm/ptrace.h>
36#include "proc-macros.S"
37
38/*
39 * This is the maximum size of an area which will be invalidated
40 * using the single invalidate entry instructions.  Anything larger
41 * than this, and we go for the whole cache.
42 *
43 * This value should be chosen such that we choose the cheapest
44 * alternative.
45 */
46#define CACHE_DLIMIT	16384
47
48/*
49 * the cache line size of the I and D cache
50 */
51#define CACHE_DLINESIZE	32
52
53	.text
54/*
55 * cpu_arm926_proc_init()
56 */
57ENTRY(cpu_arm926_proc_init)
58	mov	pc, lr
59
60/*
61 * cpu_arm926_proc_fin()
62 */
63ENTRY(cpu_arm926_proc_fin)
64	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
65	bic	r0, r0, #0x1000			@ ...i............
66	bic	r0, r0, #0x000e			@ ............wca.
67	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
68	mov	pc, lr
69
70/*
71 * cpu_arm926_reset(loc)
72 *
73 * Perform a soft reset of the system.  Put the CPU into the
74 * same state as it would be if it had been reset, and branch
75 * to what would be the reset vector.
76 *
77 * loc: location to jump to for soft reset
78 */
79	.align	5
80	.pushsection	.idmap.text, "ax"
81ENTRY(cpu_arm926_reset)
82	mov	ip, #0
83	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
84	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
85#ifdef CONFIG_MMU
86	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
87#endif
88	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
89	bic	ip, ip, #0x000f			@ ............wcam
90	bic	ip, ip, #0x1100			@ ...i...s........
91	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
92	mov	pc, r0
93ENDPROC(cpu_arm926_reset)
94	.popsection
95
96/*
97 * cpu_arm926_do_idle()
98 *
99 * Called with IRQs disabled
100 */
101	.align	10
102ENTRY(cpu_arm926_do_idle)
103	mov	r0, #0
104	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
105	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
106	bic	r2, r1, #1 << 12
107	mrs	r3, cpsr			@ Disable FIQs while Icache
108	orr	ip, r3, #PSR_F_BIT		@ is disabled
109	msr	cpsr_c, ip
110	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
111	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
112	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
113	msr	cpsr_c, r3			@ Restore FIQ state
114	mov	pc, lr
115
116/*
117 *	flush_icache_all()
118 *
119 *	Unconditionally clean and invalidate the entire icache.
120 */
121ENTRY(arm926_flush_icache_all)
122	mov	r0, #0
123	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
124	mov	pc, lr
125ENDPROC(arm926_flush_icache_all)
126
127/*
128 *	flush_user_cache_all()
129 *
130 *	Clean and invalidate all cache entries in a particular
131 *	address space.
132 */
133ENTRY(arm926_flush_user_cache_all)
134	/* FALLTHROUGH */
135
136/*
137 *	flush_kern_cache_all()
138 *
139 *	Clean and invalidate the entire cache.
140 */
141ENTRY(arm926_flush_kern_cache_all)
142	mov	r2, #VM_EXEC
143	mov	ip, #0
144__flush_whole_cache:
145#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
146	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
147#else
1481:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
149	bne	1b
150#endif
151	tst	r2, #VM_EXEC
152	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
153	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
154	mov	pc, lr
155
156/*
157 *	flush_user_cache_range(start, end, flags)
158 *
159 *	Clean and invalidate a range of cache entries in the
160 *	specified address range.
161 *
162 *	- start	- start address (inclusive)
163 *	- end	- end address (exclusive)
164 *	- flags	- vm_flags describing address space
165 */
166ENTRY(arm926_flush_user_cache_range)
167	mov	ip, #0
168	sub	r3, r1, r0			@ calculate total size
169	cmp	r3, #CACHE_DLIMIT
170	bgt	__flush_whole_cache
1711:	tst	r2, #VM_EXEC
172#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
173	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
174	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
175	add	r0, r0, #CACHE_DLINESIZE
176	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
177	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
178	add	r0, r0, #CACHE_DLINESIZE
179#else
180	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
181	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
182	add	r0, r0, #CACHE_DLINESIZE
183	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
184	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
185	add	r0, r0, #CACHE_DLINESIZE
186#endif
187	cmp	r0, r1
188	blo	1b
189	tst	r2, #VM_EXEC
190	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
191	mov	pc, lr
192
193/*
194 *	coherent_kern_range(start, end)
195 *
196 *	Ensure coherency between the Icache and the Dcache in the
197 *	region described by start, end.  If you have non-snooping
198 *	Harvard caches, you need to implement this function.
199 *
200 *	- start	- virtual start address
201 *	- end	- virtual end address
202 */
203ENTRY(arm926_coherent_kern_range)
204	/* FALLTHROUGH */
205
206/*
207 *	coherent_user_range(start, end)
208 *
209 *	Ensure coherency between the Icache and the Dcache in the
210 *	region described by start, end.  If you have non-snooping
211 *	Harvard caches, you need to implement this function.
212 *
213 *	- start	- virtual start address
214 *	- end	- virtual end address
215 */
216ENTRY(arm926_coherent_user_range)
217	bic	r0, r0, #CACHE_DLINESIZE - 1
2181:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
219	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
220	add	r0, r0, #CACHE_DLINESIZE
221	cmp	r0, r1
222	blo	1b
223	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
224	mov	pc, lr
225
226/*
227 *	flush_kern_dcache_area(void *addr, size_t size)
228 *
229 *	Ensure no D cache aliasing occurs, either with itself or
230 *	the I cache
231 *
232 *	- addr	- kernel address
233 *	- size	- region size
234 */
235ENTRY(arm926_flush_kern_dcache_area)
236	add	r1, r0, r1
2371:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
238	add	r0, r0, #CACHE_DLINESIZE
239	cmp	r0, r1
240	blo	1b
241	mov	r0, #0
242	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
243	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
244	mov	pc, lr
245
246/*
247 *	dma_inv_range(start, end)
248 *
249 *	Invalidate (discard) the specified virtual address range.
250 *	May not write back any entries.  If 'start' or 'end'
251 *	are not cache line aligned, those lines must be written
252 *	back.
253 *
254 *	- start	- virtual start address
255 *	- end	- virtual end address
256 *
257 * (same as v4wb)
258 */
259arm926_dma_inv_range:
260#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
261	tst	r0, #CACHE_DLINESIZE - 1
262	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
263	tst	r1, #CACHE_DLINESIZE - 1
264	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
265#endif
266	bic	r0, r0, #CACHE_DLINESIZE - 1
2671:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
268	add	r0, r0, #CACHE_DLINESIZE
269	cmp	r0, r1
270	blo	1b
271	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
272	mov	pc, lr
273
274/*
275 *	dma_clean_range(start, end)
276 *
277 *	Clean the specified virtual address range.
278 *
279 *	- start	- virtual start address
280 *	- end	- virtual end address
281 *
282 * (same as v4wb)
283 */
284arm926_dma_clean_range:
285#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
286	bic	r0, r0, #CACHE_DLINESIZE - 1
2871:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
288	add	r0, r0, #CACHE_DLINESIZE
289	cmp	r0, r1
290	blo	1b
291#endif
292	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
293	mov	pc, lr
294
295/*
296 *	dma_flush_range(start, end)
297 *
298 *	Clean and invalidate the specified virtual address range.
299 *
300 *	- start	- virtual start address
301 *	- end	- virtual end address
302 */
303ENTRY(arm926_dma_flush_range)
304	bic	r0, r0, #CACHE_DLINESIZE - 1
3051:
306#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
307	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
308#else
309	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
310#endif
311	add	r0, r0, #CACHE_DLINESIZE
312	cmp	r0, r1
313	blo	1b
314	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
315	mov	pc, lr
316
317/*
318 *	dma_map_area(start, size, dir)
319 *	- start	- kernel virtual start address
320 *	- size	- size of region
321 *	- dir	- DMA direction
322 */
323ENTRY(arm926_dma_map_area)
324	add	r1, r1, r0
325	cmp	r2, #DMA_TO_DEVICE
326	beq	arm926_dma_clean_range
327	bcs	arm926_dma_inv_range
328	b	arm926_dma_flush_range
329ENDPROC(arm926_dma_map_area)
330
331/*
332 *	dma_unmap_area(start, size, dir)
333 *	- start	- kernel virtual start address
334 *	- size	- size of region
335 *	- dir	- DMA direction
336 */
337ENTRY(arm926_dma_unmap_area)
338	mov	pc, lr
339ENDPROC(arm926_dma_unmap_area)
340
341	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
342	define_cache_functions arm926
343
344ENTRY(cpu_arm926_dcache_clean_area)
345#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
3461:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
347	add	r0, r0, #CACHE_DLINESIZE
348	subs	r1, r1, #CACHE_DLINESIZE
349	bhi	1b
350#endif
351	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
352	mov	pc, lr
353
354/* =============================== PageTable ============================== */
355
356/*
357 * cpu_arm926_switch_mm(pgd)
358 *
359 * Set the translation base pointer to be as described by pgd.
360 *
361 * pgd: new page tables
362 */
363	.align	5
364ENTRY(cpu_arm926_switch_mm)
365#ifdef CONFIG_MMU
366	mov	ip, #0
367#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
368	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
369#else
370@ && 'Clean & Invalidate whole DCache'
3711:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
372	bne	1b
373#endif
374	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
375	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
376	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
377	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
378#endif
379	mov	pc, lr
380
381/*
382 * cpu_arm926_set_pte_ext(ptep, pte, ext)
383 *
384 * Set a PTE and flush it out
385 */
386	.align	5
387ENTRY(cpu_arm926_set_pte_ext)
388#ifdef CONFIG_MMU
389	armv3_set_pte_ext
390	mov	r0, r0
391#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
392	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
393#endif
394	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
395#endif
396	mov	pc, lr
397
398/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
399.globl	cpu_arm926_suspend_size
400.equ	cpu_arm926_suspend_size, 4 * 3
401#ifdef CONFIG_ARM_CPU_SUSPEND
402ENTRY(cpu_arm926_do_suspend)
403	stmfd	sp!, {r4 - r6, lr}
404	mrc	p15, 0, r4, c13, c0, 0	@ PID
405	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
406	mrc	p15, 0, r6, c1, c0, 0	@ Control register
407	stmia	r0, {r4 - r6}
408	ldmfd	sp!, {r4 - r6, pc}
409ENDPROC(cpu_arm926_do_suspend)
410
411ENTRY(cpu_arm926_do_resume)
412	mov	ip, #0
413	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
414	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
415	ldmia	r0, {r4 - r6}
416	mcr	p15, 0, r4, c13, c0, 0	@ PID
417	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
418	mcr	p15, 0, r1, c2, c0, 0	@ TTB address
419	mov	r0, r6			@ control register
420	b	cpu_resume_mmu
421ENDPROC(cpu_arm926_do_resume)
422#endif
423
424	__CPUINIT
425
426	.type	__arm926_setup, #function
427__arm926_setup:
428	mov	r0, #0
429	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
430	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
431#ifdef CONFIG_MMU
432	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
433#endif
434
435
436#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
437	mov	r0, #4				@ disable write-back on caches explicitly
438	mcr	p15, 7, r0, c15, c0, 0
439#endif
440
441	adr	r5, arm926_crval
442	ldmia	r5, {r5, r6}
443	mrc	p15, 0, r0, c1, c0		@ get control register v4
444	bic	r0, r0, r5
445	orr	r0, r0, r6
446#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
447	orr	r0, r0, #0x4000			@ .1.. .... .... ....
448#endif
449	mov	pc, lr
450	.size	__arm926_setup, . - __arm926_setup
451
452	/*
453	 *  R
454	 * .RVI ZFRS BLDP WCAM
455	 * .011 0001 ..11 0101
456	 *
457	 */
458	.type	arm926_crval, #object
459arm926_crval:
460	crval	clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
461
462	__INITDATA
463
464	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
465	define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
466
467	.section ".rodata"
468
469	string	cpu_arch_name, "armv5tej"
470	string	cpu_elf_name, "v5"
471	string	cpu_arm926_name, "ARM926EJ-S"
472
473	.align
474
475	.section ".proc.info.init", #alloc, #execinstr
476
477	.type	__arm926_proc_info,#object
478__arm926_proc_info:
479	.long	0x41069260			@ ARM926EJ-S (v5TEJ)
480	.long	0xff0ffff0
481	.long   PMD_TYPE_SECT | \
482		PMD_SECT_BUFFERABLE | \
483		PMD_SECT_CACHEABLE | \
484		PMD_BIT4 | \
485		PMD_SECT_AP_WRITE | \
486		PMD_SECT_AP_READ
487	.long   PMD_TYPE_SECT | \
488		PMD_BIT4 | \
489		PMD_SECT_AP_WRITE | \
490		PMD_SECT_AP_READ
491	b	__arm926_setup
492	.long	cpu_arch_name
493	.long	cpu_elf_name
494	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
495	.long	cpu_arm926_name
496	.long	arm926_processor_functions
497	.long	v4wbi_tlb_fns
498	.long	v4wb_user_fns
499	.long	arm926_cache_fns
500	.size	__arm926_proc_info, . - __arm926_proc_info
501