1 #ifndef __iop_scrc_out_defs_h 2 #define __iop_scrc_out_defs_h 3 4 /* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/iop_scrc_out.r 7 * id: iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp 8 * last modfied: Mon Apr 11 16:08:46 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_scrc_out_defs.h ../../inst/io_proc/rtl/iop_scrc_out.r 11 * id: $Id: iop_scrc_out_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 /* Main access macros */ 17 #ifndef REG_RD 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #endif 22 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #endif 28 29 #ifndef REG_RD_VECT 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) 34 #endif 35 36 #ifndef REG_WR_VECT 37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 38 REG_WRITE( reg_##scope##_##reg, \ 39 (inst) + REG_WR_ADDR_##scope##_##reg + \ 40 (index) * STRIDE_##scope##_##reg, (val) ) 41 #endif 42 43 #ifndef REG_RD_INT 44 #define REG_RD_INT( scope, inst, reg ) \ 45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 46 #endif 47 48 #ifndef REG_WR_INT 49 #define REG_WR_INT( scope, inst, reg, val ) \ 50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 51 #endif 52 53 #ifndef REG_RD_INT_VECT 54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 56 (index) * STRIDE_##scope##_##reg ) 57 #endif 58 59 #ifndef REG_WR_INT_VECT 60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 62 (index) * STRIDE_##scope##_##reg, (val) ) 63 #endif 64 65 #ifndef REG_TYPE_CONV 66 #define REG_TYPE_CONV( type, orgtype, val ) \ 67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 68 #endif 69 70 #ifndef reg_page_size 71 #define reg_page_size 8192 72 #endif 73 74 #ifndef REG_ADDR 75 #define REG_ADDR( scope, inst, reg ) \ 76 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 77 #endif 78 79 #ifndef REG_ADDR_VECT 80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 82 (index) * STRIDE_##scope##_##reg ) 83 #endif 84 85 /* C-code for register scope iop_scrc_out */ 86 87 /* Register rw_cfg, scope iop_scrc_out, type rw */ 88 typedef struct { 89 unsigned int trig : 2; 90 unsigned int inv_crc : 1; 91 unsigned int dummy1 : 29; 92 } reg_iop_scrc_out_rw_cfg; 93 #define REG_RD_ADDR_iop_scrc_out_rw_cfg 0 94 #define REG_WR_ADDR_iop_scrc_out_rw_cfg 0 95 96 /* Register rw_ctrl, scope iop_scrc_out, type rw */ 97 typedef struct { 98 unsigned int strb_src : 1; 99 unsigned int out_src : 1; 100 unsigned int dummy1 : 30; 101 } reg_iop_scrc_out_rw_ctrl; 102 #define REG_RD_ADDR_iop_scrc_out_rw_ctrl 4 103 #define REG_WR_ADDR_iop_scrc_out_rw_ctrl 4 104 105 /* Register rw_init_crc, scope iop_scrc_out, type rw */ 106 typedef unsigned int reg_iop_scrc_out_rw_init_crc; 107 #define REG_RD_ADDR_iop_scrc_out_rw_init_crc 8 108 #define REG_WR_ADDR_iop_scrc_out_rw_init_crc 8 109 110 /* Register rw_crc, scope iop_scrc_out, type rw */ 111 typedef unsigned int reg_iop_scrc_out_rw_crc; 112 #define REG_RD_ADDR_iop_scrc_out_rw_crc 12 113 #define REG_WR_ADDR_iop_scrc_out_rw_crc 12 114 115 /* Register rw_data, scope iop_scrc_out, type rw */ 116 typedef struct { 117 unsigned int val : 1; 118 unsigned int dummy1 : 31; 119 } reg_iop_scrc_out_rw_data; 120 #define REG_RD_ADDR_iop_scrc_out_rw_data 16 121 #define REG_WR_ADDR_iop_scrc_out_rw_data 16 122 123 /* Register r_computed_crc, scope iop_scrc_out, type r */ 124 typedef unsigned int reg_iop_scrc_out_r_computed_crc; 125 #define REG_RD_ADDR_iop_scrc_out_r_computed_crc 20 126 127 128 /* Constants */ 129 enum { 130 regk_iop_scrc_out_crc = 0x00000001, 131 regk_iop_scrc_out_data = 0x00000000, 132 regk_iop_scrc_out_dif = 0x00000001, 133 regk_iop_scrc_out_hi = 0x00000000, 134 regk_iop_scrc_out_neg = 0x00000002, 135 regk_iop_scrc_out_no = 0x00000000, 136 regk_iop_scrc_out_pos = 0x00000001, 137 regk_iop_scrc_out_pos_neg = 0x00000003, 138 regk_iop_scrc_out_reg = 0x00000000, 139 regk_iop_scrc_out_rw_cfg_default = 0x00000000, 140 regk_iop_scrc_out_rw_crc_default = 0x00000000, 141 regk_iop_scrc_out_rw_ctrl_default = 0x00000000, 142 regk_iop_scrc_out_rw_data_default = 0x00000000, 143 regk_iop_scrc_out_rw_init_crc_default = 0x00000000, 144 regk_iop_scrc_out_yes = 0x00000001 145 }; 146 #endif /* __iop_scrc_out_defs_h */ 147