1#ifndef STARTUP_INC_INCLUDED 2#define STARTUP_INC_INCLUDED 3 4#include <hwregs/asm/reg_map_asm.h> 5#include <hwregs/asm/bif_core_defs_asm.h> 6#include <hwregs/asm/gio_defs_asm.h> 7#include <hwregs/asm/config_defs_asm.h> 8 9 .macro GIO_INIT 10 move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 11 move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 12 move.d $r0, [$r1] 13 14 move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 15 move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 16 move.d $r0, [$r1] 17 18 move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 19 move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 20 move.d $r0, [$r1] 21 22 move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 23 move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 24 move.d $r0, [$r1] 25 26 move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 27 move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 28 move.d $r0, [$r1] 29 30 move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 31 move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 32 move.d $r0, [$r1] 33 34 move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 35 move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 36 move.d $r0, [$r1] 37 38 move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 39 move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 40 move.d $r0, [$r1] 41 42 move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 43 move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 44 move.d $r0, [$r1] 45 46 move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 47 move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 48 move.d $r0, [$r1] 49 .endm 50 51 .macro START_CLOCKS 52 move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 53 move.d [$r1], $r0 54 or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ 55 REG_STATE(config, rw_clk_ctrl, bif, yes) | \ 56 REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 57 move.d $r0, [$r1] 58 .endm 59 60 .macro SETUP_WAIT_STATES 61 ;; Set up waitstates etc 62 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 63 move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 64 move.d $r1, [$r0] 65 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 66 move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 67 move.d $r1, [$r0] 68 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 69 move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 70 move.d $r1, [$r0] 71 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 72 move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 73 move.d $r1, [$r0] 74#ifdef CONFIG_ETRAX_VCS_SIM 75 ;; Set up minimal flash waitstates 76 move.d 0, $r10 77 move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11 78 move.d $r10, [$r11] 79#endif 80 .endm 81 82#endif 83