1 /*
2 * linux/arch/m32r/mm/fault.c
3 *
4 * Copyright (c) 2001, 2002 Hitoshi Yamamoto, and H. Kondo
5 * Copyright (c) 2004 Naoto Sugai, NIIBE Yutaka
6 *
7 * Some code taken from i386 version.
8 * Copyright (C) 1995 Linus Torvalds
9 */
10
11 #include <linux/signal.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/errno.h>
15 #include <linux/string.h>
16 #include <linux/types.h>
17 #include <linux/ptrace.h>
18 #include <linux/mman.h>
19 #include <linux/mm.h>
20 #include <linux/smp.h>
21 #include <linux/interrupt.h>
22 #include <linux/init.h>
23 #include <linux/tty.h>
24 #include <linux/vt_kern.h> /* For unblank_screen() */
25 #include <linux/highmem.h>
26 #include <linux/module.h>
27
28 #include <asm/m32r.h>
29 #include <asm/uaccess.h>
30 #include <asm/hardirq.h>
31 #include <asm/mmu_context.h>
32 #include <asm/tlbflush.h>
33
34 extern void die(const char *, struct pt_regs *, long);
35
36 #ifndef CONFIG_SMP
37 asmlinkage unsigned int tlb_entry_i_dat;
38 asmlinkage unsigned int tlb_entry_d_dat;
39 #define tlb_entry_i tlb_entry_i_dat
40 #define tlb_entry_d tlb_entry_d_dat
41 #else
42 unsigned int tlb_entry_i_dat[NR_CPUS];
43 unsigned int tlb_entry_d_dat[NR_CPUS];
44 #define tlb_entry_i tlb_entry_i_dat[smp_processor_id()]
45 #define tlb_entry_d tlb_entry_d_dat[smp_processor_id()]
46 #endif
47
48 extern void init_tlb(void);
49
50 /*======================================================================*
51 * do_page_fault()
52 *======================================================================*
53 * This routine handles page faults. It determines the address,
54 * and the problem, and then passes it off to one of the appropriate
55 * routines.
56 *
57 * ARGUMENT:
58 * regs : M32R SP reg.
59 * error_code : See below
60 * address : M32R MMU MDEVA reg. (Operand ACE)
61 * : M32R BPC reg. (Instruction ACE)
62 *
63 * error_code :
64 * bit 0 == 0 means no page found, 1 means protection fault
65 * bit 1 == 0 means read, 1 means write
66 * bit 2 == 0 means kernel, 1 means user-mode
67 * bit 3 == 0 means data, 1 means instruction
68 *======================================================================*/
69 #define ACE_PROTECTION 1
70 #define ACE_WRITE 2
71 #define ACE_USERMODE 4
72 #define ACE_INSTRUCTION 8
73
do_page_fault(struct pt_regs * regs,unsigned long error_code,unsigned long address)74 asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
75 unsigned long address)
76 {
77 struct task_struct *tsk;
78 struct mm_struct *mm;
79 struct vm_area_struct * vma;
80 unsigned long page, addr;
81 int write;
82 int fault;
83 siginfo_t info;
84
85 /*
86 * If BPSW IE bit enable --> set PSW IE bit
87 */
88 if (regs->psw & M32R_PSW_BIE)
89 local_irq_enable();
90
91 tsk = current;
92
93 info.si_code = SEGV_MAPERR;
94
95 /*
96 * We fault-in kernel-space virtual memory on-demand. The
97 * 'reference' page table is init_mm.pgd.
98 *
99 * NOTE! We MUST NOT take any locks for this case. We may
100 * be in an interrupt or a critical region, and should
101 * only copy the information from the master page table,
102 * nothing more.
103 *
104 * This verifies that the fault happens in kernel space
105 * (error_code & ACE_USERMODE) == 0, and that the fault was not a
106 * protection error (error_code & ACE_PROTECTION) == 0.
107 */
108 if (address >= TASK_SIZE && !(error_code & ACE_USERMODE))
109 goto vmalloc_fault;
110
111 mm = tsk->mm;
112
113 /*
114 * If we're in an interrupt or have no user context or are running in an
115 * atomic region then we must not take the fault..
116 */
117 if (in_atomic() || !mm)
118 goto bad_area_nosemaphore;
119
120 /* When running in the kernel we expect faults to occur only to
121 * addresses in user space. All other faults represent errors in the
122 * kernel and should generate an OOPS. Unfortunately, in the case of an
123 * erroneous fault occurring in a code path which already holds mmap_sem
124 * we will deadlock attempting to validate the fault against the
125 * address space. Luckily the kernel only validly references user
126 * space from well defined areas of code, which are listed in the
127 * exceptions table.
128 *
129 * As the vast majority of faults will be valid we will only perform
130 * the source reference check when there is a possibility of a deadlock.
131 * Attempt to lock the address space, if we cannot we then validate the
132 * source. If this is invalid we can skip the address space check,
133 * thus avoiding the deadlock.
134 */
135 if (!down_read_trylock(&mm->mmap_sem)) {
136 if ((error_code & ACE_USERMODE) == 0 &&
137 !search_exception_tables(regs->psw))
138 goto bad_area_nosemaphore;
139 down_read(&mm->mmap_sem);
140 }
141
142 vma = find_vma(mm, address);
143 if (!vma)
144 goto bad_area;
145 if (vma->vm_start <= address)
146 goto good_area;
147 if (!(vma->vm_flags & VM_GROWSDOWN))
148 goto bad_area;
149
150 if (error_code & ACE_USERMODE) {
151 /*
152 * accessing the stack below "spu" is always a bug.
153 * The "+ 4" is there due to the push instruction
154 * doing pre-decrement on the stack and that
155 * doesn't show up until later..
156 */
157 if (address + 4 < regs->spu)
158 goto bad_area;
159 }
160
161 if (expand_stack(vma, address))
162 goto bad_area;
163 /*
164 * Ok, we have a good vm_area for this memory access, so
165 * we can handle it..
166 */
167 good_area:
168 info.si_code = SEGV_ACCERR;
169 write = 0;
170 switch (error_code & (ACE_WRITE|ACE_PROTECTION)) {
171 default: /* 3: write, present */
172 /* fall through */
173 case ACE_WRITE: /* write, not present */
174 if (!(vma->vm_flags & VM_WRITE))
175 goto bad_area;
176 write++;
177 break;
178 case ACE_PROTECTION: /* read, present */
179 case 0: /* read, not present */
180 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
181 goto bad_area;
182 }
183
184 /*
185 * For instruction access exception, check if the area is executable
186 */
187 if ((error_code & ACE_INSTRUCTION) && !(vma->vm_flags & VM_EXEC))
188 goto bad_area;
189
190 /*
191 * If for any reason at all we couldn't handle the fault,
192 * make sure we exit gracefully rather than endlessly redo
193 * the fault.
194 */
195 addr = (address & PAGE_MASK);
196 set_thread_fault_code(error_code);
197 fault = handle_mm_fault(mm, vma, addr, write ? FAULT_FLAG_WRITE : 0);
198 if (unlikely(fault & VM_FAULT_ERROR)) {
199 if (fault & VM_FAULT_OOM)
200 goto out_of_memory;
201 else if (fault & VM_FAULT_SIGBUS)
202 goto do_sigbus;
203 BUG();
204 }
205 if (fault & VM_FAULT_MAJOR)
206 tsk->maj_flt++;
207 else
208 tsk->min_flt++;
209 set_thread_fault_code(0);
210 up_read(&mm->mmap_sem);
211 return;
212
213 /*
214 * Something tried to access memory that isn't in our memory map..
215 * Fix it, but check if it's kernel or user first..
216 */
217 bad_area:
218 up_read(&mm->mmap_sem);
219
220 bad_area_nosemaphore:
221 /* User mode accesses just cause a SIGSEGV */
222 if (error_code & ACE_USERMODE) {
223 tsk->thread.address = address;
224 tsk->thread.error_code = error_code | (address >= TASK_SIZE);
225 tsk->thread.trap_no = 14;
226 info.si_signo = SIGSEGV;
227 info.si_errno = 0;
228 /* info.si_code has been set above */
229 info.si_addr = (void __user *)address;
230 force_sig_info(SIGSEGV, &info, tsk);
231 return;
232 }
233
234 no_context:
235 /* Are we prepared to handle this kernel fault? */
236 if (fixup_exception(regs))
237 return;
238
239 /*
240 * Oops. The kernel tried to access some bad page. We'll have to
241 * terminate things with extreme prejudice.
242 */
243
244 bust_spinlocks(1);
245
246 if (address < PAGE_SIZE)
247 printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
248 else
249 printk(KERN_ALERT "Unable to handle kernel paging request");
250 printk(" at virtual address %08lx\n",address);
251 printk(KERN_ALERT " printing bpc:\n");
252 printk("%08lx\n", regs->bpc);
253 page = *(unsigned long *)MPTB;
254 page = ((unsigned long *) page)[address >> PGDIR_SHIFT];
255 printk(KERN_ALERT "*pde = %08lx\n", page);
256 if (page & _PAGE_PRESENT) {
257 page &= PAGE_MASK;
258 address &= 0x003ff000;
259 page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT];
260 printk(KERN_ALERT "*pte = %08lx\n", page);
261 }
262 die("Oops", regs, error_code);
263 bust_spinlocks(0);
264 do_exit(SIGKILL);
265
266 /*
267 * We ran out of memory, or some other thing happened to us that made
268 * us unable to handle the page fault gracefully.
269 */
270 out_of_memory:
271 up_read(&mm->mmap_sem);
272 if (!(error_code & ACE_USERMODE))
273 goto no_context;
274 pagefault_out_of_memory();
275 return;
276
277 do_sigbus:
278 up_read(&mm->mmap_sem);
279
280 /* Kernel mode? Handle exception or die */
281 if (!(error_code & ACE_USERMODE))
282 goto no_context;
283
284 tsk->thread.address = address;
285 tsk->thread.error_code = error_code;
286 tsk->thread.trap_no = 14;
287 info.si_signo = SIGBUS;
288 info.si_errno = 0;
289 info.si_code = BUS_ADRERR;
290 info.si_addr = (void __user *)address;
291 force_sig_info(SIGBUS, &info, tsk);
292 return;
293
294 vmalloc_fault:
295 {
296 /*
297 * Synchronize this task's top level page-table
298 * with the 'reference' page table.
299 *
300 * Do _not_ use "tsk" here. We might be inside
301 * an interrupt in the middle of a task switch..
302 */
303 int offset = pgd_index(address);
304 pgd_t *pgd, *pgd_k;
305 pmd_t *pmd, *pmd_k;
306 pte_t *pte_k;
307
308 pgd = (pgd_t *)*(unsigned long *)MPTB;
309 pgd = offset + (pgd_t *)pgd;
310 pgd_k = init_mm.pgd + offset;
311
312 if (!pgd_present(*pgd_k))
313 goto no_context;
314
315 /*
316 * set_pgd(pgd, *pgd_k); here would be useless on PAE
317 * and redundant with the set_pmd() on non-PAE.
318 */
319
320 pmd = pmd_offset(pgd, address);
321 pmd_k = pmd_offset(pgd_k, address);
322 if (!pmd_present(*pmd_k))
323 goto no_context;
324 set_pmd(pmd, *pmd_k);
325
326 pte_k = pte_offset_kernel(pmd_k, address);
327 if (!pte_present(*pte_k))
328 goto no_context;
329
330 addr = (address & PAGE_MASK);
331 set_thread_fault_code(error_code);
332 update_mmu_cache(NULL, addr, pte_k);
333 set_thread_fault_code(0);
334 return;
335 }
336 }
337
338 /*======================================================================*
339 * update_mmu_cache()
340 *======================================================================*/
341 #define TLB_MASK (NR_TLB_ENTRIES - 1)
342 #define ITLB_END (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8))
343 #define DTLB_END (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8))
update_mmu_cache(struct vm_area_struct * vma,unsigned long vaddr,pte_t * ptep)344 void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
345 pte_t *ptep)
346 {
347 volatile unsigned long *entry1, *entry2;
348 unsigned long pte_data, flags;
349 unsigned int *entry_dat;
350 int inst = get_thread_fault_code() & ACE_INSTRUCTION;
351 int i;
352
353 /* Ptrace may call this routine. */
354 if (vma && current->active_mm != vma->vm_mm)
355 return;
356
357 local_irq_save(flags);
358
359 vaddr = (vaddr & PAGE_MASK) | get_asid();
360
361 pte_data = pte_val(*ptep);
362
363 #ifdef CONFIG_CHIP_OPSP
364 entry1 = (unsigned long *)ITLB_BASE;
365 for (i = 0; i < NR_TLB_ENTRIES; i++) {
366 if (*entry1++ == vaddr) {
367 set_tlb_data(entry1, pte_data);
368 break;
369 }
370 entry1++;
371 }
372 entry2 = (unsigned long *)DTLB_BASE;
373 for (i = 0; i < NR_TLB_ENTRIES; i++) {
374 if (*entry2++ == vaddr) {
375 set_tlb_data(entry2, pte_data);
376 break;
377 }
378 entry2++;
379 }
380 #else
381 /*
382 * Update TLB entries
383 * entry1: ITLB entry address
384 * entry2: DTLB entry address
385 */
386 __asm__ __volatile__ (
387 "seth %0, #high(%4) \n\t"
388 "st %2, @(%5, %0) \n\t"
389 "ldi %1, #1 \n\t"
390 "st %1, @(%6, %0) \n\t"
391 "add3 r4, %0, %7 \n\t"
392 ".fillinsn \n"
393 "1: \n\t"
394 "ld %1, @(%6, %0) \n\t"
395 "bnez %1, 1b \n\t"
396 "ld %0, @r4+ \n\t"
397 "ld %1, @r4 \n\t"
398 "st %3, @+%0 \n\t"
399 "st %3, @+%1 \n\t"
400 : "=&r" (entry1), "=&r" (entry2)
401 : "r" (vaddr), "r" (pte_data), "i" (MMU_REG_BASE),
402 "i" (MSVA_offset), "i" (MTOP_offset), "i" (MIDXI_offset)
403 : "r4", "memory"
404 );
405 #endif
406
407 if ((!inst && entry2 >= DTLB_END) || (inst && entry1 >= ITLB_END))
408 goto notfound;
409
410 found:
411 local_irq_restore(flags);
412
413 return;
414
415 /* Valid entry not found */
416 notfound:
417 /*
418 * Update ITLB or DTLB entry
419 * entry1: TLB entry address
420 * entry2: TLB base address
421 */
422 if (!inst) {
423 entry2 = (unsigned long *)DTLB_BASE;
424 entry_dat = &tlb_entry_d;
425 } else {
426 entry2 = (unsigned long *)ITLB_BASE;
427 entry_dat = &tlb_entry_i;
428 }
429 entry1 = entry2 + (((*entry_dat - 1) & TLB_MASK) << 1);
430
431 for (i = 0 ; i < NR_TLB_ENTRIES ; i++) {
432 if (!(entry1[1] & 2)) /* Valid bit check */
433 break;
434
435 if (entry1 != entry2)
436 entry1 -= 2;
437 else
438 entry1 += TLB_MASK << 1;
439 }
440
441 if (i >= NR_TLB_ENTRIES) { /* Empty entry not found */
442 entry1 = entry2 + (*entry_dat << 1);
443 *entry_dat = (*entry_dat + 1) & TLB_MASK;
444 }
445 *entry1++ = vaddr; /* Set TLB tag */
446 set_tlb_data(entry1, pte_data);
447
448 goto found;
449 }
450
451 /*======================================================================*
452 * flush_tlb_page() : flushes one page
453 *======================================================================*/
local_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)454 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
455 {
456 if (vma->vm_mm && mm_context(vma->vm_mm) != NO_CONTEXT) {
457 unsigned long flags;
458
459 local_irq_save(flags);
460 page &= PAGE_MASK;
461 page |= (mm_context(vma->vm_mm) & MMU_CONTEXT_ASID_MASK);
462 __flush_tlb_page(page);
463 local_irq_restore(flags);
464 }
465 }
466
467 /*======================================================================*
468 * flush_tlb_range() : flushes a range of pages
469 *======================================================================*/
local_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)470 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
471 unsigned long end)
472 {
473 struct mm_struct *mm;
474
475 mm = vma->vm_mm;
476 if (mm_context(mm) != NO_CONTEXT) {
477 unsigned long flags;
478 int size;
479
480 local_irq_save(flags);
481 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
482 if (size > (NR_TLB_ENTRIES / 4)) { /* Too many TLB to flush */
483 mm_context(mm) = NO_CONTEXT;
484 if (mm == current->mm)
485 activate_context(mm);
486 } else {
487 unsigned long asid;
488
489 asid = mm_context(mm) & MMU_CONTEXT_ASID_MASK;
490 start &= PAGE_MASK;
491 end += (PAGE_SIZE - 1);
492 end &= PAGE_MASK;
493
494 start |= asid;
495 end |= asid;
496 while (start < end) {
497 __flush_tlb_page(start);
498 start += PAGE_SIZE;
499 }
500 }
501 local_irq_restore(flags);
502 }
503 }
504
505 /*======================================================================*
506 * flush_tlb_mm() : flushes the specified mm context TLB's
507 *======================================================================*/
local_flush_tlb_mm(struct mm_struct * mm)508 void local_flush_tlb_mm(struct mm_struct *mm)
509 {
510 /* Invalidate all TLB of this process. */
511 /* Instead of invalidating each TLB, we get new MMU context. */
512 if (mm_context(mm) != NO_CONTEXT) {
513 unsigned long flags;
514
515 local_irq_save(flags);
516 mm_context(mm) = NO_CONTEXT;
517 if (mm == current->mm)
518 activate_context(mm);
519 local_irq_restore(flags);
520 }
521 }
522
523 /*======================================================================*
524 * flush_tlb_all() : flushes all processes TLBs
525 *======================================================================*/
local_flush_tlb_all(void)526 void local_flush_tlb_all(void)
527 {
528 unsigned long flags;
529
530 local_irq_save(flags);
531 __flush_tlb_all();
532 local_irq_restore(flags);
533 }
534
535 /*======================================================================*
536 * init_mmu()
537 *======================================================================*/
init_mmu(void)538 void __init init_mmu(void)
539 {
540 tlb_entry_i = 0;
541 tlb_entry_d = 0;
542 mmu_context_cache = MMU_CONTEXT_FIRST_VERSION;
543 set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK);
544 *(volatile unsigned long *)MPTB = (unsigned long)swapper_pg_dir;
545 }
546