1/* 2 * Copyright (C) 2009 Extreme Engineering Solutions, Inc. 3 * Based on TQM8548 device tree 4 * 5 * XPedite5200 PrPMC/XMC module based on MPC8548E. This dts is for the 6 * xMon boot loader memory map which differs from U-Boot's. 7 * 8 * This is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13/dts-v1/; 14 15/ { 16 model = "xes,xpedite5200"; 17 compatible = "xes,xpedite5200", "xes,MPC8548"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 form-factor = "PMC/XMC"; 21 boot-bank = <0x0>; 22 23 aliases { 24 ethernet0 = &enet0; 25 ethernet1 = &enet1; 26 ethernet2 = &enet2; 27 ethernet3 = &enet3; 28 29 serial0 = &serial0; 30 serial1 = &serial1; 31 pci0 = &pci0; 32 pci1 = &pci1; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 PowerPC,8548@0 { 40 device_type = "cpu"; 41 reg = <0>; 42 d-cache-line-size = <32>; // 32 bytes 43 i-cache-line-size = <32>; // 32 bytes 44 d-cache-size = <0x8000>; // L1, 32K 45 i-cache-size = <0x8000>; // L1, 32K 46 next-level-cache = <&L2>; 47 }; 48 }; 49 50 memory { 51 device_type = "memory"; 52 reg = <0x0 0x0>; // Filled in by boot loader 53 }; 54 55 soc@ef000000 { 56 #address-cells = <1>; 57 #size-cells = <1>; 58 device_type = "soc"; 59 ranges = <0x0 0xef000000 0x100000>; 60 bus-frequency = <0>; 61 compatible = "fsl,mpc8548-immr", "simple-bus"; 62 63 ecm-law@0 { 64 compatible = "fsl,ecm-law"; 65 reg = <0x0 0x1000>; 66 fsl,num-laws = <12>; 67 }; 68 69 ecm@1000 { 70 compatible = "fsl,mpc8548-ecm", "fsl,ecm"; 71 reg = <0x1000 0x1000>; 72 interrupts = <17 2>; 73 interrupt-parent = <&mpic>; 74 }; 75 76 memory-controller@2000 { 77 compatible = "fsl,mpc8548-memory-controller"; 78 reg = <0x2000 0x1000>; 79 interrupt-parent = <&mpic>; 80 interrupts = <18 2>; 81 }; 82 83 L2: l2-cache-controller@20000 { 84 compatible = "fsl,mpc8548-l2-cache-controller"; 85 reg = <0x20000 0x1000>; 86 cache-line-size = <32>; // 32 bytes 87 cache-size = <0x80000>; // L2, 512K 88 interrupt-parent = <&mpic>; 89 interrupts = <16 2>; 90 }; 91 92 /* On-card I2C */ 93 i2c@3000 { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 cell-index = <0>; 97 compatible = "fsl-i2c"; 98 reg = <0x3000 0x100>; 99 interrupts = <43 2>; 100 interrupt-parent = <&mpic>; 101 dfsrr; 102 103 /* 104 * Board GPIO: 105 * 0: BRD_CFG0 (1: P14 IO present) 106 * 1: BRD_CFG1 (1: FP ethernet present) 107 * 2: BRD_CFG2 (1: XMC IO present) 108 * 3: XMC root complex indicator 109 * 4: Flash boot device indicator 110 * 5: Flash write protect enable 111 * 6: PMC monarch indicator 112 * 7: PMC EREADY 113 */ 114 gpio1: gpio@18 { 115 compatible = "nxp,pca9556"; 116 reg = <0x18>; 117 #gpio-cells = <2>; 118 gpio-controller; 119 polarity = <0x00>; 120 }; 121 122 /* P14 GPIO */ 123 gpio2: gpio@19 { 124 compatible = "nxp,pca9556"; 125 reg = <0x19>; 126 #gpio-cells = <2>; 127 gpio-controller; 128 polarity = <0x00>; 129 }; 130 131 eeprom@50 { 132 compatible = "atmel,at24c16"; 133 reg = <0x50>; 134 }; 135 136 rtc@68 { 137 compatible = "stm,m41t00", 138 "dallas,ds1338"; 139 reg = <0x68>; 140 }; 141 142 dtt@48 { 143 compatible = "maxim,max1237"; 144 reg = <0x34>; 145 }; 146 }; 147 148 /* Off-card I2C */ 149 i2c@3100 { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 cell-index = <1>; 153 compatible = "fsl-i2c"; 154 reg = <0x3100 0x100>; 155 interrupts = <43 2>; 156 interrupt-parent = <&mpic>; 157 dfsrr; 158 }; 159 160 dma@21300 { 161 #address-cells = <1>; 162 #size-cells = <1>; 163 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma"; 164 reg = <0x21300 0x4>; 165 ranges = <0x0 0x21100 0x200>; 166 cell-index = <0>; 167 dma-channel@0 { 168 compatible = "fsl,mpc8548-dma-channel", 169 "fsl,eloplus-dma-channel"; 170 reg = <0x0 0x80>; 171 cell-index = <0>; 172 interrupt-parent = <&mpic>; 173 interrupts = <20 2>; 174 }; 175 dma-channel@80 { 176 compatible = "fsl,mpc8548-dma-channel", 177 "fsl,eloplus-dma-channel"; 178 reg = <0x80 0x80>; 179 cell-index = <1>; 180 interrupt-parent = <&mpic>; 181 interrupts = <21 2>; 182 }; 183 dma-channel@100 { 184 compatible = "fsl,mpc8548-dma-channel", 185 "fsl,eloplus-dma-channel"; 186 reg = <0x100 0x80>; 187 cell-index = <2>; 188 interrupt-parent = <&mpic>; 189 interrupts = <22 2>; 190 }; 191 dma-channel@180 { 192 compatible = "fsl,mpc8548-dma-channel", 193 "fsl,eloplus-dma-channel"; 194 reg = <0x180 0x80>; 195 cell-index = <3>; 196 interrupt-parent = <&mpic>; 197 interrupts = <23 2>; 198 }; 199 }; 200 201 /* eTSEC1: Front panel port 0 */ 202 enet0: ethernet@24000 { 203 #address-cells = <1>; 204 #size-cells = <1>; 205 cell-index = <0>; 206 device_type = "network"; 207 model = "eTSEC"; 208 compatible = "gianfar"; 209 reg = <0x24000 0x1000>; 210 ranges = <0x0 0x24000 0x1000>; 211 local-mac-address = [ 00 00 00 00 00 00 ]; 212 interrupts = <29 2 30 2 34 2>; 213 interrupt-parent = <&mpic>; 214 tbi-handle = <&tbi0>; 215 phy-handle = <&phy0>; 216 217 mdio@520 { 218 #address-cells = <1>; 219 #size-cells = <0>; 220 compatible = "fsl,gianfar-mdio"; 221 reg = <0x520 0x20>; 222 223 phy0: ethernet-phy@1 { 224 interrupt-parent = <&mpic>; 225 interrupts = <8 1>; 226 reg = <0x1>; 227 }; 228 phy1: ethernet-phy@2 { 229 interrupt-parent = <&mpic>; 230 interrupts = <8 1>; 231 reg = <0x2>; 232 }; 233 phy2: ethernet-phy@3 { 234 interrupt-parent = <&mpic>; 235 interrupts = <8 1>; 236 reg = <0x3>; 237 }; 238 phy3: ethernet-phy@4 { 239 interrupt-parent = <&mpic>; 240 interrupts = <8 1>; 241 reg = <0x4>; 242 }; 243 tbi0: tbi-phy@11 { 244 reg = <0x11>; 245 device_type = "tbi-phy"; 246 }; 247 }; 248 }; 249 250 /* eTSEC2: Front panel port 1 */ 251 enet1: ethernet@25000 { 252 #address-cells = <1>; 253 #size-cells = <1>; 254 cell-index = <1>; 255 device_type = "network"; 256 model = "eTSEC"; 257 compatible = "gianfar"; 258 reg = <0x25000 0x1000>; 259 ranges = <0x0 0x25000 0x1000>; 260 local-mac-address = [ 00 00 00 00 00 00 ]; 261 interrupts = <35 2 36 2 40 2>; 262 interrupt-parent = <&mpic>; 263 tbi-handle = <&tbi1>; 264 phy-handle = <&phy1>; 265 266 mdio@520 { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "fsl,gianfar-tbi"; 270 reg = <0x520 0x20>; 271 272 tbi1: tbi-phy@11 { 273 reg = <0x11>; 274 device_type = "tbi-phy"; 275 }; 276 }; 277 }; 278 279 /* eTSEC3: Rear panel port 2 */ 280 enet2: ethernet@26000 { 281 #address-cells = <1>; 282 #size-cells = <1>; 283 cell-index = <2>; 284 device_type = "network"; 285 model = "eTSEC"; 286 compatible = "gianfar"; 287 reg = <0x26000 0x1000>; 288 ranges = <0x0 0x26000 0x1000>; 289 local-mac-address = [ 00 00 00 00 00 00 ]; 290 interrupts = <31 2 32 2 33 2>; 291 interrupt-parent = <&mpic>; 292 tbi-handle = <&tbi2>; 293 phy-handle = <&phy2>; 294 295 mdio@520 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "fsl,gianfar-tbi"; 299 reg = <0x520 0x20>; 300 301 tbi2: tbi-phy@11 { 302 reg = <0x11>; 303 device_type = "tbi-phy"; 304 }; 305 }; 306 }; 307 308 /* eTSEC4: Rear panel port 3 */ 309 enet3: ethernet@27000 { 310 #address-cells = <1>; 311 #size-cells = <1>; 312 cell-index = <3>; 313 device_type = "network"; 314 model = "eTSEC"; 315 compatible = "gianfar"; 316 reg = <0x27000 0x1000>; 317 ranges = <0x0 0x27000 0x1000>; 318 local-mac-address = [ 00 00 00 00 00 00 ]; 319 interrupts = <37 2 38 2 39 2>; 320 interrupt-parent = <&mpic>; 321 tbi-handle = <&tbi3>; 322 phy-handle = <&phy3>; 323 324 mdio@520 { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 compatible = "fsl,gianfar-tbi"; 328 reg = <0x520 0x20>; 329 330 tbi3: tbi-phy@11 { 331 reg = <0x11>; 332 device_type = "tbi-phy"; 333 }; 334 }; 335 }; 336 337 serial0: serial@4500 { 338 cell-index = <0>; 339 device_type = "serial"; 340 compatible = "fsl,ns16550", "ns16550"; 341 reg = <0x4500 0x100>; 342 clock-frequency = <0>; 343 current-speed = <9600>; 344 interrupts = <42 2>; 345 interrupt-parent = <&mpic>; 346 }; 347 348 serial1: serial@4600 { 349 cell-index = <1>; 350 device_type = "serial"; 351 compatible = "fsl,ns16550", "ns16550"; 352 reg = <0x4600 0x100>; 353 clock-frequency = <0>; 354 current-speed = <9600>; 355 interrupts = <42 2>; 356 interrupt-parent = <&mpic>; 357 }; 358 359 global-utilities@e0000 { // global utilities reg 360 compatible = "fsl,mpc8548-guts"; 361 reg = <0xe0000 0x1000>; 362 fsl,has-rstcr; 363 }; 364 365 mpic: pic@40000 { 366 interrupt-controller; 367 #address-cells = <0>; 368 #interrupt-cells = <2>; 369 reg = <0x40000 0x40000>; 370 compatible = "chrp,open-pic"; 371 device_type = "open-pic"; 372 }; 373 }; 374 375 localbus@ef005000 { 376 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus", 377 "simple-bus"; 378 #address-cells = <2>; 379 #size-cells = <1>; 380 reg = <0xef005000 0x100>; // BRx, ORx, etc. 381 interrupt-parent = <&mpic>; 382 interrupts = <19 2>; 383 384 ranges = < 385 0 0x0 0xf8000000 0x08000000 // NOR boot flash 386 1 0x0 0xf0000000 0x08000000 // NOR expansion flash 387 2 0x0 0xe8000000 0x00010000 // NAND CE1 388 3 0x0 0xe8010000 0x00010000 // NAND CE2 389 >; 390 391 nor-boot@0,0 { 392 #address-cells = <1>; 393 #size-cells = <1>; 394 compatible = "cfi-flash"; 395 reg = <0 0x0 0x4000000>; 396 bank-width = <2>; 397 398 partition@0 { 399 label = "Primary OS"; 400 reg = <0x00000000 0x180000>; 401 }; 402 partition@180000 { 403 label = "Secondary OS"; 404 reg = <0x00180000 0x180000>; 405 }; 406 partition@300000 { 407 label = "User"; 408 reg = <0x00300000 0x3c80000>; 409 }; 410 partition@3f80000 { 411 label = "Boot firmware"; 412 reg = <0x03f80000 0x80000>; 413 }; 414 }; 415 416 nor-alternate@1,0 { 417 #address-cells = <1>; 418 #size-cells = <1>; 419 compatible = "cfi-flash"; 420 reg = <1 0x0 0x4000000>; 421 bank-width = <2>; 422 423 partition@0 { 424 label = "Filesystem"; 425 reg = <0x00000000 0x3f80000>; 426 }; 427 partition@3f80000 { 428 label = "Alternate boot firmware"; 429 reg = <0x03f80000 0x80000>; 430 }; 431 }; 432 433 nand@2,0 { 434 #address-cells = <1>; 435 #size-cells = <1>; 436 compatible = "xes,address-ctl-nand"; 437 reg = <2 0x0 0x10000>; 438 cle-line = <0x8>; /* CLE tied to A3 */ 439 ale-line = <0x10>; /* ALE tied to A4 */ 440 441 partition@0 { 442 label = "NAND Filesystem"; 443 reg = <0 0x40000000>; 444 }; 445 }; 446 }; 447 448 /* PMC interface */ 449 pci0: pci@ef008000 { 450 #interrupt-cells = <1>; 451 #size-cells = <2>; 452 #address-cells = <3>; 453 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 454 device_type = "pci"; 455 reg = <0xef008000 0x1000>; 456 clock-frequency = <33333333>; 457 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 458 interrupt-map = < 459 /* IDSEL */ 460 0xe000 0 0 1 &mpic 2 1 461 0xe000 0 0 2 &mpic 3 1>; 462 463 interrupt-parent = <&mpic>; 464 interrupts = <24 2>; 465 bus-range = <0 0>; 466 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 467 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>; 468 }; 469 470 /* XMC PCIe */ 471 pci1: pcie@ef00a000 { 472 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 473 interrupt-map = < 474 /* IDSEL 0x0 */ 475 0x00000 0 0 1 &mpic 0 1 476 0x00000 0 0 2 &mpic 1 1 477 0x00000 0 0 3 &mpic 2 1 478 0x00000 0 0 4 &mpic 3 1>; 479 480 interrupt-parent = <&mpic>; 481 interrupts = <26 2>; 482 bus-range = <0 0xff>; 483 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 484 0x01000000 0 0x00000000 0xd1000000 0 0x01000000>; 485 clock-frequency = <33333333>; 486 #interrupt-cells = <1>; 487 #size-cells = <2>; 488 #address-cells = <3>; 489 reg = <0xef00a000 0x1000>; 490 compatible = "fsl,mpc8548-pcie"; 491 device_type = "pci"; 492 pcie@0 { 493 reg = <0 0 0 0 0>; 494 #size-cells = <2>; 495 #address-cells = <3>; 496 device_type = "pci"; 497 ranges = <0x02000000 0 0xc0000000 0x02000000 0 498 0xc0000000 0 0x20000000 499 0x01000000 0 0x00000000 0x01000000 0 500 0x00000000 0 0x08000000>; 501 }; 502 }; 503 504 /* Needed for dtbImage boot wrapper compatibility */ 505 chosen { 506 linux,stdout-path = &serial0; 507 }; 508}; 509