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1 /*
2  * linux/arch/unicore32/kernel/irq.c
3  *
4  * Code specific to PKUnity SoC and UniCore ISA
5  *
6  * Copyright (C) 2001-2010 GUAN Xue-tao
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/signal.h>
15 #include <linux/ioport.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/random.h>
19 #include <linux/smp.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/errno.h>
23 #include <linux/list.h>
24 #include <linux/kallsyms.h>
25 #include <linux/proc_fs.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/gpio.h>
28 
29 #include <mach/hardware.h>
30 
31 #include "setup.h"
32 
33 /*
34  * PKUnity GPIO edge detection for IRQs:
35  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
36  * Use this instead of directly setting GRER/GFER.
37  */
38 static int GPIO_IRQ_rising_edge;
39 static int GPIO_IRQ_falling_edge;
40 static int GPIO_IRQ_mask = 0;
41 
42 #define GPIO_MASK(irq)		(1 << (irq - IRQ_GPIO0))
43 
puv3_gpio_type(struct irq_data * d,unsigned int type)44 static int puv3_gpio_type(struct irq_data *d, unsigned int type)
45 {
46 	unsigned int mask;
47 
48 	if (d->irq < IRQ_GPIOHIGH)
49 		mask = 1 << d->irq;
50 	else
51 		mask = GPIO_MASK(d->irq);
52 
53 	if (type == IRQ_TYPE_PROBE) {
54 		if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
55 			return 0;
56 		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
57 	}
58 
59 	if (type & IRQ_TYPE_EDGE_RISING)
60 		GPIO_IRQ_rising_edge |= mask;
61 	else
62 		GPIO_IRQ_rising_edge &= ~mask;
63 	if (type & IRQ_TYPE_EDGE_FALLING)
64 		GPIO_IRQ_falling_edge |= mask;
65 	else
66 		GPIO_IRQ_falling_edge &= ~mask;
67 
68 	writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
69 	writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
70 
71 	return 0;
72 }
73 
74 /*
75  * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 7.
76  */
puv3_low_gpio_ack(struct irq_data * d)77 static void puv3_low_gpio_ack(struct irq_data *d)
78 {
79 	writel((1 << d->irq), GPIO_GEDR);
80 }
81 
puv3_low_gpio_mask(struct irq_data * d)82 static void puv3_low_gpio_mask(struct irq_data *d)
83 {
84 	writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
85 }
86 
puv3_low_gpio_unmask(struct irq_data * d)87 static void puv3_low_gpio_unmask(struct irq_data *d)
88 {
89 	writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR);
90 }
91 
puv3_low_gpio_wake(struct irq_data * d,unsigned int on)92 static int puv3_low_gpio_wake(struct irq_data *d, unsigned int on)
93 {
94 	if (on)
95 		writel(readl(PM_PWER) | (1 << d->irq), PM_PWER);
96 	else
97 		writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER);
98 	return 0;
99 }
100 
101 static struct irq_chip puv3_low_gpio_chip = {
102 	.name		= "GPIO-low",
103 	.irq_ack	= puv3_low_gpio_ack,
104 	.irq_mask	= puv3_low_gpio_mask,
105 	.irq_unmask	= puv3_low_gpio_unmask,
106 	.irq_set_type	= puv3_gpio_type,
107 	.irq_set_wake	= puv3_low_gpio_wake,
108 };
109 
110 /*
111  * IRQ8 (GPIO0 through 27) handler.  We enter here with the
112  * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
113  * and call the handler.
114  */
115 static void
puv3_gpio_handler(unsigned int irq,struct irq_desc * desc)116 puv3_gpio_handler(unsigned int irq, struct irq_desc *desc)
117 {
118 	unsigned int mask;
119 
120 	mask = readl(GPIO_GEDR);
121 	do {
122 		/*
123 		 * clear down all currently active IRQ sources.
124 		 * We will be processing them all.
125 		 */
126 		writel(mask, GPIO_GEDR);
127 
128 		irq = IRQ_GPIO0;
129 		do {
130 			if (mask & 1)
131 				generic_handle_irq(irq);
132 			mask >>= 1;
133 			irq++;
134 		} while (mask);
135 		mask = readl(GPIO_GEDR);
136 	} while (mask);
137 }
138 
139 /*
140  * GPIO0-27 edge IRQs need to be handled specially.
141  * In addition, the IRQs are all collected up into one bit in the
142  * interrupt controller registers.
143  */
puv3_high_gpio_ack(struct irq_data * d)144 static void puv3_high_gpio_ack(struct irq_data *d)
145 {
146 	unsigned int mask = GPIO_MASK(d->irq);
147 
148 	writel(mask, GPIO_GEDR);
149 }
150 
puv3_high_gpio_mask(struct irq_data * d)151 static void puv3_high_gpio_mask(struct irq_data *d)
152 {
153 	unsigned int mask = GPIO_MASK(d->irq);
154 
155 	GPIO_IRQ_mask &= ~mask;
156 
157 	writel(readl(GPIO_GRER) & ~mask, GPIO_GRER);
158 	writel(readl(GPIO_GFER) & ~mask, GPIO_GFER);
159 }
160 
puv3_high_gpio_unmask(struct irq_data * d)161 static void puv3_high_gpio_unmask(struct irq_data *d)
162 {
163 	unsigned int mask = GPIO_MASK(d->irq);
164 
165 	GPIO_IRQ_mask |= mask;
166 
167 	writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
168 	writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
169 }
170 
puv3_high_gpio_wake(struct irq_data * d,unsigned int on)171 static int puv3_high_gpio_wake(struct irq_data *d, unsigned int on)
172 {
173 	if (on)
174 		writel(readl(PM_PWER) | PM_PWER_GPIOHIGH, PM_PWER);
175 	else
176 		writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER);
177 	return 0;
178 }
179 
180 static struct irq_chip puv3_high_gpio_chip = {
181 	.name		= "GPIO-high",
182 	.irq_ack	= puv3_high_gpio_ack,
183 	.irq_mask	= puv3_high_gpio_mask,
184 	.irq_unmask	= puv3_high_gpio_unmask,
185 	.irq_set_type	= puv3_gpio_type,
186 	.irq_set_wake	= puv3_high_gpio_wake,
187 };
188 
189 /*
190  * We don't need to ACK IRQs on the PKUnity unless they're GPIOs
191  * this is for internal IRQs i.e. from 8 to 31.
192  */
puv3_mask_irq(struct irq_data * d)193 static void puv3_mask_irq(struct irq_data *d)
194 {
195 	writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
196 }
197 
puv3_unmask_irq(struct irq_data * d)198 static void puv3_unmask_irq(struct irq_data *d)
199 {
200 	writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR);
201 }
202 
203 /*
204  * Apart form GPIOs, only the RTC alarm can be a wakeup event.
205  */
puv3_set_wake(struct irq_data * d,unsigned int on)206 static int puv3_set_wake(struct irq_data *d, unsigned int on)
207 {
208 	if (d->irq == IRQ_RTCAlarm) {
209 		if (on)
210 			writel(readl(PM_PWER) | PM_PWER_RTC, PM_PWER);
211 		else
212 			writel(readl(PM_PWER) & ~PM_PWER_RTC, PM_PWER);
213 		return 0;
214 	}
215 	return -EINVAL;
216 }
217 
218 static struct irq_chip puv3_normal_chip = {
219 	.name		= "PKUnity-v3",
220 	.irq_ack	= puv3_mask_irq,
221 	.irq_mask	= puv3_mask_irq,
222 	.irq_unmask	= puv3_unmask_irq,
223 	.irq_set_wake	= puv3_set_wake,
224 };
225 
226 static struct resource irq_resource = {
227 	.name	= "irqs",
228 	.start	= io_v2p(PKUNITY_INTC_BASE),
229 	.end	= io_v2p(PKUNITY_INTC_BASE) + 0xFFFFF,
230 };
231 
232 static struct puv3_irq_state {
233 	unsigned int	saved;
234 	unsigned int	icmr;
235 	unsigned int	iclr;
236 	unsigned int	iccr;
237 } puv3_irq_state;
238 
puv3_irq_suspend(void)239 static int puv3_irq_suspend(void)
240 {
241 	struct puv3_irq_state *st = &puv3_irq_state;
242 
243 	st->saved = 1;
244 	st->icmr = readl(INTC_ICMR);
245 	st->iclr = readl(INTC_ICLR);
246 	st->iccr = readl(INTC_ICCR);
247 
248 	/*
249 	 * Disable all GPIO-based interrupts.
250 	 */
251 	writel(readl(INTC_ICMR) & ~(0x1ff), INTC_ICMR);
252 
253 	/*
254 	 * Set the appropriate edges for wakeup.
255 	 */
256 	writel(readl(PM_PWER) & GPIO_IRQ_rising_edge, GPIO_GRER);
257 	writel(readl(PM_PWER) & GPIO_IRQ_falling_edge, GPIO_GFER);
258 
259 	/*
260 	 * Clear any pending GPIO interrupts.
261 	 */
262 	writel(readl(GPIO_GEDR), GPIO_GEDR);
263 
264 	return 0;
265 }
266 
puv3_irq_resume(void)267 static void puv3_irq_resume(void)
268 {
269 	struct puv3_irq_state *st = &puv3_irq_state;
270 
271 	if (st->saved) {
272 		writel(st->iccr, INTC_ICCR);
273 		writel(st->iclr, INTC_ICLR);
274 
275 		writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
276 		writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
277 
278 		writel(st->icmr, INTC_ICMR);
279 	}
280 }
281 
282 static struct syscore_ops puv3_irq_syscore_ops = {
283 	.suspend	= puv3_irq_suspend,
284 	.resume		= puv3_irq_resume,
285 };
286 
puv3_irq_init_syscore(void)287 static int __init puv3_irq_init_syscore(void)
288 {
289 	register_syscore_ops(&puv3_irq_syscore_ops);
290 	return 0;
291 }
292 
293 device_initcall(puv3_irq_init_syscore);
294 
init_IRQ(void)295 void __init init_IRQ(void)
296 {
297 	unsigned int irq;
298 
299 	request_resource(&iomem_resource, &irq_resource);
300 
301 	/* disable all IRQs */
302 	writel(0, INTC_ICMR);
303 
304 	/* all IRQs are IRQ, not REAL */
305 	writel(0, INTC_ICLR);
306 
307 	/* clear all GPIO edge detects */
308 	writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR);
309 	writel(0, GPIO_GFER);
310 	writel(0, GPIO_GRER);
311 	writel(0x0FFFFFFF, GPIO_GEDR);
312 
313 	writel(1, INTC_ICCR);
314 
315 	for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
316 		irq_set_chip(irq, &puv3_low_gpio_chip);
317 		irq_set_handler(irq, handle_edge_irq);
318 		irq_modify_status(irq,
319 			IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
320 			0);
321 	}
322 
323 	for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) {
324 		irq_set_chip(irq, &puv3_normal_chip);
325 		irq_set_handler(irq, handle_level_irq);
326 		irq_modify_status(irq,
327 			IRQ_NOREQUEST | IRQ_NOAUTOEN,
328 			IRQ_NOPROBE);
329 	}
330 
331 	for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) {
332 		irq_set_chip(irq, &puv3_high_gpio_chip);
333 		irq_set_handler(irq, handle_edge_irq);
334 		irq_modify_status(irq,
335 			IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
336 			0);
337 	}
338 
339 	/*
340 	 * Install handler for GPIO 0-27 edge detect interrupts
341 	 */
342 	irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
343 	irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
344 
345 #ifdef CONFIG_PUV3_GPIO
346 	puv3_init_gpio();
347 #endif
348 }
349 
350 /*
351  * do_IRQ handles all hardware IRQ's.  Decoded IRQs should not
352  * come via this function.  Instead, they should provide their
353  * own 'handler'
354  */
asm_do_IRQ(unsigned int irq,struct pt_regs * regs)355 asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
356 {
357 	struct pt_regs *old_regs = set_irq_regs(regs);
358 
359 	irq_enter();
360 
361 	/*
362 	 * Some hardware gives randomly wrong interrupts.  Rather
363 	 * than crashing, do something sensible.
364 	 */
365 	if (unlikely(irq >= nr_irqs)) {
366 		if (printk_ratelimit())
367 			printk(KERN_WARNING "Bad IRQ%u\n", irq);
368 		ack_bad_irq(irq);
369 	} else {
370 		generic_handle_irq(irq);
371 	}
372 
373 	irq_exit();
374 	set_irq_regs(old_regs);
375 }
376 
377