1/* 2 * linux/arch/unicore32/mm/proc-ucv2.S 3 * 4 * Code specific to PKUnity SoC and UniCore ISA 5 * 6 * Copyright (C) 2001-2010 GUAN Xue-tao 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/assembler.h> 15#include <asm/hwcap.h> 16#include <asm/pgtable-hwdef.h> 17#include <asm/pgtable.h> 18 19#include "proc-macros.S" 20 21ENTRY(cpu_proc_fin) 22 stm.w (lr), [sp-] 23 mov ip, #PSR_R_BIT | PSR_I_BIT | PRIV_MODE 24 mov.a asr, ip 25 b.l __cpuc_flush_kern_all 26 ldm.w (pc), [sp]+ 27 28/* 29 * cpu_reset(loc) 30 * 31 * Perform a soft reset of the system. Put the CPU into the 32 * same state as it would be if it had been reset, and branch 33 * to what would be the reset vector. 34 * 35 * - loc - location to jump to for soft reset 36 */ 37 .align 5 38ENTRY(cpu_reset) 39 mov ip, #0 40 movc p0.c5, ip, #28 @ Cache invalidate all 41 nop8 42 43 movc p0.c6, ip, #6 @ TLB invalidate all 44 nop8 45 46 movc ip, p0.c1, #0 @ ctrl register 47 or ip, ip, #0x2000 @ vector base address 48 andn ip, ip, #0x000f @ ............idam 49 movc p0.c1, ip, #0 @ disable caches and mmu 50 nop 51 mov pc, r0 @ jump to loc 52 nop8 53 54/* 55 * cpu_do_idle() 56 * 57 * Idle the processor (eg, wait for interrupt). 58 * 59 * IRQs are already disabled. 60 */ 61ENTRY(cpu_do_idle) 62 mov r0, #0 @ PCI address 63 .rept 8 64 ldw r1, [r0] 65 .endr 66 mov pc, lr 67 68ENTRY(cpu_dcache_clean_area) 69#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE 70 csub.a r1, #MAX_AREA_SIZE 71 bsg 101f 72 mov r9, #PAGE_SZ 73 sub r9, r9, #1 @ PAGE_MASK 741: va2pa r0, r10, r11, r12, r13 @ r10 is PA 75 b 3f 762: cand.a r0, r9 77 beq 1b 783: movc p0.c5, r10, #11 @ clean D entry 79 nop8 80 add r0, r0, #CACHE_LINESIZE 81 add r10, r10, #CACHE_LINESIZE 82 sub.a r1, r1, #CACHE_LINESIZE 83 bua 2b 84 mov pc, lr 85#endif 86101: mov ip, #0 87 movc p0.c5, ip, #10 @ Dcache clean all 88 nop8 89 90 mov pc, lr 91 92/* 93 * cpu_do_switch_mm(pgd_phys) 94 * 95 * Set the translation table base pointer to be pgd_phys 96 * 97 * - pgd_phys - physical address of new pgd 98 * 99 * It is assumed that: 100 * - we are not using split page tables 101 */ 102 .align 5 103ENTRY(cpu_do_switch_mm) 104 movc p0.c2, r0, #0 @ update page table ptr 105 nop8 106 107 movc p0.c6, ip, #6 @ TLB invalidate all 108 nop8 109 110 mov pc, lr 111 112/* 113 * cpu_set_pte(ptep, pte) 114 * 115 * Set a level 2 translation table entry. 116 * 117 * - ptep - pointer to level 2 translation table entry 118 * - pte - PTE value to store 119 */ 120 .align 5 121ENTRY(cpu_set_pte) 122 stw r1, [r0] 123#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE 124 sub r2, r0, #PAGE_OFFSET 125 movc p0.c5, r2, #11 @ Dcache clean line 126 nop8 127#else 128 mov ip, #0 129 movc p0.c5, ip, #10 @ Dcache clean all 130 nop8 131 @dcacheline_flush r0, r2, ip 132#endif 133 mov pc, lr 134 135