1 /*
2 * linux/drivers/media/mmc/goldfish.c
3 *
4 * Copyright 2007, Google Inc.
5 *
6 * based on omap.c driver, which was
7 * Copyright (C) 2004 Nokia Corporation
8 * Written by Tuukka Tikkanen and Juha Yrjl<juha.yrjola@nokia.com>
9 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
10 * Other hacks (DMA, SD, etc) by David Brownell
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/major.h>
20
21 #include <linux/types.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24
25 #include <linux/kernel.h>
26 #include <linux/fs.h>
27 #include <linux/errno.h>
28 #include <linux/hdreg.h>
29 #include <linux/kdev_t.h>
30 #include <linux/blkdev.h>
31 #include <linux/mutex.h>
32 #include <linux/scatterlist.h>
33 #include <linux/mmc/mmc.h>
34 #include <linux/mmc/sdio.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/card.h>
37
38 #include <linux/moduleparam.h>
39 #include <linux/init.h>
40 #include <linux/ioport.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/delay.h>
43 #include <linux/spinlock.h>
44 #include <linux/timer.h>
45 #include <linux/clk.h>
46
47 #include <asm/io.h>
48 #include <asm/irq.h>
49 #include <asm/scatterlist.h>
50 #ifdef CONFIG_ARM
51 #include <asm/mach-types.h>
52 #include <mach/hardware.h>
53 #endif
54
55
56 #include <asm/types.h>
57 #include <asm/io.h>
58 #include <asm/uaccess.h>
59
60 #define DRIVER_NAME "goldfish_mmc"
61
62 #define BUFFER_SIZE 16384
63
64 #define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
65 #define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
66
67
68 enum {
69 /* status register */
70 MMC_INT_STATUS = 0x00,
71 /* set this to enable IRQ */
72 MMC_INT_ENABLE = 0x04,
73 /* set this to specify buffer address */
74 MMC_SET_BUFFER = 0x08,
75
76 /* MMC command number */
77 MMC_CMD = 0x0C,
78
79 /* MMC argument */
80 MMC_ARG = 0x10,
81
82 /* MMC response (or R2 bits 0 - 31) */
83 MMC_RESP_0 = 0x14,
84
85 /* MMC R2 response bits 32 - 63 */
86 MMC_RESP_1 = 0x18,
87
88 /* MMC R2 response bits 64 - 95 */
89 MMC_RESP_2 = 0x1C,
90
91 /* MMC R2 response bits 96 - 127 */
92 MMC_RESP_3 = 0x20,
93
94 MMC_BLOCK_LENGTH = 0x24,
95 MMC_BLOCK_COUNT = 0x28,
96
97 /* MMC state flags */
98 MMC_STATE = 0x2C,
99
100 /* MMC_INT_STATUS bits */
101
102 MMC_STAT_END_OF_CMD = 1U << 0,
103 MMC_STAT_END_OF_DATA = 1U << 1,
104 MMC_STAT_STATE_CHANGE = 1U << 2,
105 MMC_STAT_CMD_TIMEOUT = 1U << 3,
106
107 /* MMC_STATE bits */
108 MMC_STATE_INSERTED = 1U << 0,
109 MMC_STATE_READ_ONLY = 1U << 1,
110 };
111
112 /*
113 * Command types
114 */
115 #define OMAP_MMC_CMDTYPE_BC 0
116 #define OMAP_MMC_CMDTYPE_BCR 1
117 #define OMAP_MMC_CMDTYPE_AC 2
118 #define OMAP_MMC_CMDTYPE_ADTC 3
119
120
121 struct goldfish_mmc_host {
122 struct mmc_request * mrq;
123 struct mmc_command * cmd;
124 struct mmc_data * data;
125 struct mmc_host * mmc;
126 struct device * dev;
127 unsigned char id; /* 16xx chips have 2 MMC blocks */
128 void __iomem *virt_base;
129 unsigned int phys_base;
130 int irq;
131 unsigned char bus_mode;
132 unsigned char hw_bus_mode;
133
134 unsigned int sg_len;
135 unsigned dma_done:1;
136 unsigned dma_in_use:1;
137
138 void __iomem *reg_base;
139 };
140
141 static inline int
goldfish_mmc_cover_is_open(struct goldfish_mmc_host * host)142 goldfish_mmc_cover_is_open(struct goldfish_mmc_host *host)
143 {
144 return 0;
145 }
146
147 static ssize_t
goldfish_mmc_show_cover_switch(struct device * dev,struct device_attribute * attr,char * buf)148 goldfish_mmc_show_cover_switch(struct device *dev,
149 struct device_attribute *attr, char *buf)
150 {
151 struct goldfish_mmc_host *host = dev_get_drvdata(dev);
152
153 return sprintf(buf, "%s\n", goldfish_mmc_cover_is_open(host) ? "open" :
154 "closed");
155 }
156
157 static DEVICE_ATTR(cover_switch, S_IRUGO, goldfish_mmc_show_cover_switch, NULL);
158
159 static void
goldfish_mmc_start_command(struct goldfish_mmc_host * host,struct mmc_command * cmd)160 goldfish_mmc_start_command(struct goldfish_mmc_host *host, struct mmc_command *cmd)
161 {
162 u32 cmdreg;
163 u32 resptype;
164 u32 cmdtype;
165
166 host->cmd = cmd;
167
168 resptype = 0;
169 cmdtype = 0;
170
171 /* Our hardware needs to know exact type */
172 switch (mmc_resp_type(cmd)) {
173 case MMC_RSP_NONE:
174 break;
175 case MMC_RSP_R1:
176 case MMC_RSP_R1B:
177 /* resp 1, 1b, 6, 7 */
178 resptype = 1;
179 break;
180 case MMC_RSP_R2:
181 resptype = 2;
182 break;
183 case MMC_RSP_R3:
184 resptype = 3;
185 break;
186 default:
187 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
188 break;
189 }
190
191 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
192 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
193 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
194 cmdtype = OMAP_MMC_CMDTYPE_BC;
195 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
196 cmdtype = OMAP_MMC_CMDTYPE_BCR;
197 } else {
198 cmdtype = OMAP_MMC_CMDTYPE_AC;
199 }
200
201 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
202
203 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
204 cmdreg |= 1 << 6;
205
206 if (cmd->flags & MMC_RSP_BUSY)
207 cmdreg |= 1 << 11;
208
209 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
210 cmdreg |= 1 << 15;
211
212 GOLDFISH_MMC_WRITE(host, MMC_ARG, cmd->arg);
213 GOLDFISH_MMC_WRITE(host, MMC_CMD, cmdreg);
214 }
215
216 static void
goldfish_mmc_xfer_done(struct goldfish_mmc_host * host,struct mmc_data * data)217 goldfish_mmc_xfer_done(struct goldfish_mmc_host *host, struct mmc_data *data)
218 {
219 if (host->dma_in_use) {
220 enum dma_data_direction dma_data_dir;
221
222 if (data->flags & MMC_DATA_WRITE)
223 dma_data_dir = DMA_TO_DEVICE;
224 else
225 dma_data_dir = DMA_FROM_DEVICE;
226
227 if (dma_data_dir == DMA_FROM_DEVICE) {
228 // we don't really have DMA, so we need to copy from our platform driver buffer
229 uint8_t* dest = (uint8_t *)sg_virt(data->sg);
230 memcpy(dest, host->virt_base, data->sg->length);
231 }
232
233 host->data->bytes_xfered += data->sg->length;
234
235 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len, dma_data_dir);
236 }
237
238 host->data = NULL;
239 host->sg_len = 0;
240
241 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
242 * dozens of requests until the card finishes writing data.
243 * It'd be cheaper to just wait till an EOFB interrupt arrives...
244 */
245
246 if (!data->stop) {
247 host->mrq = NULL;
248 mmc_request_done(host->mmc, data->mrq);
249 return;
250 }
251
252 goldfish_mmc_start_command(host, data->stop);
253 }
254
255 static void
goldfish_mmc_end_of_data(struct goldfish_mmc_host * host,struct mmc_data * data)256 goldfish_mmc_end_of_data(struct goldfish_mmc_host *host, struct mmc_data *data)
257 {
258 if (!host->dma_in_use) {
259 goldfish_mmc_xfer_done(host, data);
260 return;
261 }
262 if (host->dma_done)
263 goldfish_mmc_xfer_done(host, data);
264 }
265
266 static void
goldfish_mmc_cmd_done(struct goldfish_mmc_host * host,struct mmc_command * cmd)267 goldfish_mmc_cmd_done(struct goldfish_mmc_host *host, struct mmc_command *cmd)
268 {
269 host->cmd = NULL;
270 if (cmd->flags & MMC_RSP_PRESENT) {
271 if (cmd->flags & MMC_RSP_136) {
272 /* response type 2 */
273 cmd->resp[3] =
274 GOLDFISH_MMC_READ(host, MMC_RESP_0);
275 cmd->resp[2] =
276 GOLDFISH_MMC_READ(host, MMC_RESP_1);
277 cmd->resp[1] =
278 GOLDFISH_MMC_READ(host, MMC_RESP_2);
279 cmd->resp[0] =
280 GOLDFISH_MMC_READ(host, MMC_RESP_3);
281 } else {
282 /* response types 1, 1b, 3, 4, 5, 6 */
283 cmd->resp[0] =
284 GOLDFISH_MMC_READ(host, MMC_RESP_0);
285 }
286 }
287
288 if (host->data == NULL || cmd->error) {
289 host->mrq = NULL;
290 mmc_request_done(host->mmc, cmd->mrq);
291 }
292 }
293
goldfish_mmc_irq(int irq,void * dev_id)294 static irqreturn_t goldfish_mmc_irq(int irq, void *dev_id)
295 {
296 struct goldfish_mmc_host * host = (struct goldfish_mmc_host *)dev_id;
297 u16 status;
298 int end_command = 0;
299 int end_transfer = 0;
300 int transfer_error = 0;
301 int state_changed = 0;
302 int cmd_timeout = 0;
303
304 while ((status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS)) != 0) {
305 GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
306
307 if (status & MMC_STAT_END_OF_CMD) {
308 end_command = 1;
309 }
310
311 if (status & MMC_STAT_END_OF_DATA) {
312 end_transfer = 1;
313 }
314 if (status & MMC_STAT_STATE_CHANGE) {
315 state_changed = 1;
316 }
317
318 if (status & MMC_STAT_CMD_TIMEOUT) {
319 end_command = 0;
320 cmd_timeout = 1;
321 }
322 }
323
324 if (cmd_timeout) {
325 struct mmc_request *mrq = host->mrq;
326 mrq->cmd->error = -ETIMEDOUT;
327 host->mrq = NULL;
328 mmc_request_done(host->mmc, mrq);
329 }
330
331 if (end_command) {
332 goldfish_mmc_cmd_done(host, host->cmd);
333 }
334 if (transfer_error)
335 goldfish_mmc_xfer_done(host, host->data);
336 else if (end_transfer) {
337 host->dma_done = 1;
338 goldfish_mmc_end_of_data(host, host->data);
339 } else if (host->data != NULL && host->mrq->cmd->opcode == 13) {
340 /*
341 * WORKAROUND -- after porting this driver from 2.6 to 3.4,
342 * this case pops up during device initialization.
343 * This happens as the host stack is sending ACMD13 which
344 * involves data read while goldfish emulator implementation
345 * only supports CMD13 which does not have data phase.
346 * The workaround works by passing garbage result to the stack.
347 * TODO -- To implement proper response
348 */
349 host->dma_done = 1;
350 goldfish_mmc_end_of_data(host, host->data);
351 }
352
353 if (state_changed) {
354 u32 state = GOLDFISH_MMC_READ(host, MMC_STATE);
355 pr_info("%s: Card detect now %d\n", __func__,
356 (state & MMC_STATE_INSERTED));
357 mmc_detect_change(host->mmc, 0);
358 }
359
360 if (!end_command && !end_transfer &&
361 !transfer_error && !state_changed && !cmd_timeout) {
362 status = GOLDFISH_MMC_READ(host, MMC_INT_STATUS);
363 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
364 if (status != 0) {
365 GOLDFISH_MMC_WRITE(host, MMC_INT_STATUS, status);
366 GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE, 0);
367 }
368 }
369
370 return IRQ_HANDLED;
371 }
372
373 static void
goldfish_mmc_prepare_data(struct goldfish_mmc_host * host,struct mmc_request * req)374 goldfish_mmc_prepare_data(struct goldfish_mmc_host *host, struct mmc_request *req)
375 {
376 struct mmc_data *data = req->data;
377 int block_size;
378 unsigned sg_len;
379 enum dma_data_direction dma_data_dir;
380
381 host->data = data;
382 if (data == NULL) {
383 GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, 0);
384 GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, 0);
385 host->dma_in_use = 0;
386 return;
387 }
388
389 block_size = data->blksz;
390
391 GOLDFISH_MMC_WRITE(host, MMC_BLOCK_COUNT, data->blocks - 1);
392 GOLDFISH_MMC_WRITE(host, MMC_BLOCK_LENGTH, block_size - 1);
393
394 /* cope with calling layer confusion; it issues "single
395 * block" writes using multi-block scatterlists.
396 */
397 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
398
399 if (data->flags & MMC_DATA_WRITE)
400 dma_data_dir = DMA_TO_DEVICE;
401 else
402 dma_data_dir = DMA_FROM_DEVICE;
403 #if defined(CONFIG_ARM) || defined(CONFIG_MIPS)
404 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
405 sg_len, dma_data_dir);
406 #elif defined(CONFIG_X86)
407 /*
408 * Use NULL for dev for ISA-like devices
409 */
410 host->sg_len = dma_map_sg(NULL, data->sg,
411 sg_len, dma_data_dir);
412 #else
413 #error NOT SUPPORTED
414 #endif
415 host->dma_done = 0;
416 host->dma_in_use = 1;
417
418 if (dma_data_dir == DMA_TO_DEVICE) {
419 // we don't really have DMA, so we need to copy to our platform driver buffer
420 const uint8_t* src = (uint8_t *)sg_virt(data->sg);
421 memcpy(host->virt_base, src, data->sg->length);
422 }
423 }
424
goldfish_mmc_request(struct mmc_host * mmc,struct mmc_request * req)425 static void goldfish_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
426 {
427 struct goldfish_mmc_host *host = mmc_priv(mmc);
428
429 WARN_ON(host->mrq != NULL);
430
431 host->mrq = req;
432 goldfish_mmc_prepare_data(host, req);
433 goldfish_mmc_start_command(host, req->cmd);
434
435 /* this is to avoid accidentally being detected as an SDIO card in mmc_attach_sdio() */
436 if (req->cmd->opcode == SD_IO_SEND_OP_COND &&
437 req->cmd->flags == (MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR)) {
438 req->cmd->error = -EINVAL;
439 }
440 }
441
goldfish_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)442 static void goldfish_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
443 {
444 struct goldfish_mmc_host *host = mmc_priv(mmc);
445
446 host->bus_mode = ios->bus_mode;
447 host->hw_bus_mode = host->bus_mode;
448 }
449
goldfish_mmc_get_ro(struct mmc_host * mmc)450 static int goldfish_mmc_get_ro(struct mmc_host *mmc)
451 {
452 uint32_t state;
453 struct goldfish_mmc_host *host = mmc_priv(mmc);
454
455 state = GOLDFISH_MMC_READ(host, MMC_STATE);
456 return ((state & MMC_STATE_READ_ONLY) != 0);
457 }
458
459 static const struct mmc_host_ops goldfish_mmc_ops = {
460 .request = goldfish_mmc_request,
461 .set_ios = goldfish_mmc_set_ios,
462 .get_ro = goldfish_mmc_get_ro,
463 };
464
goldfish_mmc_probe(struct platform_device * pdev)465 static int goldfish_mmc_probe(struct platform_device *pdev)
466 {
467 struct mmc_host *mmc;
468 struct goldfish_mmc_host *host = NULL;
469 struct resource *res;
470 int ret = 0;
471 int irq;
472 dma_addr_t buf_addr;
473
474 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
475 irq = platform_get_irq(pdev, 0);
476 if (res == NULL || irq < 0)
477 return -ENXIO;
478
479 mmc = mmc_alloc_host(sizeof(struct goldfish_mmc_host), &pdev->dev);
480 if (mmc == NULL) {
481 ret = -ENOMEM;
482 goto err_alloc_host_failed;
483 }
484
485 host = mmc_priv(mmc);
486 host->mmc = mmc;
487 #if defined(CONFIG_ARM)
488 host->reg_base = (void __iomem *)IO_ADDRESS(res->start - IO_START);
489 host->virt_base = dma_alloc_writecombine(&pdev->dev, BUFFER_SIZE,
490 &buf_addr, GFP_KERNEL);
491 #elif defined(CONFIG_X86) || defined(CONFIG_MIPS)
492 /*
493 * Use NULL for dev for ISA-like devices
494 */
495 host->reg_base = ioremap(res->start, res->end - res->start + 1);
496 host->virt_base = dma_alloc_coherent(NULL, BUFFER_SIZE, &buf_addr, GFP_KERNEL);
497 #else
498 #error NOT SUPPORTED
499 #endif
500 if(host->virt_base == 0) {
501 ret = -EBUSY;
502 goto dma_alloc_failed;
503 }
504 host->phys_base = buf_addr;
505
506 host->id = pdev->id;
507 host->irq = irq;
508
509 mmc->ops = &goldfish_mmc_ops;
510 mmc->f_min = 400000;
511 mmc->f_max = 24000000;
512 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
513 mmc->caps = MMC_CAP_4_BIT_DATA;
514
515 /* Use scatterlist DMA to reduce per-transfer costs.
516 * NOTE max_seg_size assumption that small blocks aren't
517 * normally used (except e.g. for reading SD registers).
518 */
519 mmc->max_segs = 32;
520 mmc->max_blk_size = 2048; /* MMC_BLOCK_LENGTH is 11 bits (+1) */
521 mmc->max_blk_count = 2048; /* MMC_BLOCK_COUNT is 11 bits (+1) */
522 mmc->max_req_size = BUFFER_SIZE;
523 mmc->max_seg_size = mmc->max_req_size;
524
525 ret = request_irq(host->irq, goldfish_mmc_irq, 0, DRIVER_NAME, host);
526 if (ret)
527 goto err_request_irq_failed;
528
529 host->dev = &pdev->dev;
530 platform_set_drvdata(pdev, host);
531
532 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
533 if (ret)
534 dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
535
536 GOLDFISH_MMC_WRITE(host, MMC_SET_BUFFER, host->phys_base);
537 GOLDFISH_MMC_WRITE(host, MMC_INT_ENABLE,
538 MMC_STAT_END_OF_CMD | MMC_STAT_END_OF_DATA | MMC_STAT_STATE_CHANGE |
539 MMC_STAT_CMD_TIMEOUT);
540
541 mmc_add_host(mmc);
542
543 return 0;
544
545 err_request_irq_failed:
546 #if defined(CONFIG_ARM)
547 dma_free_writecombine(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
548 #elif defined(CONFIG_X86) || defined(CONFIG_MIPS)
549 dma_free_coherent(NULL, BUFFER_SIZE, host->virt_base, host->phys_base);
550 #else
551 #error NOT SUPPORTED
552 #endif
553 dma_alloc_failed:
554 mmc_free_host(host->mmc);
555 err_alloc_host_failed:
556 return ret;
557 }
558
goldfish_mmc_remove(struct platform_device * pdev)559 static int goldfish_mmc_remove(struct platform_device *pdev)
560 {
561 struct goldfish_mmc_host *host = platform_get_drvdata(pdev);
562
563 platform_set_drvdata(pdev, NULL);
564
565 BUG_ON(host == NULL);
566
567 mmc_remove_host(host->mmc);
568 free_irq(host->irq, host);
569 #if defined(CONFIG_ARM)
570 dma_free_writecombine(&pdev->dev, BUFFER_SIZE, host->virt_base, host->phys_base);
571 #elif defined(CONFIG_X86) || defined(CONFIG_MIPS)
572 dma_free_coherent(NULL, BUFFER_SIZE, host->virt_base, host->phys_base);
573 #else
574 #error NOT SUPPORTED
575 #endif
576 mmc_free_host(host->mmc);
577
578 return 0;
579 }
580
581 static struct platform_driver goldfish_mmc_driver = {
582 .probe = goldfish_mmc_probe,
583 .remove = goldfish_mmc_remove,
584 .driver = {
585 .name = DRIVER_NAME,
586 },
587 };
588
goldfish_mmc_init(void)589 static int __init goldfish_mmc_init(void)
590 {
591 return platform_driver_register(&goldfish_mmc_driver);
592 }
593
goldfish_mmc_exit(void)594 static void __exit goldfish_mmc_exit(void)
595 {
596 platform_driver_unregister(&goldfish_mmc_driver);
597 }
598
599 module_init(goldfish_mmc_init);
600 module_exit(goldfish_mmc_exit);
601
602