1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #ifdef IXGBE_FCOE
59 char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
61 #else
62 static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #endif
65 #define MAJ 3
66 #define MIN 8
67 #define BUILD 21
68 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
69 __stringify(BUILD) "-k"
70 const char ixgbe_driver_version[] = DRV_VERSION;
71 static const char ixgbe_copyright[] =
72 "Copyright (c) 1999-2012 Intel Corporation.";
73
74 static const struct ixgbe_info *ixgbe_info_tbl[] = {
75 [board_82598] = &ixgbe_82598_info,
76 [board_82599] = &ixgbe_82599_info,
77 [board_X540] = &ixgbe_X540_info,
78 };
79
80 /* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
118 /* required last entry */
119 {0, }
120 };
121 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
123 #ifdef CONFIG_IXGBE_DCA
124 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
125 void *p);
126 static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130 };
131 #endif
132
133 #ifdef CONFIG_PCI_IOV
134 static unsigned int max_vfs;
135 module_param(max_vfs, uint, 0);
136 MODULE_PARM_DESC(max_vfs,
137 "Maximum number of virtual functions to allocate per physical function");
138 #endif /* CONFIG_PCI_IOV */
139
140 static unsigned int allow_unsupported_sfp;
141 module_param(allow_unsupported_sfp, uint, 0);
142 MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
145 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146 static int debug = -1;
147 module_param(debug, int, 0);
148 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
150 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152 MODULE_LICENSE("GPL");
153 MODULE_VERSION(DRV_VERSION);
154
ixgbe_service_event_schedule(struct ixgbe_adapter * adapter)155 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
156 {
157 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
158 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
159 schedule_work(&adapter->service_task);
160 }
161
ixgbe_service_event_complete(struct ixgbe_adapter * adapter)162 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
163 {
164 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
165
166 /* flush memory to make sure state is correct before next watchdog */
167 smp_mb__before_clear_bit();
168 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
169 }
170
171 struct ixgbe_reg_info {
172 u32 ofs;
173 char *name;
174 };
175
176 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
177
178 /* General Registers */
179 {IXGBE_CTRL, "CTRL"},
180 {IXGBE_STATUS, "STATUS"},
181 {IXGBE_CTRL_EXT, "CTRL_EXT"},
182
183 /* Interrupt Registers */
184 {IXGBE_EICR, "EICR"},
185
186 /* RX Registers */
187 {IXGBE_SRRCTL(0), "SRRCTL"},
188 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
189 {IXGBE_RDLEN(0), "RDLEN"},
190 {IXGBE_RDH(0), "RDH"},
191 {IXGBE_RDT(0), "RDT"},
192 {IXGBE_RXDCTL(0), "RXDCTL"},
193 {IXGBE_RDBAL(0), "RDBAL"},
194 {IXGBE_RDBAH(0), "RDBAH"},
195
196 /* TX Registers */
197 {IXGBE_TDBAL(0), "TDBAL"},
198 {IXGBE_TDBAH(0), "TDBAH"},
199 {IXGBE_TDLEN(0), "TDLEN"},
200 {IXGBE_TDH(0), "TDH"},
201 {IXGBE_TDT(0), "TDT"},
202 {IXGBE_TXDCTL(0), "TXDCTL"},
203
204 /* List Terminator */
205 {}
206 };
207
208
209 /*
210 * ixgbe_regdump - register printout routine
211 */
ixgbe_regdump(struct ixgbe_hw * hw,struct ixgbe_reg_info * reginfo)212 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
213 {
214 int i = 0, j = 0;
215 char rname[16];
216 u32 regs[64];
217
218 switch (reginfo->ofs) {
219 case IXGBE_SRRCTL(0):
220 for (i = 0; i < 64; i++)
221 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
222 break;
223 case IXGBE_DCA_RXCTRL(0):
224 for (i = 0; i < 64; i++)
225 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
226 break;
227 case IXGBE_RDLEN(0):
228 for (i = 0; i < 64; i++)
229 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
230 break;
231 case IXGBE_RDH(0):
232 for (i = 0; i < 64; i++)
233 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
234 break;
235 case IXGBE_RDT(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
238 break;
239 case IXGBE_RXDCTL(0):
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
242 break;
243 case IXGBE_RDBAL(0):
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
246 break;
247 case IXGBE_RDBAH(0):
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
250 break;
251 case IXGBE_TDBAL(0):
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
254 break;
255 case IXGBE_TDBAH(0):
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
258 break;
259 case IXGBE_TDLEN(0):
260 for (i = 0; i < 64; i++)
261 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
262 break;
263 case IXGBE_TDH(0):
264 for (i = 0; i < 64; i++)
265 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
266 break;
267 case IXGBE_TDT(0):
268 for (i = 0; i < 64; i++)
269 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
270 break;
271 case IXGBE_TXDCTL(0):
272 for (i = 0; i < 64; i++)
273 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
274 break;
275 default:
276 pr_info("%-15s %08x\n", reginfo->name,
277 IXGBE_READ_REG(hw, reginfo->ofs));
278 return;
279 }
280
281 for (i = 0; i < 8; i++) {
282 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
283 pr_err("%-15s", rname);
284 for (j = 0; j < 8; j++)
285 pr_cont(" %08x", regs[i*8+j]);
286 pr_cont("\n");
287 }
288
289 }
290
291 /*
292 * ixgbe_dump - Print registers, tx-rings and rx-rings
293 */
ixgbe_dump(struct ixgbe_adapter * adapter)294 static void ixgbe_dump(struct ixgbe_adapter *adapter)
295 {
296 struct net_device *netdev = adapter->netdev;
297 struct ixgbe_hw *hw = &adapter->hw;
298 struct ixgbe_reg_info *reginfo;
299 int n = 0;
300 struct ixgbe_ring *tx_ring;
301 struct ixgbe_tx_buffer *tx_buffer;
302 union ixgbe_adv_tx_desc *tx_desc;
303 struct my_u0 { u64 a; u64 b; } *u0;
304 struct ixgbe_ring *rx_ring;
305 union ixgbe_adv_rx_desc *rx_desc;
306 struct ixgbe_rx_buffer *rx_buffer_info;
307 u32 staterr;
308 int i = 0;
309
310 if (!netif_msg_hw(adapter))
311 return;
312
313 /* Print netdevice Info */
314 if (netdev) {
315 dev_info(&adapter->pdev->dev, "Net device Info\n");
316 pr_info("Device Name state "
317 "trans_start last_rx\n");
318 pr_info("%-15s %016lX %016lX %016lX\n",
319 netdev->name,
320 netdev->state,
321 netdev->trans_start,
322 netdev->last_rx);
323 }
324
325 /* Print Registers */
326 dev_info(&adapter->pdev->dev, "Register Dump\n");
327 pr_info(" Register Name Value\n");
328 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
329 reginfo->name; reginfo++) {
330 ixgbe_regdump(hw, reginfo);
331 }
332
333 /* Print TX Ring Summary */
334 if (!netdev || !netif_running(netdev))
335 goto exit;
336
337 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
338 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
339 for (n = 0; n < adapter->num_tx_queues; n++) {
340 tx_ring = adapter->tx_ring[n];
341 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
342 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
343 n, tx_ring->next_to_use, tx_ring->next_to_clean,
344 (u64)dma_unmap_addr(tx_buffer, dma),
345 dma_unmap_len(tx_buffer, len),
346 tx_buffer->next_to_watch,
347 (u64)tx_buffer->time_stamp);
348 }
349
350 /* Print TX Rings */
351 if (!netif_msg_tx_done(adapter))
352 goto rx_ring_summary;
353
354 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
355
356 /* Transmit Descriptor Formats
357 *
358 * Advanced Transmit Descriptor
359 * +--------------------------------------------------------------+
360 * 0 | Buffer Address [63:0] |
361 * +--------------------------------------------------------------+
362 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
363 * +--------------------------------------------------------------+
364 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
365 */
366
367 for (n = 0; n < adapter->num_tx_queues; n++) {
368 tx_ring = adapter->tx_ring[n];
369 pr_info("------------------------------------\n");
370 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
371 pr_info("------------------------------------\n");
372 pr_info("T [desc] [address 63:0 ] "
373 "[PlPOIdStDDt Ln] [bi->dma ] "
374 "leng ntw timestamp bi->skb\n");
375
376 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
377 tx_desc = IXGBE_TX_DESC(tx_ring, i);
378 tx_buffer = &tx_ring->tx_buffer_info[i];
379 u0 = (struct my_u0 *)tx_desc;
380 pr_info("T [0x%03X] %016llX %016llX %016llX"
381 " %04X %p %016llX %p", i,
382 le64_to_cpu(u0->a),
383 le64_to_cpu(u0->b),
384 (u64)dma_unmap_addr(tx_buffer, dma),
385 dma_unmap_len(tx_buffer, len),
386 tx_buffer->next_to_watch,
387 (u64)tx_buffer->time_stamp,
388 tx_buffer->skb);
389 if (i == tx_ring->next_to_use &&
390 i == tx_ring->next_to_clean)
391 pr_cont(" NTC/U\n");
392 else if (i == tx_ring->next_to_use)
393 pr_cont(" NTU\n");
394 else if (i == tx_ring->next_to_clean)
395 pr_cont(" NTC\n");
396 else
397 pr_cont("\n");
398
399 if (netif_msg_pktdata(adapter) &&
400 dma_unmap_len(tx_buffer, len) != 0)
401 print_hex_dump(KERN_INFO, "",
402 DUMP_PREFIX_ADDRESS, 16, 1,
403 phys_to_virt(dma_unmap_addr(tx_buffer,
404 dma)),
405 dma_unmap_len(tx_buffer, len),
406 true);
407 }
408 }
409
410 /* Print RX Rings Summary */
411 rx_ring_summary:
412 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
413 pr_info("Queue [NTU] [NTC]\n");
414 for (n = 0; n < adapter->num_rx_queues; n++) {
415 rx_ring = adapter->rx_ring[n];
416 pr_info("%5d %5X %5X\n",
417 n, rx_ring->next_to_use, rx_ring->next_to_clean);
418 }
419
420 /* Print RX Rings */
421 if (!netif_msg_rx_status(adapter))
422 goto exit;
423
424 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
425
426 /* Advanced Receive Descriptor (Read) Format
427 * 63 1 0
428 * +-----------------------------------------------------+
429 * 0 | Packet Buffer Address [63:1] |A0/NSE|
430 * +----------------------------------------------+------+
431 * 8 | Header Buffer Address [63:1] | DD |
432 * +-----------------------------------------------------+
433 *
434 *
435 * Advanced Receive Descriptor (Write-Back) Format
436 *
437 * 63 48 47 32 31 30 21 20 16 15 4 3 0
438 * +------------------------------------------------------+
439 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
440 * | Checksum Ident | | | | Type | Type |
441 * +------------------------------------------------------+
442 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
443 * +------------------------------------------------------+
444 * 63 48 47 32 31 20 19 0
445 */
446 for (n = 0; n < adapter->num_rx_queues; n++) {
447 rx_ring = adapter->rx_ring[n];
448 pr_info("------------------------------------\n");
449 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
450 pr_info("------------------------------------\n");
451 pr_info("R [desc] [ PktBuf A0] "
452 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
453 "<-- Adv Rx Read format\n");
454 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
455 "[vl er S cks ln] ---------------- [bi->skb] "
456 "<-- Adv Rx Write-Back format\n");
457
458 for (i = 0; i < rx_ring->count; i++) {
459 rx_buffer_info = &rx_ring->rx_buffer_info[i];
460 rx_desc = IXGBE_RX_DESC(rx_ring, i);
461 u0 = (struct my_u0 *)rx_desc;
462 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
463 if (staterr & IXGBE_RXD_STAT_DD) {
464 /* Descriptor Done */
465 pr_info("RWB[0x%03X] %016llX "
466 "%016llX ---------------- %p", i,
467 le64_to_cpu(u0->a),
468 le64_to_cpu(u0->b),
469 rx_buffer_info->skb);
470 } else {
471 pr_info("R [0x%03X] %016llX "
472 "%016llX %016llX %p", i,
473 le64_to_cpu(u0->a),
474 le64_to_cpu(u0->b),
475 (u64)rx_buffer_info->dma,
476 rx_buffer_info->skb);
477
478 if (netif_msg_pktdata(adapter)) {
479 print_hex_dump(KERN_INFO, "",
480 DUMP_PREFIX_ADDRESS, 16, 1,
481 phys_to_virt(rx_buffer_info->dma),
482 ixgbe_rx_bufsz(rx_ring), true);
483 }
484 }
485
486 if (i == rx_ring->next_to_use)
487 pr_cont(" NTU\n");
488 else if (i == rx_ring->next_to_clean)
489 pr_cont(" NTC\n");
490 else
491 pr_cont("\n");
492
493 }
494 }
495
496 exit:
497 return;
498 }
499
ixgbe_release_hw_control(struct ixgbe_adapter * adapter)500 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501 {
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
508 }
509
ixgbe_get_hw_control(struct ixgbe_adapter * adapter)510 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511 {
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
518 }
519
520 /*
521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
ixgbe_set_ivar(struct ixgbe_adapter * adapter,s8 direction,u8 queue,u8 msix_vector)528 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
529 u8 queue, u8 msix_vector)
530 {
531 u32 ivar, index;
532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
545 case ixgbe_mac_X540:
546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
568 }
569
ixgbe_irq_rearm_queues(struct ixgbe_adapter * adapter,u64 qmask)570 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
571 u64 qmask)
572 {
573 u32 mask;
574
575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
579 break;
580 case ixgbe_mac_82599EB:
581 case ixgbe_mac_X540:
582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
586 break;
587 default:
588 break;
589 }
590 }
591
ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring * ring,struct ixgbe_tx_buffer * tx_buffer)592 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
594 {
595 if (tx_buffer->skb) {
596 dev_kfree_skb_any(tx_buffer->skb);
597 if (dma_unmap_len(tx_buffer, len))
598 dma_unmap_single(ring->dev,
599 dma_unmap_addr(tx_buffer, dma),
600 dma_unmap_len(tx_buffer, len),
601 DMA_TO_DEVICE);
602 } else if (dma_unmap_len(tx_buffer, len)) {
603 dma_unmap_page(ring->dev,
604 dma_unmap_addr(tx_buffer, dma),
605 dma_unmap_len(tx_buffer, len),
606 DMA_TO_DEVICE);
607 }
608 tx_buffer->next_to_watch = NULL;
609 tx_buffer->skb = NULL;
610 dma_unmap_len_set(tx_buffer, len, 0);
611 /* tx_buffer must be completely set up in the transmit path */
612 }
613
ixgbe_update_xoff_received(struct ixgbe_adapter * adapter)614 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
615 {
616 struct ixgbe_hw *hw = &adapter->hw;
617 struct ixgbe_hw_stats *hwstats = &adapter->stats;
618 u32 data = 0;
619 u32 xoff[8] = {0};
620 int i;
621
622 if ((hw->fc.current_mode == ixgbe_fc_full) ||
623 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
624 switch (hw->mac.type) {
625 case ixgbe_mac_82598EB:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
627 break;
628 default:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
630 }
631 hwstats->lxoffrxc += data;
632
633 /* refill credits (no tx hang) if we received xoff */
634 if (!data)
635 return;
636
637 for (i = 0; i < adapter->num_tx_queues; i++)
638 clear_bit(__IXGBE_HANG_CHECK_ARMED,
639 &adapter->tx_ring[i]->state);
640 return;
641 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
642 return;
643
644 /* update stats for each tc, only valid with PFC enabled */
645 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
646 switch (hw->mac.type) {
647 case ixgbe_mac_82598EB:
648 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
649 break;
650 default:
651 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
652 }
653 hwstats->pxoffrxc[i] += xoff[i];
654 }
655
656 /* disarm tx queues that have received xoff frames */
657 for (i = 0; i < adapter->num_tx_queues; i++) {
658 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
659 u8 tc = tx_ring->dcb_tc;
660
661 if (xoff[tc])
662 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
663 }
664 }
665
ixgbe_get_tx_completed(struct ixgbe_ring * ring)666 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
667 {
668 return ring->stats.packets;
669 }
670
ixgbe_get_tx_pending(struct ixgbe_ring * ring)671 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
672 {
673 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
674 struct ixgbe_hw *hw = &adapter->hw;
675
676 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
677 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
678
679 if (head != tail)
680 return (head < tail) ?
681 tail - head : (tail + ring->count - head);
682
683 return 0;
684 }
685
ixgbe_check_tx_hang(struct ixgbe_ring * tx_ring)686 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
687 {
688 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
689 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
690 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
691 bool ret = false;
692
693 clear_check_for_tx_hang(tx_ring);
694
695 /*
696 * Check for a hung queue, but be thorough. This verifies
697 * that a transmit has been completed since the previous
698 * check AND there is at least one packet pending. The
699 * ARMED bit is set to indicate a potential hang. The
700 * bit is cleared if a pause frame is received to remove
701 * false hang detection due to PFC or 802.3x frames. By
702 * requiring this to fail twice we avoid races with
703 * pfc clearing the ARMED bit and conditions where we
704 * run the check_tx_hang logic with a transmit completion
705 * pending but without time to complete it yet.
706 */
707 if ((tx_done_old == tx_done) && tx_pending) {
708 /* make sure it is true for two checks in a row */
709 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
710 &tx_ring->state);
711 } else {
712 /* update completed stats and continue */
713 tx_ring->tx_stats.tx_done_old = tx_done;
714 /* reset the countdown */
715 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
716 }
717
718 return ret;
719 }
720
721 /**
722 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
723 * @adapter: driver private struct
724 **/
ixgbe_tx_timeout_reset(struct ixgbe_adapter * adapter)725 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
726 {
727
728 /* Do the reset outside of interrupt context */
729 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
730 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
731 ixgbe_service_event_schedule(adapter);
732 }
733 }
734
735 /**
736 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
737 * @q_vector: structure containing interrupt and ring information
738 * @tx_ring: tx ring to clean
739 **/
ixgbe_clean_tx_irq(struct ixgbe_q_vector * q_vector,struct ixgbe_ring * tx_ring)740 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
741 struct ixgbe_ring *tx_ring)
742 {
743 struct ixgbe_adapter *adapter = q_vector->adapter;
744 struct ixgbe_tx_buffer *tx_buffer;
745 union ixgbe_adv_tx_desc *tx_desc;
746 unsigned int total_bytes = 0, total_packets = 0;
747 unsigned int budget = q_vector->tx.work_limit;
748 unsigned int i = tx_ring->next_to_clean;
749
750 if (test_bit(__IXGBE_DOWN, &adapter->state))
751 return true;
752
753 tx_buffer = &tx_ring->tx_buffer_info[i];
754 tx_desc = IXGBE_TX_DESC(tx_ring, i);
755 i -= tx_ring->count;
756
757 do {
758 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
759
760 /* if next_to_watch is not set then there is no work pending */
761 if (!eop_desc)
762 break;
763
764 /* prevent any other reads prior to eop_desc */
765 rmb();
766
767 /* if DD is not set pending work has not been completed */
768 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
769 break;
770
771 /* clear next_to_watch to prevent false hangs */
772 tx_buffer->next_to_watch = NULL;
773
774 /* update the statistics for this packet */
775 total_bytes += tx_buffer->bytecount;
776 total_packets += tx_buffer->gso_segs;
777
778 /* free the skb */
779 dev_kfree_skb_any(tx_buffer->skb);
780
781 /* unmap skb header data */
782 dma_unmap_single(tx_ring->dev,
783 dma_unmap_addr(tx_buffer, dma),
784 dma_unmap_len(tx_buffer, len),
785 DMA_TO_DEVICE);
786
787 /* clear tx_buffer data */
788 tx_buffer->skb = NULL;
789 dma_unmap_len_set(tx_buffer, len, 0);
790
791 /* unmap remaining buffers */
792 while (tx_desc != eop_desc) {
793 tx_buffer++;
794 tx_desc++;
795 i++;
796 if (unlikely(!i)) {
797 i -= tx_ring->count;
798 tx_buffer = tx_ring->tx_buffer_info;
799 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
800 }
801
802 /* unmap any remaining paged data */
803 if (dma_unmap_len(tx_buffer, len)) {
804 dma_unmap_page(tx_ring->dev,
805 dma_unmap_addr(tx_buffer, dma),
806 dma_unmap_len(tx_buffer, len),
807 DMA_TO_DEVICE);
808 dma_unmap_len_set(tx_buffer, len, 0);
809 }
810 }
811
812 /* move us one more past the eop_desc for start of next pkt */
813 tx_buffer++;
814 tx_desc++;
815 i++;
816 if (unlikely(!i)) {
817 i -= tx_ring->count;
818 tx_buffer = tx_ring->tx_buffer_info;
819 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
820 }
821
822 /* issue prefetch for next Tx descriptor */
823 prefetch(tx_desc);
824
825 /* update budget accounting */
826 budget--;
827 } while (likely(budget));
828
829 i += tx_ring->count;
830 tx_ring->next_to_clean = i;
831 u64_stats_update_begin(&tx_ring->syncp);
832 tx_ring->stats.bytes += total_bytes;
833 tx_ring->stats.packets += total_packets;
834 u64_stats_update_end(&tx_ring->syncp);
835 q_vector->tx.total_bytes += total_bytes;
836 q_vector->tx.total_packets += total_packets;
837
838 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
839 /* schedule immediate reset if we believe we hung */
840 struct ixgbe_hw *hw = &adapter->hw;
841 e_err(drv, "Detected Tx Unit Hang\n"
842 " Tx Queue <%d>\n"
843 " TDH, TDT <%x>, <%x>\n"
844 " next_to_use <%x>\n"
845 " next_to_clean <%x>\n"
846 "tx_buffer_info[next_to_clean]\n"
847 " time_stamp <%lx>\n"
848 " jiffies <%lx>\n",
849 tx_ring->queue_index,
850 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
851 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
852 tx_ring->next_to_use, i,
853 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
854
855 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
856
857 e_info(probe,
858 "tx hang %d detected on queue %d, resetting adapter\n",
859 adapter->tx_timeout_count + 1, tx_ring->queue_index);
860
861 /* schedule immediate reset if we believe we hung */
862 ixgbe_tx_timeout_reset(adapter);
863
864 /* the adapter is about to reset, no point in enabling stuff */
865 return true;
866 }
867
868 netdev_tx_completed_queue(txring_txq(tx_ring),
869 total_packets, total_bytes);
870
871 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
872 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
873 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
874 /* Make sure that anybody stopping the queue after this
875 * sees the new next_to_clean.
876 */
877 smp_mb();
878 if (__netif_subqueue_stopped(tx_ring->netdev,
879 tx_ring->queue_index)
880 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
881 netif_wake_subqueue(tx_ring->netdev,
882 tx_ring->queue_index);
883 ++tx_ring->tx_stats.restart_queue;
884 }
885 }
886
887 return !!budget;
888 }
889
890 #ifdef CONFIG_IXGBE_DCA
ixgbe_update_tx_dca(struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring,int cpu)891 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
892 struct ixgbe_ring *tx_ring,
893 int cpu)
894 {
895 struct ixgbe_hw *hw = &adapter->hw;
896 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
897 u16 reg_offset;
898
899 switch (hw->mac.type) {
900 case ixgbe_mac_82598EB:
901 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
902 break;
903 case ixgbe_mac_82599EB:
904 case ixgbe_mac_X540:
905 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
906 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
907 break;
908 default:
909 /* for unknown hardware do not write register */
910 return;
911 }
912
913 /*
914 * We can enable relaxed ordering for reads, but not writes when
915 * DCA is enabled. This is due to a known issue in some chipsets
916 * which will cause the DCA tag to be cleared.
917 */
918 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
919 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
920 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
921
922 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
923 }
924
ixgbe_update_rx_dca(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring,int cpu)925 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
926 struct ixgbe_ring *rx_ring,
927 int cpu)
928 {
929 struct ixgbe_hw *hw = &adapter->hw;
930 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
931 u8 reg_idx = rx_ring->reg_idx;
932
933
934 switch (hw->mac.type) {
935 case ixgbe_mac_82599EB:
936 case ixgbe_mac_X540:
937 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
938 break;
939 default:
940 break;
941 }
942
943 /*
944 * We can enable relaxed ordering for reads, but not writes when
945 * DCA is enabled. This is due to a known issue in some chipsets
946 * which will cause the DCA tag to be cleared.
947 */
948 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
949 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
950 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
951
952 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
953 }
954
ixgbe_update_dca(struct ixgbe_q_vector * q_vector)955 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
956 {
957 struct ixgbe_adapter *adapter = q_vector->adapter;
958 struct ixgbe_ring *ring;
959 int cpu = get_cpu();
960
961 if (q_vector->cpu == cpu)
962 goto out_no_update;
963
964 ixgbe_for_each_ring(ring, q_vector->tx)
965 ixgbe_update_tx_dca(adapter, ring, cpu);
966
967 ixgbe_for_each_ring(ring, q_vector->rx)
968 ixgbe_update_rx_dca(adapter, ring, cpu);
969
970 q_vector->cpu = cpu;
971 out_no_update:
972 put_cpu();
973 }
974
ixgbe_setup_dca(struct ixgbe_adapter * adapter)975 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
976 {
977 int num_q_vectors;
978 int i;
979
980 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
981 return;
982
983 /* always use CB2 mode, difference is masked in the CB driver */
984 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
985
986 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
987 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
988 else
989 num_q_vectors = 1;
990
991 for (i = 0; i < num_q_vectors; i++) {
992 adapter->q_vector[i]->cpu = -1;
993 ixgbe_update_dca(adapter->q_vector[i]);
994 }
995 }
996
__ixgbe_notify_dca(struct device * dev,void * data)997 static int __ixgbe_notify_dca(struct device *dev, void *data)
998 {
999 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1000 unsigned long event = *(unsigned long *)data;
1001
1002 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1003 return 0;
1004
1005 switch (event) {
1006 case DCA_PROVIDER_ADD:
1007 /* if we're already enabled, don't do it again */
1008 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1009 break;
1010 if (dca_add_requester(dev) == 0) {
1011 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1012 ixgbe_setup_dca(adapter);
1013 break;
1014 }
1015 /* Fall Through since DCA is disabled. */
1016 case DCA_PROVIDER_REMOVE:
1017 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1018 dca_remove_requester(dev);
1019 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1020 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1021 }
1022 break;
1023 }
1024
1025 return 0;
1026 }
1027
1028 #endif /* CONFIG_IXGBE_DCA */
ixgbe_rx_hash(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1029 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1030 union ixgbe_adv_rx_desc *rx_desc,
1031 struct sk_buff *skb)
1032 {
1033 if (ring->netdev->features & NETIF_F_RXHASH)
1034 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1035 }
1036
1037 #ifdef IXGBE_FCOE
1038 /**
1039 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1040 * @ring: structure containing ring specific data
1041 * @rx_desc: advanced rx descriptor
1042 *
1043 * Returns : true if it is FCoE pkt
1044 */
ixgbe_rx_is_fcoe(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc)1045 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1046 union ixgbe_adv_rx_desc *rx_desc)
1047 {
1048 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1049
1050 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1051 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1052 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1053 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1054 }
1055
1056 #endif /* IXGBE_FCOE */
1057 /**
1058 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1059 * @ring: structure containing ring specific data
1060 * @rx_desc: current Rx descriptor being processed
1061 * @skb: skb currently being received and modified
1062 **/
ixgbe_rx_checksum(struct ixgbe_ring * ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1063 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1064 union ixgbe_adv_rx_desc *rx_desc,
1065 struct sk_buff *skb)
1066 {
1067 skb_checksum_none_assert(skb);
1068
1069 /* Rx csum disabled */
1070 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1071 return;
1072
1073 /* if IP and error */
1074 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1075 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1076 ring->rx_stats.csum_err++;
1077 return;
1078 }
1079
1080 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1081 return;
1082
1083 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1084 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1085
1086 /*
1087 * 82599 errata, UDP frames with a 0 checksum can be marked as
1088 * checksum errors.
1089 */
1090 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1091 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1092 return;
1093
1094 ring->rx_stats.csum_err++;
1095 return;
1096 }
1097
1098 /* It must be a TCP or UDP packet with a valid checksum */
1099 skb->ip_summed = CHECKSUM_UNNECESSARY;
1100 }
1101
ixgbe_release_rx_desc(struct ixgbe_ring * rx_ring,u32 val)1102 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1103 {
1104 rx_ring->next_to_use = val;
1105
1106 /* update next to alloc since we have filled the ring */
1107 rx_ring->next_to_alloc = val;
1108 /*
1109 * Force memory writes to complete before letting h/w
1110 * know there are new descriptors to fetch. (Only
1111 * applicable for weak-ordered memory model archs,
1112 * such as IA-64).
1113 */
1114 wmb();
1115 writel(val, rx_ring->tail);
1116 }
1117
ixgbe_alloc_mapped_page(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * bi)1118 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1119 struct ixgbe_rx_buffer *bi)
1120 {
1121 struct page *page = bi->page;
1122 dma_addr_t dma = bi->dma;
1123
1124 /* since we are recycling buffers we should seldom need to alloc */
1125 if (likely(dma))
1126 return true;
1127
1128 /* alloc new page for storage */
1129 if (likely(!page)) {
1130 page = alloc_pages(GFP_ATOMIC | __GFP_COLD,
1131 ixgbe_rx_pg_order(rx_ring));
1132 if (unlikely(!page)) {
1133 rx_ring->rx_stats.alloc_rx_page_failed++;
1134 return false;
1135 }
1136 bi->page = page;
1137 }
1138
1139 /* map page for use */
1140 dma = dma_map_page(rx_ring->dev, page, 0,
1141 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1142
1143 /*
1144 * if mapping failed free memory back to system since
1145 * there isn't much point in holding memory we can't use
1146 */
1147 if (dma_mapping_error(rx_ring->dev, dma)) {
1148 put_page(page);
1149 bi->page = NULL;
1150
1151 rx_ring->rx_stats.alloc_rx_page_failed++;
1152 return false;
1153 }
1154
1155 bi->dma = dma;
1156 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1157
1158 return true;
1159 }
1160
1161 /**
1162 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1163 * @rx_ring: ring to place buffers on
1164 * @cleaned_count: number of buffers to replace
1165 **/
ixgbe_alloc_rx_buffers(struct ixgbe_ring * rx_ring,u16 cleaned_count)1166 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1167 {
1168 union ixgbe_adv_rx_desc *rx_desc;
1169 struct ixgbe_rx_buffer *bi;
1170 u16 i = rx_ring->next_to_use;
1171
1172 /* nothing to do */
1173 if (!cleaned_count)
1174 return;
1175
1176 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1177 bi = &rx_ring->rx_buffer_info[i];
1178 i -= rx_ring->count;
1179
1180 do {
1181 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1182 break;
1183
1184 /*
1185 * Refresh the desc even if buffer_addrs didn't change
1186 * because each write-back erases this info.
1187 */
1188 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1189
1190 rx_desc++;
1191 bi++;
1192 i++;
1193 if (unlikely(!i)) {
1194 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1195 bi = rx_ring->rx_buffer_info;
1196 i -= rx_ring->count;
1197 }
1198
1199 /* clear the hdr_addr for the next_to_use descriptor */
1200 rx_desc->read.hdr_addr = 0;
1201
1202 cleaned_count--;
1203 } while (cleaned_count);
1204
1205 i += rx_ring->count;
1206
1207 if (rx_ring->next_to_use != i)
1208 ixgbe_release_rx_desc(rx_ring, i);
1209 }
1210
1211 /**
1212 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1213 * @data: pointer to the start of the headers
1214 * @max_len: total length of section to find headers in
1215 *
1216 * This function is meant to determine the length of headers that will
1217 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1218 * motivation of doing this is to only perform one pull for IPv4 TCP
1219 * packets so that we can do basic things like calculating the gso_size
1220 * based on the average data per packet.
1221 **/
ixgbe_get_headlen(unsigned char * data,unsigned int max_len)1222 static unsigned int ixgbe_get_headlen(unsigned char *data,
1223 unsigned int max_len)
1224 {
1225 union {
1226 unsigned char *network;
1227 /* l2 headers */
1228 struct ethhdr *eth;
1229 struct vlan_hdr *vlan;
1230 /* l3 headers */
1231 struct iphdr *ipv4;
1232 } hdr;
1233 __be16 protocol;
1234 u8 nexthdr = 0; /* default to not TCP */
1235 u8 hlen;
1236
1237 /* this should never happen, but better safe than sorry */
1238 if (max_len < ETH_HLEN)
1239 return max_len;
1240
1241 /* initialize network frame pointer */
1242 hdr.network = data;
1243
1244 /* set first protocol and move network header forward */
1245 protocol = hdr.eth->h_proto;
1246 hdr.network += ETH_HLEN;
1247
1248 /* handle any vlan tag if present */
1249 if (protocol == __constant_htons(ETH_P_8021Q)) {
1250 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1251 return max_len;
1252
1253 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1254 hdr.network += VLAN_HLEN;
1255 }
1256
1257 /* handle L3 protocols */
1258 if (protocol == __constant_htons(ETH_P_IP)) {
1259 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1260 return max_len;
1261
1262 /* access ihl as a u8 to avoid unaligned access on ia64 */
1263 hlen = (hdr.network[0] & 0x0F) << 2;
1264
1265 /* verify hlen meets minimum size requirements */
1266 if (hlen < sizeof(struct iphdr))
1267 return hdr.network - data;
1268
1269 /* record next protocol */
1270 nexthdr = hdr.ipv4->protocol;
1271 hdr.network += hlen;
1272 #ifdef IXGBE_FCOE
1273 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1274 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1275 return max_len;
1276 hdr.network += FCOE_HEADER_LEN;
1277 #endif
1278 } else {
1279 return hdr.network - data;
1280 }
1281
1282 /* finally sort out TCP */
1283 if (nexthdr == IPPROTO_TCP) {
1284 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1285 return max_len;
1286
1287 /* access doff as a u8 to avoid unaligned access on ia64 */
1288 hlen = (hdr.network[12] & 0xF0) >> 2;
1289
1290 /* verify hlen meets minimum size requirements */
1291 if (hlen < sizeof(struct tcphdr))
1292 return hdr.network - data;
1293
1294 hdr.network += hlen;
1295 }
1296
1297 /*
1298 * If everything has gone correctly hdr.network should be the
1299 * data section of the packet and will be the end of the header.
1300 * If not then it probably represents the end of the last recognized
1301 * header.
1302 */
1303 if ((hdr.network - data) < max_len)
1304 return hdr.network - data;
1305 else
1306 return max_len;
1307 }
1308
ixgbe_get_rsc_cnt(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1309 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1310 union ixgbe_adv_rx_desc *rx_desc,
1311 struct sk_buff *skb)
1312 {
1313 __le32 rsc_enabled;
1314 u32 rsc_cnt;
1315
1316 if (!ring_is_rsc_enabled(rx_ring))
1317 return;
1318
1319 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1320 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1321
1322 /* If this is an RSC frame rsc_cnt should be non-zero */
1323 if (!rsc_enabled)
1324 return;
1325
1326 rsc_cnt = le32_to_cpu(rsc_enabled);
1327 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1328
1329 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1330 }
1331
ixgbe_set_rsc_gso_size(struct ixgbe_ring * ring,struct sk_buff * skb)1332 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1333 struct sk_buff *skb)
1334 {
1335 u16 hdr_len = skb_headlen(skb);
1336
1337 /* set gso_size to avoid messing up TCP MSS */
1338 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1339 IXGBE_CB(skb)->append_cnt);
1340 }
1341
ixgbe_update_rsc_stats(struct ixgbe_ring * rx_ring,struct sk_buff * skb)1342 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1343 struct sk_buff *skb)
1344 {
1345 /* if append_cnt is 0 then frame is not RSC */
1346 if (!IXGBE_CB(skb)->append_cnt)
1347 return;
1348
1349 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1350 rx_ring->rx_stats.rsc_flush++;
1351
1352 ixgbe_set_rsc_gso_size(rx_ring, skb);
1353
1354 /* gso_size is computed using append_cnt so always clear it last */
1355 IXGBE_CB(skb)->append_cnt = 0;
1356 }
1357
1358 /**
1359 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1360 * @rx_ring: rx descriptor ring packet is being transacted on
1361 * @rx_desc: pointer to the EOP Rx descriptor
1362 * @skb: pointer to current skb being populated
1363 *
1364 * This function checks the ring, descriptor, and packet information in
1365 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1366 * other fields within the skb.
1367 **/
ixgbe_process_skb_fields(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1368 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1369 union ixgbe_adv_rx_desc *rx_desc,
1370 struct sk_buff *skb)
1371 {
1372 ixgbe_update_rsc_stats(rx_ring, skb);
1373
1374 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1375
1376 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1377
1378 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1379 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1380 __vlan_hwaccel_put_tag(skb, vid);
1381 }
1382
1383 skb_record_rx_queue(skb, rx_ring->queue_index);
1384
1385 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1386 }
1387
ixgbe_rx_skb(struct ixgbe_q_vector * q_vector,struct sk_buff * skb)1388 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1389 struct sk_buff *skb)
1390 {
1391 struct ixgbe_adapter *adapter = q_vector->adapter;
1392
1393 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1394 napi_gro_receive(&q_vector->napi, skb);
1395 else
1396 netif_rx(skb);
1397 }
1398
1399 /**
1400 * ixgbe_is_non_eop - process handling of non-EOP buffers
1401 * @rx_ring: Rx ring being processed
1402 * @rx_desc: Rx descriptor for current buffer
1403 * @skb: Current socket buffer containing buffer in progress
1404 *
1405 * This function updates next to clean. If the buffer is an EOP buffer
1406 * this function exits returning false, otherwise it will place the
1407 * sk_buff in the next buffer to be chained and return true indicating
1408 * that this is in fact a non-EOP buffer.
1409 **/
ixgbe_is_non_eop(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1410 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1411 union ixgbe_adv_rx_desc *rx_desc,
1412 struct sk_buff *skb)
1413 {
1414 u32 ntc = rx_ring->next_to_clean + 1;
1415
1416 /* fetch, update, and store next to clean */
1417 ntc = (ntc < rx_ring->count) ? ntc : 0;
1418 rx_ring->next_to_clean = ntc;
1419
1420 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1421
1422 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1423 return false;
1424
1425 /* append_cnt indicates packet is RSC, if so fetch nextp */
1426 if (IXGBE_CB(skb)->append_cnt) {
1427 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1428 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1429 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1430 }
1431
1432 /* place skb in next buffer to be received */
1433 rx_ring->rx_buffer_info[ntc].skb = skb;
1434 rx_ring->rx_stats.non_eop_descs++;
1435
1436 return true;
1437 }
1438
1439 /**
1440 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1441 * @rx_ring: rx descriptor ring packet is being transacted on
1442 * @rx_desc: pointer to the EOP Rx descriptor
1443 * @skb: pointer to current skb being fixed
1444 *
1445 * Check for corrupted packet headers caused by senders on the local L2
1446 * embedded NIC switch not setting up their Tx Descriptors right. These
1447 * should be very rare.
1448 *
1449 * Also address the case where we are pulling data in on pages only
1450 * and as such no data is present in the skb header.
1451 *
1452 * In addition if skb is not at least 60 bytes we need to pad it so that
1453 * it is large enough to qualify as a valid Ethernet frame.
1454 *
1455 * Returns true if an error was encountered and skb was freed.
1456 **/
ixgbe_cleanup_headers(struct ixgbe_ring * rx_ring,union ixgbe_adv_rx_desc * rx_desc,struct sk_buff * skb)1457 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1458 union ixgbe_adv_rx_desc *rx_desc,
1459 struct sk_buff *skb)
1460 {
1461 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1462 struct net_device *netdev = rx_ring->netdev;
1463 unsigned char *va;
1464 unsigned int pull_len;
1465
1466 /* if the page was released unmap it, else just sync our portion */
1467 if (unlikely(IXGBE_CB(skb)->page_released)) {
1468 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1469 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1470 IXGBE_CB(skb)->page_released = false;
1471 } else {
1472 dma_sync_single_range_for_cpu(rx_ring->dev,
1473 IXGBE_CB(skb)->dma,
1474 frag->page_offset,
1475 ixgbe_rx_bufsz(rx_ring),
1476 DMA_FROM_DEVICE);
1477 }
1478 IXGBE_CB(skb)->dma = 0;
1479
1480 /* verify that the packet does not have any known errors */
1481 if (unlikely(ixgbe_test_staterr(rx_desc,
1482 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1483 !(netdev->features & NETIF_F_RXALL))) {
1484 dev_kfree_skb_any(skb);
1485 return true;
1486 }
1487
1488 /*
1489 * it is valid to use page_address instead of kmap since we are
1490 * working with pages allocated out of the lomem pool per
1491 * alloc_page(GFP_ATOMIC)
1492 */
1493 va = skb_frag_address(frag);
1494
1495 /*
1496 * we need the header to contain the greater of either ETH_HLEN or
1497 * 60 bytes if the skb->len is less than 60 for skb_pad.
1498 */
1499 pull_len = skb_frag_size(frag);
1500 if (pull_len > 256)
1501 pull_len = ixgbe_get_headlen(va, pull_len);
1502
1503 /* align pull length to size of long to optimize memcpy performance */
1504 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1505
1506 /* update all of the pointers */
1507 skb_frag_size_sub(frag, pull_len);
1508 frag->page_offset += pull_len;
1509 skb->data_len -= pull_len;
1510 skb->tail += pull_len;
1511
1512 /*
1513 * if we sucked the frag empty then we should free it,
1514 * if there are other frags here something is screwed up in hardware
1515 */
1516 if (skb_frag_size(frag) == 0) {
1517 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1518 skb_shinfo(skb)->nr_frags = 0;
1519 __skb_frag_unref(frag);
1520 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1521 }
1522
1523 #ifdef IXGBE_FCOE
1524 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1525 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1526 return false;
1527
1528 #endif
1529 /* if skb_pad returns an error the skb was freed */
1530 if (unlikely(skb->len < 60)) {
1531 int pad_len = 60 - skb->len;
1532
1533 if (skb_pad(skb, pad_len))
1534 return true;
1535 __skb_put(skb, pad_len);
1536 }
1537
1538 return false;
1539 }
1540
1541 /**
1542 * ixgbe_can_reuse_page - determine if we can reuse a page
1543 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1544 *
1545 * Returns true if page can be reused in another Rx buffer
1546 **/
ixgbe_can_reuse_page(struct ixgbe_rx_buffer * rx_buffer)1547 static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1548 {
1549 struct page *page = rx_buffer->page;
1550
1551 /* if we are only owner of page and it is local we can reuse it */
1552 return likely(page_count(page) == 1) &&
1553 likely(page_to_nid(page) == numa_node_id());
1554 }
1555
1556 /**
1557 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1558 * @rx_ring: rx descriptor ring to store buffers on
1559 * @old_buff: donor buffer to have page reused
1560 *
1561 * Syncronizes page for reuse by the adapter
1562 **/
ixgbe_reuse_rx_page(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * old_buff)1563 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1564 struct ixgbe_rx_buffer *old_buff)
1565 {
1566 struct ixgbe_rx_buffer *new_buff;
1567 u16 nta = rx_ring->next_to_alloc;
1568 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1569
1570 new_buff = &rx_ring->rx_buffer_info[nta];
1571
1572 /* update, and store next to alloc */
1573 nta++;
1574 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1575
1576 /* transfer page from old buffer to new buffer */
1577 new_buff->page = old_buff->page;
1578 new_buff->dma = old_buff->dma;
1579
1580 /* flip page offset to other buffer and store to new_buff */
1581 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1582
1583 /* sync the buffer for use by the device */
1584 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1585 new_buff->page_offset, bufsz,
1586 DMA_FROM_DEVICE);
1587
1588 /* bump ref count on page before it is given to the stack */
1589 get_page(new_buff->page);
1590 }
1591
1592 /**
1593 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1594 * @rx_ring: rx descriptor ring to transact packets on
1595 * @rx_buffer: buffer containing page to add
1596 * @rx_desc: descriptor containing length of buffer written by hardware
1597 * @skb: sk_buff to place the data into
1598 *
1599 * This function is based on skb_add_rx_frag. I would have used that
1600 * function however it doesn't handle the truesize case correctly since we
1601 * are allocating more memory than might be used for a single receive.
1602 **/
ixgbe_add_rx_frag(struct ixgbe_ring * rx_ring,struct ixgbe_rx_buffer * rx_buffer,struct sk_buff * skb,int size)1603 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1604 struct ixgbe_rx_buffer *rx_buffer,
1605 struct sk_buff *skb, int size)
1606 {
1607 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1608 rx_buffer->page, rx_buffer->page_offset,
1609 size);
1610 skb->len += size;
1611 skb->data_len += size;
1612 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1613 }
1614
1615 /**
1616 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1617 * @q_vector: structure containing interrupt and ring information
1618 * @rx_ring: rx descriptor ring to transact packets on
1619 * @budget: Total limit on number of packets to process
1620 *
1621 * This function provides a "bounce buffer" approach to Rx interrupt
1622 * processing. The advantage to this is that on systems that have
1623 * expensive overhead for IOMMU access this provides a means of avoiding
1624 * it by maintaining the mapping of the page to the syste.
1625 *
1626 * Returns true if all work is completed without reaching budget
1627 **/
ixgbe_clean_rx_irq(struct ixgbe_q_vector * q_vector,struct ixgbe_ring * rx_ring,int budget)1628 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1629 struct ixgbe_ring *rx_ring,
1630 int budget)
1631 {
1632 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1633 #ifdef IXGBE_FCOE
1634 struct ixgbe_adapter *adapter = q_vector->adapter;
1635 int ddp_bytes = 0;
1636 #endif /* IXGBE_FCOE */
1637 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1638
1639 do {
1640 struct ixgbe_rx_buffer *rx_buffer;
1641 union ixgbe_adv_rx_desc *rx_desc;
1642 struct sk_buff *skb;
1643 struct page *page;
1644 u16 ntc;
1645
1646 /* return some buffers to hardware, one at a time is too slow */
1647 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1648 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1649 cleaned_count = 0;
1650 }
1651
1652 ntc = rx_ring->next_to_clean;
1653 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1654 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1655
1656 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1657 break;
1658
1659 /*
1660 * This memory barrier is needed to keep us from reading
1661 * any other fields out of the rx_desc until we know the
1662 * RXD_STAT_DD bit is set
1663 */
1664 rmb();
1665
1666 page = rx_buffer->page;
1667 prefetchw(page);
1668
1669 skb = rx_buffer->skb;
1670
1671 if (likely(!skb)) {
1672 void *page_addr = page_address(page) +
1673 rx_buffer->page_offset;
1674
1675 /* prefetch first cache line of first page */
1676 prefetch(page_addr);
1677 #if L1_CACHE_BYTES < 128
1678 prefetch(page_addr + L1_CACHE_BYTES);
1679 #endif
1680
1681 /* allocate a skb to store the frags */
1682 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1683 IXGBE_RX_HDR_SIZE);
1684 if (unlikely(!skb)) {
1685 rx_ring->rx_stats.alloc_rx_buff_failed++;
1686 break;
1687 }
1688
1689 /*
1690 * we will be copying header into skb->data in
1691 * pskb_may_pull so it is in our interest to prefetch
1692 * it now to avoid a possible cache miss
1693 */
1694 prefetchw(skb->data);
1695
1696 /*
1697 * Delay unmapping of the first packet. It carries the
1698 * header information, HW may still access the header
1699 * after the writeback. Only unmap it when EOP is
1700 * reached
1701 */
1702 IXGBE_CB(skb)->dma = rx_buffer->dma;
1703 } else {
1704 /* we are reusing so sync this buffer for CPU use */
1705 dma_sync_single_range_for_cpu(rx_ring->dev,
1706 rx_buffer->dma,
1707 rx_buffer->page_offset,
1708 ixgbe_rx_bufsz(rx_ring),
1709 DMA_FROM_DEVICE);
1710 }
1711
1712 /* pull page into skb */
1713 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1714 le16_to_cpu(rx_desc->wb.upper.length));
1715
1716 if (ixgbe_can_reuse_page(rx_buffer)) {
1717 /* hand second half of page back to the ring */
1718 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1719 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1720 /* the page has been released from the ring */
1721 IXGBE_CB(skb)->page_released = true;
1722 } else {
1723 /* we are not reusing the buffer so unmap it */
1724 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1725 ixgbe_rx_pg_size(rx_ring),
1726 DMA_FROM_DEVICE);
1727 }
1728
1729 /* clear contents of buffer_info */
1730 rx_buffer->skb = NULL;
1731 rx_buffer->dma = 0;
1732 rx_buffer->page = NULL;
1733
1734 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1735
1736 cleaned_count++;
1737
1738 /* place incomplete frames back on ring for completion */
1739 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1740 continue;
1741
1742 /* verify the packet layout is correct */
1743 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1744 continue;
1745
1746 /* probably a little skewed due to removing CRC */
1747 total_rx_bytes += skb->len;
1748 total_rx_packets++;
1749
1750 /* populate checksum, timestamp, VLAN, and protocol */
1751 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1752
1753 #ifdef IXGBE_FCOE
1754 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1755 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
1756 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1757 if (!ddp_bytes) {
1758 dev_kfree_skb_any(skb);
1759 continue;
1760 }
1761 }
1762
1763 #endif /* IXGBE_FCOE */
1764 ixgbe_rx_skb(q_vector, skb);
1765
1766 /* update budget accounting */
1767 budget--;
1768 } while (likely(budget));
1769
1770 #ifdef IXGBE_FCOE
1771 /* include DDPed FCoE data */
1772 if (ddp_bytes > 0) {
1773 unsigned int mss;
1774
1775 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1776 sizeof(struct fc_frame_header) -
1777 sizeof(struct fcoe_crc_eof);
1778 if (mss > 512)
1779 mss &= ~511;
1780 total_rx_bytes += ddp_bytes;
1781 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1782 }
1783
1784 #endif /* IXGBE_FCOE */
1785 u64_stats_update_begin(&rx_ring->syncp);
1786 rx_ring->stats.packets += total_rx_packets;
1787 rx_ring->stats.bytes += total_rx_bytes;
1788 u64_stats_update_end(&rx_ring->syncp);
1789 q_vector->rx.total_packets += total_rx_packets;
1790 q_vector->rx.total_bytes += total_rx_bytes;
1791
1792 if (cleaned_count)
1793 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1794
1795 return !!budget;
1796 }
1797
1798 /**
1799 * ixgbe_configure_msix - Configure MSI-X hardware
1800 * @adapter: board private structure
1801 *
1802 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1803 * interrupts.
1804 **/
ixgbe_configure_msix(struct ixgbe_adapter * adapter)1805 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1806 {
1807 struct ixgbe_q_vector *q_vector;
1808 int q_vectors, v_idx;
1809 u32 mask;
1810
1811 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1812
1813 /* Populate MSIX to EITR Select */
1814 if (adapter->num_vfs > 32) {
1815 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1816 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1817 }
1818
1819 /*
1820 * Populate the IVAR table and set the ITR values to the
1821 * corresponding register.
1822 */
1823 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1824 struct ixgbe_ring *ring;
1825 q_vector = adapter->q_vector[v_idx];
1826
1827 ixgbe_for_each_ring(ring, q_vector->rx)
1828 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1829
1830 ixgbe_for_each_ring(ring, q_vector->tx)
1831 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1832
1833 if (q_vector->tx.ring && !q_vector->rx.ring) {
1834 /* tx only vector */
1835 if (adapter->tx_itr_setting == 1)
1836 q_vector->itr = IXGBE_10K_ITR;
1837 else
1838 q_vector->itr = adapter->tx_itr_setting;
1839 } else {
1840 /* rx or rx/tx vector */
1841 if (adapter->rx_itr_setting == 1)
1842 q_vector->itr = IXGBE_20K_ITR;
1843 else
1844 q_vector->itr = adapter->rx_itr_setting;
1845 }
1846
1847 ixgbe_write_eitr(q_vector);
1848 }
1849
1850 switch (adapter->hw.mac.type) {
1851 case ixgbe_mac_82598EB:
1852 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1853 v_idx);
1854 break;
1855 case ixgbe_mac_82599EB:
1856 case ixgbe_mac_X540:
1857 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1858 break;
1859 default:
1860 break;
1861 }
1862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1863
1864 /* set up to autoclear timer, and the vectors */
1865 mask = IXGBE_EIMS_ENABLE_MASK;
1866 mask &= ~(IXGBE_EIMS_OTHER |
1867 IXGBE_EIMS_MAILBOX |
1868 IXGBE_EIMS_LSC);
1869
1870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1871 }
1872
1873 enum latency_range {
1874 lowest_latency = 0,
1875 low_latency = 1,
1876 bulk_latency = 2,
1877 latency_invalid = 255
1878 };
1879
1880 /**
1881 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1882 * @q_vector: structure containing interrupt and ring information
1883 * @ring_container: structure containing ring performance data
1884 *
1885 * Stores a new ITR value based on packets and byte
1886 * counts during the last interrupt. The advantage of per interrupt
1887 * computation is faster updates and more accurate ITR for the current
1888 * traffic pattern. Constants in this function were computed
1889 * based on theoretical maximum wire speed and thresholds were set based
1890 * on testing data as well as attempting to minimize response time
1891 * while increasing bulk throughput.
1892 * this functionality is controlled by the InterruptThrottleRate module
1893 * parameter (see ixgbe_param.c)
1894 **/
ixgbe_update_itr(struct ixgbe_q_vector * q_vector,struct ixgbe_ring_container * ring_container)1895 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1896 struct ixgbe_ring_container *ring_container)
1897 {
1898 int bytes = ring_container->total_bytes;
1899 int packets = ring_container->total_packets;
1900 u32 timepassed_us;
1901 u64 bytes_perint;
1902 u8 itr_setting = ring_container->itr;
1903
1904 if (packets == 0)
1905 return;
1906
1907 /* simple throttlerate management
1908 * 0-10MB/s lowest (100000 ints/s)
1909 * 10-20MB/s low (20000 ints/s)
1910 * 20-1249MB/s bulk (8000 ints/s)
1911 */
1912 /* what was last interrupt timeslice? */
1913 timepassed_us = q_vector->itr >> 2;
1914 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1915
1916 switch (itr_setting) {
1917 case lowest_latency:
1918 if (bytes_perint > 10)
1919 itr_setting = low_latency;
1920 break;
1921 case low_latency:
1922 if (bytes_perint > 20)
1923 itr_setting = bulk_latency;
1924 else if (bytes_perint <= 10)
1925 itr_setting = lowest_latency;
1926 break;
1927 case bulk_latency:
1928 if (bytes_perint <= 20)
1929 itr_setting = low_latency;
1930 break;
1931 }
1932
1933 /* clear work counters since we have the values we need */
1934 ring_container->total_bytes = 0;
1935 ring_container->total_packets = 0;
1936
1937 /* write updated itr to ring container */
1938 ring_container->itr = itr_setting;
1939 }
1940
1941 /**
1942 * ixgbe_write_eitr - write EITR register in hardware specific way
1943 * @q_vector: structure containing interrupt and ring information
1944 *
1945 * This function is made to be called by ethtool and by the driver
1946 * when it needs to update EITR registers at runtime. Hardware
1947 * specific quirks/differences are taken care of here.
1948 */
ixgbe_write_eitr(struct ixgbe_q_vector * q_vector)1949 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1950 {
1951 struct ixgbe_adapter *adapter = q_vector->adapter;
1952 struct ixgbe_hw *hw = &adapter->hw;
1953 int v_idx = q_vector->v_idx;
1954 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
1955
1956 switch (adapter->hw.mac.type) {
1957 case ixgbe_mac_82598EB:
1958 /* must write high and low 16 bits to reset counter */
1959 itr_reg |= (itr_reg << 16);
1960 break;
1961 case ixgbe_mac_82599EB:
1962 case ixgbe_mac_X540:
1963 /*
1964 * set the WDIS bit to not clear the timer bits and cause an
1965 * immediate assertion of the interrupt
1966 */
1967 itr_reg |= IXGBE_EITR_CNT_WDIS;
1968 break;
1969 default:
1970 break;
1971 }
1972 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1973 }
1974
ixgbe_set_itr(struct ixgbe_q_vector * q_vector)1975 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1976 {
1977 u32 new_itr = q_vector->itr;
1978 u8 current_itr;
1979
1980 ixgbe_update_itr(q_vector, &q_vector->tx);
1981 ixgbe_update_itr(q_vector, &q_vector->rx);
1982
1983 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1984
1985 switch (current_itr) {
1986 /* counts and packets in update_itr are dependent on these numbers */
1987 case lowest_latency:
1988 new_itr = IXGBE_100K_ITR;
1989 break;
1990 case low_latency:
1991 new_itr = IXGBE_20K_ITR;
1992 break;
1993 case bulk_latency:
1994 new_itr = IXGBE_8K_ITR;
1995 break;
1996 default:
1997 break;
1998 }
1999
2000 if (new_itr != q_vector->itr) {
2001 /* do an exponential smoothing */
2002 new_itr = (10 * new_itr * q_vector->itr) /
2003 ((9 * new_itr) + q_vector->itr);
2004
2005 /* save the algorithm value here */
2006 q_vector->itr = new_itr;
2007
2008 ixgbe_write_eitr(q_vector);
2009 }
2010 }
2011
2012 /**
2013 * ixgbe_check_overtemp_subtask - check for over temperature
2014 * @adapter: pointer to adapter
2015 **/
ixgbe_check_overtemp_subtask(struct ixgbe_adapter * adapter)2016 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2017 {
2018 struct ixgbe_hw *hw = &adapter->hw;
2019 u32 eicr = adapter->interrupt_event;
2020
2021 if (test_bit(__IXGBE_DOWN, &adapter->state))
2022 return;
2023
2024 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2025 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2026 return;
2027
2028 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2029
2030 switch (hw->device_id) {
2031 case IXGBE_DEV_ID_82599_T3_LOM:
2032 /*
2033 * Since the warning interrupt is for both ports
2034 * we don't have to check if:
2035 * - This interrupt wasn't for our port.
2036 * - We may have missed the interrupt so always have to
2037 * check if we got a LSC
2038 */
2039 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2040 !(eicr & IXGBE_EICR_LSC))
2041 return;
2042
2043 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2044 u32 autoneg;
2045 bool link_up = false;
2046
2047 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2048
2049 if (link_up)
2050 return;
2051 }
2052
2053 /* Check if this is not due to overtemp */
2054 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2055 return;
2056
2057 break;
2058 default:
2059 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2060 return;
2061 break;
2062 }
2063 e_crit(drv,
2064 "Network adapter has been stopped because it has over heated. "
2065 "Restart the computer. If the problem persists, "
2066 "power off the system and replace the adapter\n");
2067
2068 adapter->interrupt_event = 0;
2069 }
2070
ixgbe_check_fan_failure(struct ixgbe_adapter * adapter,u32 eicr)2071 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2072 {
2073 struct ixgbe_hw *hw = &adapter->hw;
2074
2075 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2076 (eicr & IXGBE_EICR_GPI_SDP1)) {
2077 e_crit(probe, "Fan has stopped, replace the adapter\n");
2078 /* write to clear the interrupt */
2079 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2080 }
2081 }
2082
ixgbe_check_overtemp_event(struct ixgbe_adapter * adapter,u32 eicr)2083 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2084 {
2085 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2086 return;
2087
2088 switch (adapter->hw.mac.type) {
2089 case ixgbe_mac_82599EB:
2090 /*
2091 * Need to check link state so complete overtemp check
2092 * on service task
2093 */
2094 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2095 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2096 adapter->interrupt_event = eicr;
2097 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2098 ixgbe_service_event_schedule(adapter);
2099 return;
2100 }
2101 return;
2102 case ixgbe_mac_X540:
2103 if (!(eicr & IXGBE_EICR_TS))
2104 return;
2105 break;
2106 default:
2107 return;
2108 }
2109
2110 e_crit(drv,
2111 "Network adapter has been stopped because it has over heated. "
2112 "Restart the computer. If the problem persists, "
2113 "power off the system and replace the adapter\n");
2114 }
2115
ixgbe_check_sfp_event(struct ixgbe_adapter * adapter,u32 eicr)2116 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2117 {
2118 struct ixgbe_hw *hw = &adapter->hw;
2119
2120 if (eicr & IXGBE_EICR_GPI_SDP2) {
2121 /* Clear the interrupt */
2122 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2123 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2124 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2125 ixgbe_service_event_schedule(adapter);
2126 }
2127 }
2128
2129 if (eicr & IXGBE_EICR_GPI_SDP1) {
2130 /* Clear the interrupt */
2131 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2132 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2133 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2134 ixgbe_service_event_schedule(adapter);
2135 }
2136 }
2137 }
2138
ixgbe_check_lsc(struct ixgbe_adapter * adapter)2139 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2140 {
2141 struct ixgbe_hw *hw = &adapter->hw;
2142
2143 adapter->lsc_int++;
2144 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2145 adapter->link_check_timeout = jiffies;
2146 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2147 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2148 IXGBE_WRITE_FLUSH(hw);
2149 ixgbe_service_event_schedule(adapter);
2150 }
2151 }
2152
ixgbe_irq_enable_queues(struct ixgbe_adapter * adapter,u64 qmask)2153 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2154 u64 qmask)
2155 {
2156 u32 mask;
2157 struct ixgbe_hw *hw = &adapter->hw;
2158
2159 switch (hw->mac.type) {
2160 case ixgbe_mac_82598EB:
2161 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2162 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2163 break;
2164 case ixgbe_mac_82599EB:
2165 case ixgbe_mac_X540:
2166 mask = (qmask & 0xFFFFFFFF);
2167 if (mask)
2168 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2169 mask = (qmask >> 32);
2170 if (mask)
2171 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2172 break;
2173 default:
2174 break;
2175 }
2176 /* skip the flush */
2177 }
2178
ixgbe_irq_disable_queues(struct ixgbe_adapter * adapter,u64 qmask)2179 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2180 u64 qmask)
2181 {
2182 u32 mask;
2183 struct ixgbe_hw *hw = &adapter->hw;
2184
2185 switch (hw->mac.type) {
2186 case ixgbe_mac_82598EB:
2187 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2188 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2189 break;
2190 case ixgbe_mac_82599EB:
2191 case ixgbe_mac_X540:
2192 mask = (qmask & 0xFFFFFFFF);
2193 if (mask)
2194 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2195 mask = (qmask >> 32);
2196 if (mask)
2197 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2198 break;
2199 default:
2200 break;
2201 }
2202 /* skip the flush */
2203 }
2204
2205 /**
2206 * ixgbe_irq_enable - Enable default interrupt generation settings
2207 * @adapter: board private structure
2208 **/
ixgbe_irq_enable(struct ixgbe_adapter * adapter,bool queues,bool flush)2209 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2210 bool flush)
2211 {
2212 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2213
2214 /* don't reenable LSC while waiting for link */
2215 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2216 mask &= ~IXGBE_EIMS_LSC;
2217
2218 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2219 switch (adapter->hw.mac.type) {
2220 case ixgbe_mac_82599EB:
2221 mask |= IXGBE_EIMS_GPI_SDP0;
2222 break;
2223 case ixgbe_mac_X540:
2224 mask |= IXGBE_EIMS_TS;
2225 break;
2226 default:
2227 break;
2228 }
2229 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2230 mask |= IXGBE_EIMS_GPI_SDP1;
2231 switch (adapter->hw.mac.type) {
2232 case ixgbe_mac_82599EB:
2233 mask |= IXGBE_EIMS_GPI_SDP1;
2234 mask |= IXGBE_EIMS_GPI_SDP2;
2235 case ixgbe_mac_X540:
2236 mask |= IXGBE_EIMS_ECC;
2237 mask |= IXGBE_EIMS_MAILBOX;
2238 break;
2239 default:
2240 break;
2241 }
2242 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2243 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2244 mask |= IXGBE_EIMS_FLOW_DIR;
2245
2246 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2247 if (queues)
2248 ixgbe_irq_enable_queues(adapter, ~0);
2249 if (flush)
2250 IXGBE_WRITE_FLUSH(&adapter->hw);
2251 }
2252
ixgbe_msix_other(int irq,void * data)2253 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2254 {
2255 struct ixgbe_adapter *adapter = data;
2256 struct ixgbe_hw *hw = &adapter->hw;
2257 u32 eicr;
2258
2259 /*
2260 * Workaround for Silicon errata. Use clear-by-write instead
2261 * of clear-by-read. Reading with EICS will return the
2262 * interrupt causes without clearing, which later be done
2263 * with the write to EICR.
2264 */
2265 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2266
2267 /* The lower 16bits of the EICR register are for the queue interrupts
2268 * which should be masked here in order to not accidently clear them if
2269 * the bits are high when ixgbe_msix_other is called. There is a race
2270 * condition otherwise which results in possible performance loss
2271 * especially if the ixgbe_msix_other interrupt is triggering
2272 * consistently (as it would when PPS is turned on for the X540 device)
2273 */
2274 eicr &= 0xFFFF0000;
2275
2276 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2277
2278 if (eicr & IXGBE_EICR_LSC)
2279 ixgbe_check_lsc(adapter);
2280
2281 if (eicr & IXGBE_EICR_MAILBOX)
2282 ixgbe_msg_task(adapter);
2283
2284 switch (hw->mac.type) {
2285 case ixgbe_mac_82599EB:
2286 case ixgbe_mac_X540:
2287 if (eicr & IXGBE_EICR_ECC)
2288 e_info(link, "Received unrecoverable ECC Err, please "
2289 "reboot\n");
2290 /* Handle Flow Director Full threshold interrupt */
2291 if (eicr & IXGBE_EICR_FLOW_DIR) {
2292 int reinit_count = 0;
2293 int i;
2294 for (i = 0; i < adapter->num_tx_queues; i++) {
2295 struct ixgbe_ring *ring = adapter->tx_ring[i];
2296 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2297 &ring->state))
2298 reinit_count++;
2299 }
2300 if (reinit_count) {
2301 /* no more flow director interrupts until after init */
2302 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2303 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2304 ixgbe_service_event_schedule(adapter);
2305 }
2306 }
2307 ixgbe_check_sfp_event(adapter, eicr);
2308 ixgbe_check_overtemp_event(adapter, eicr);
2309 break;
2310 default:
2311 break;
2312 }
2313
2314 ixgbe_check_fan_failure(adapter, eicr);
2315
2316 /* re-enable the original interrupt state, no lsc, no queues */
2317 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2318 ixgbe_irq_enable(adapter, false, false);
2319
2320 return IRQ_HANDLED;
2321 }
2322
ixgbe_msix_clean_rings(int irq,void * data)2323 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2324 {
2325 struct ixgbe_q_vector *q_vector = data;
2326
2327 /* EIAM disabled interrupts (on this vector) for us */
2328
2329 if (q_vector->rx.ring || q_vector->tx.ring)
2330 napi_schedule(&q_vector->napi);
2331
2332 return IRQ_HANDLED;
2333 }
2334
2335 /**
2336 * ixgbe_poll - NAPI Rx polling callback
2337 * @napi: structure for representing this polling device
2338 * @budget: how many packets driver is allowed to clean
2339 *
2340 * This function is used for legacy and MSI, NAPI mode
2341 **/
ixgbe_poll(struct napi_struct * napi,int budget)2342 int ixgbe_poll(struct napi_struct *napi, int budget)
2343 {
2344 struct ixgbe_q_vector *q_vector =
2345 container_of(napi, struct ixgbe_q_vector, napi);
2346 struct ixgbe_adapter *adapter = q_vector->adapter;
2347 struct ixgbe_ring *ring;
2348 int per_ring_budget;
2349 bool clean_complete = true;
2350
2351 #ifdef CONFIG_IXGBE_DCA
2352 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2353 ixgbe_update_dca(q_vector);
2354 #endif
2355
2356 ixgbe_for_each_ring(ring, q_vector->tx)
2357 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2358
2359 /* attempt to distribute budget to each queue fairly, but don't allow
2360 * the budget to go below 1 because we'll exit polling */
2361 if (q_vector->rx.count > 1)
2362 per_ring_budget = max(budget/q_vector->rx.count, 1);
2363 else
2364 per_ring_budget = budget;
2365
2366 ixgbe_for_each_ring(ring, q_vector->rx)
2367 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2368 per_ring_budget);
2369
2370 /* If all work not completed, return budget and keep polling */
2371 if (!clean_complete)
2372 return budget;
2373
2374 /* all work done, exit the polling mode */
2375 napi_complete(napi);
2376 if (adapter->rx_itr_setting & 1)
2377 ixgbe_set_itr(q_vector);
2378 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2379 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2380
2381 return 0;
2382 }
2383
2384 /**
2385 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2386 * @adapter: board private structure
2387 *
2388 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2389 * interrupts from the kernel.
2390 **/
ixgbe_request_msix_irqs(struct ixgbe_adapter * adapter)2391 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2392 {
2393 struct net_device *netdev = adapter->netdev;
2394 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2395 int vector, err;
2396 int ri = 0, ti = 0;
2397
2398 for (vector = 0; vector < q_vectors; vector++) {
2399 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2400 struct msix_entry *entry = &adapter->msix_entries[vector];
2401
2402 if (q_vector->tx.ring && q_vector->rx.ring) {
2403 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2404 "%s-%s-%d", netdev->name, "TxRx", ri++);
2405 ti++;
2406 } else if (q_vector->rx.ring) {
2407 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2408 "%s-%s-%d", netdev->name, "rx", ri++);
2409 } else if (q_vector->tx.ring) {
2410 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2411 "%s-%s-%d", netdev->name, "tx", ti++);
2412 } else {
2413 /* skip this unused q_vector */
2414 continue;
2415 }
2416 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2417 q_vector->name, q_vector);
2418 if (err) {
2419 e_err(probe, "request_irq failed for MSIX interrupt "
2420 "Error: %d\n", err);
2421 goto free_queue_irqs;
2422 }
2423 /* If Flow Director is enabled, set interrupt affinity */
2424 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2425 /* assign the mask for this irq */
2426 irq_set_affinity_hint(entry->vector,
2427 &q_vector->affinity_mask);
2428 }
2429 }
2430
2431 err = request_irq(adapter->msix_entries[vector].vector,
2432 ixgbe_msix_other, 0, netdev->name, adapter);
2433 if (err) {
2434 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2435 goto free_queue_irqs;
2436 }
2437
2438 return 0;
2439
2440 free_queue_irqs:
2441 while (vector) {
2442 vector--;
2443 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2444 NULL);
2445 free_irq(adapter->msix_entries[vector].vector,
2446 adapter->q_vector[vector]);
2447 }
2448 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2449 pci_disable_msix(adapter->pdev);
2450 kfree(adapter->msix_entries);
2451 adapter->msix_entries = NULL;
2452 return err;
2453 }
2454
2455 /**
2456 * ixgbe_intr - legacy mode Interrupt Handler
2457 * @irq: interrupt number
2458 * @data: pointer to a network interface device structure
2459 **/
ixgbe_intr(int irq,void * data)2460 static irqreturn_t ixgbe_intr(int irq, void *data)
2461 {
2462 struct ixgbe_adapter *adapter = data;
2463 struct ixgbe_hw *hw = &adapter->hw;
2464 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2465 u32 eicr;
2466
2467 /*
2468 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2469 * before the read of EICR.
2470 */
2471 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2472
2473 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2474 * therefore no explicit interrupt disable is necessary */
2475 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2476 if (!eicr) {
2477 /*
2478 * shared interrupt alert!
2479 * make sure interrupts are enabled because the read will
2480 * have disabled interrupts due to EIAM
2481 * finish the workaround of silicon errata on 82598. Unmask
2482 * the interrupt that we masked before the EICR read.
2483 */
2484 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2485 ixgbe_irq_enable(adapter, true, true);
2486 return IRQ_NONE; /* Not our interrupt */
2487 }
2488
2489 if (eicr & IXGBE_EICR_LSC)
2490 ixgbe_check_lsc(adapter);
2491
2492 switch (hw->mac.type) {
2493 case ixgbe_mac_82599EB:
2494 ixgbe_check_sfp_event(adapter, eicr);
2495 /* Fall through */
2496 case ixgbe_mac_X540:
2497 if (eicr & IXGBE_EICR_ECC)
2498 e_info(link, "Received unrecoverable ECC err, please "
2499 "reboot\n");
2500 ixgbe_check_overtemp_event(adapter, eicr);
2501 break;
2502 default:
2503 break;
2504 }
2505
2506 ixgbe_check_fan_failure(adapter, eicr);
2507
2508 /* would disable interrupts here but EIAM disabled it */
2509 napi_schedule(&q_vector->napi);
2510
2511 /*
2512 * re-enable link(maybe) and non-queue interrupts, no flush.
2513 * ixgbe_poll will re-enable the queue interrupts
2514 */
2515 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2516 ixgbe_irq_enable(adapter, false, false);
2517
2518 return IRQ_HANDLED;
2519 }
2520
2521 /**
2522 * ixgbe_request_irq - initialize interrupts
2523 * @adapter: board private structure
2524 *
2525 * Attempts to configure interrupts using the best available
2526 * capabilities of the hardware and kernel.
2527 **/
ixgbe_request_irq(struct ixgbe_adapter * adapter)2528 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2529 {
2530 struct net_device *netdev = adapter->netdev;
2531 int err;
2532
2533 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2534 err = ixgbe_request_msix_irqs(adapter);
2535 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2536 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2537 netdev->name, adapter);
2538 else
2539 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2540 netdev->name, adapter);
2541
2542 if (err)
2543 e_err(probe, "request_irq failed, Error %d\n", err);
2544
2545 return err;
2546 }
2547
ixgbe_free_irq(struct ixgbe_adapter * adapter)2548 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2549 {
2550 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2551 int i, q_vectors;
2552
2553 q_vectors = adapter->num_msix_vectors;
2554 i = q_vectors - 1;
2555 free_irq(adapter->msix_entries[i].vector, adapter);
2556 i--;
2557
2558 for (; i >= 0; i--) {
2559 /* free only the irqs that were actually requested */
2560 if (!adapter->q_vector[i]->rx.ring &&
2561 !adapter->q_vector[i]->tx.ring)
2562 continue;
2563
2564 /* clear the affinity_mask in the IRQ descriptor */
2565 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2566 NULL);
2567
2568 free_irq(adapter->msix_entries[i].vector,
2569 adapter->q_vector[i]);
2570 }
2571 } else {
2572 free_irq(adapter->pdev->irq, adapter);
2573 }
2574 }
2575
2576 /**
2577 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2578 * @adapter: board private structure
2579 **/
ixgbe_irq_disable(struct ixgbe_adapter * adapter)2580 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2581 {
2582 switch (adapter->hw.mac.type) {
2583 case ixgbe_mac_82598EB:
2584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2585 break;
2586 case ixgbe_mac_82599EB:
2587 case ixgbe_mac_X540:
2588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2591 break;
2592 default:
2593 break;
2594 }
2595 IXGBE_WRITE_FLUSH(&adapter->hw);
2596 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2597 int i;
2598 for (i = 0; i < adapter->num_msix_vectors; i++)
2599 synchronize_irq(adapter->msix_entries[i].vector);
2600 } else {
2601 synchronize_irq(adapter->pdev->irq);
2602 }
2603 }
2604
2605 /**
2606 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2607 *
2608 **/
ixgbe_configure_msi_and_legacy(struct ixgbe_adapter * adapter)2609 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2610 {
2611 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2612
2613 /* rx/tx vector */
2614 if (adapter->rx_itr_setting == 1)
2615 q_vector->itr = IXGBE_20K_ITR;
2616 else
2617 q_vector->itr = adapter->rx_itr_setting;
2618
2619 ixgbe_write_eitr(q_vector);
2620
2621 ixgbe_set_ivar(adapter, 0, 0, 0);
2622 ixgbe_set_ivar(adapter, 1, 0, 0);
2623
2624 e_info(hw, "Legacy interrupt IVAR setup done\n");
2625 }
2626
2627 /**
2628 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2629 * @adapter: board private structure
2630 * @ring: structure containing ring specific data
2631 *
2632 * Configure the Tx descriptor ring after a reset.
2633 **/
ixgbe_configure_tx_ring(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)2634 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2635 struct ixgbe_ring *ring)
2636 {
2637 struct ixgbe_hw *hw = &adapter->hw;
2638 u64 tdba = ring->dma;
2639 int wait_loop = 10;
2640 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2641 u8 reg_idx = ring->reg_idx;
2642
2643 /* disable queue to avoid issues while updating state */
2644 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2645 IXGBE_WRITE_FLUSH(hw);
2646
2647 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2648 (tdba & DMA_BIT_MASK(32)));
2649 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2650 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2651 ring->count * sizeof(union ixgbe_adv_tx_desc));
2652 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2653 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2654 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2655
2656 /*
2657 * set WTHRESH to encourage burst writeback, it should not be set
2658 * higher than 1 when ITR is 0 as it could cause false TX hangs
2659 *
2660 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2661 * to or less than the number of on chip descriptors, which is
2662 * currently 40.
2663 */
2664 if (!ring->q_vector || (ring->q_vector->itr < 8))
2665 txdctl |= (1 << 16); /* WTHRESH = 1 */
2666 else
2667 txdctl |= (8 << 16); /* WTHRESH = 8 */
2668
2669 /*
2670 * Setting PTHRESH to 32 both improves performance
2671 * and avoids a TX hang with DFP enabled
2672 */
2673 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2674 32; /* PTHRESH = 32 */
2675
2676 /* reinitialize flowdirector state */
2677 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2678 adapter->atr_sample_rate) {
2679 ring->atr_sample_rate = adapter->atr_sample_rate;
2680 ring->atr_count = 0;
2681 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2682 } else {
2683 ring->atr_sample_rate = 0;
2684 }
2685
2686 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2687
2688 /* enable queue */
2689 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2690
2691 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2692 if (hw->mac.type == ixgbe_mac_82598EB &&
2693 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2694 return;
2695
2696 /* poll to verify queue is enabled */
2697 do {
2698 usleep_range(1000, 2000);
2699 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2700 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2701 if (!wait_loop)
2702 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2703 }
2704
ixgbe_setup_mtqc(struct ixgbe_adapter * adapter)2705 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2706 {
2707 struct ixgbe_hw *hw = &adapter->hw;
2708 u32 rttdcs;
2709 u32 reg;
2710 u8 tcs = netdev_get_num_tc(adapter->netdev);
2711
2712 if (hw->mac.type == ixgbe_mac_82598EB)
2713 return;
2714
2715 /* disable the arbiter while setting MTQC */
2716 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2717 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2718 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2719
2720 /* set transmit pool layout */
2721 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2722 case (IXGBE_FLAG_SRIOV_ENABLED):
2723 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2724 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2725 break;
2726 default:
2727 if (!tcs)
2728 reg = IXGBE_MTQC_64Q_1PB;
2729 else if (tcs <= 4)
2730 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2731 else
2732 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2733
2734 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2735
2736 /* Enable Security TX Buffer IFG for multiple pb */
2737 if (tcs) {
2738 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2739 reg |= IXGBE_SECTX_DCB;
2740 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2741 }
2742 break;
2743 }
2744
2745 /* re-enable the arbiter */
2746 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2747 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2748 }
2749
2750 /**
2751 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2752 * @adapter: board private structure
2753 *
2754 * Configure the Tx unit of the MAC after a reset.
2755 **/
ixgbe_configure_tx(struct ixgbe_adapter * adapter)2756 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2757 {
2758 struct ixgbe_hw *hw = &adapter->hw;
2759 u32 dmatxctl;
2760 u32 i;
2761
2762 ixgbe_setup_mtqc(adapter);
2763
2764 if (hw->mac.type != ixgbe_mac_82598EB) {
2765 /* DMATXCTL.EN must be before Tx queues are enabled */
2766 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2767 dmatxctl |= IXGBE_DMATXCTL_TE;
2768 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2769 }
2770
2771 /* Setup the HW Tx Head and Tail descriptor pointers */
2772 for (i = 0; i < adapter->num_tx_queues; i++)
2773 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2774 }
2775
2776 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2777
ixgbe_configure_srrctl(struct ixgbe_adapter * adapter,struct ixgbe_ring * rx_ring)2778 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2779 struct ixgbe_ring *rx_ring)
2780 {
2781 u32 srrctl;
2782 u8 reg_idx = rx_ring->reg_idx;
2783
2784 switch (adapter->hw.mac.type) {
2785 case ixgbe_mac_82598EB: {
2786 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2787 const int mask = feature[RING_F_RSS].mask;
2788 reg_idx = reg_idx & mask;
2789 }
2790 break;
2791 case ixgbe_mac_82599EB:
2792 case ixgbe_mac_X540:
2793 default:
2794 break;
2795 }
2796
2797 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2798
2799 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2800 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2801 if (adapter->num_vfs)
2802 srrctl |= IXGBE_SRRCTL_DROP_EN;
2803
2804 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2805 IXGBE_SRRCTL_BSIZEHDR_MASK;
2806
2807 #if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2808 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2809 #else
2810 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2811 #endif
2812 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2813
2814 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2815 }
2816
ixgbe_setup_mrqc(struct ixgbe_adapter * adapter)2817 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2818 {
2819 struct ixgbe_hw *hw = &adapter->hw;
2820 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2821 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2822 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2823 u32 mrqc = 0, reta = 0;
2824 u32 rxcsum;
2825 int i, j;
2826 u8 tcs = netdev_get_num_tc(adapter->netdev);
2827 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2828
2829 if (tcs)
2830 maxq = min(maxq, adapter->num_tx_queues / tcs);
2831
2832 /* Fill out hash function seeds */
2833 for (i = 0; i < 10; i++)
2834 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2835
2836 /* Fill out redirection table */
2837 for (i = 0, j = 0; i < 128; i++, j++) {
2838 if (j == maxq)
2839 j = 0;
2840 /* reta = 4-byte sliding window of
2841 * 0x00..(indices-1)(indices-1)00..etc. */
2842 reta = (reta << 8) | (j * 0x11);
2843 if ((i & 3) == 3)
2844 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2845 }
2846
2847 /* Disable indicating checksum in descriptor, enables RSS hash */
2848 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2849 rxcsum |= IXGBE_RXCSUM_PCSD;
2850 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2851
2852 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2853 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2854 mrqc = IXGBE_MRQC_RSSEN;
2855 } else {
2856 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2857 | IXGBE_FLAG_SRIOV_ENABLED);
2858
2859 switch (mask) {
2860 case (IXGBE_FLAG_RSS_ENABLED):
2861 if (!tcs)
2862 mrqc = IXGBE_MRQC_RSSEN;
2863 else if (tcs <= 4)
2864 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2865 else
2866 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2867 break;
2868 case (IXGBE_FLAG_SRIOV_ENABLED):
2869 mrqc = IXGBE_MRQC_VMDQEN;
2870 break;
2871 default:
2872 break;
2873 }
2874 }
2875
2876 /* Perform hash on these packet types */
2877 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2878 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2879 | IXGBE_MRQC_RSS_FIELD_IPV6
2880 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2881
2882 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2883 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2884 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2885 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2886
2887 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2888 }
2889
2890 /**
2891 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2892 * @adapter: address of board private structure
2893 * @index: index of ring to set
2894 **/
ixgbe_configure_rscctl(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)2895 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2896 struct ixgbe_ring *ring)
2897 {
2898 struct ixgbe_hw *hw = &adapter->hw;
2899 u32 rscctrl;
2900 u8 reg_idx = ring->reg_idx;
2901
2902 if (!ring_is_rsc_enabled(ring))
2903 return;
2904
2905 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2906 rscctrl |= IXGBE_RSCCTL_RSCEN;
2907 /*
2908 * we must limit the number of descriptors so that the
2909 * total size of max desc * buf_len is not greater
2910 * than 65536
2911 */
2912 #if (PAGE_SIZE <= 8192)
2913 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2914 #elif (PAGE_SIZE <= 16384)
2915 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2916 #else
2917 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2918 #endif
2919 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2920 }
2921
2922 /**
2923 * ixgbe_set_uta - Set unicast filter table address
2924 * @adapter: board private structure
2925 *
2926 * The unicast table address is a register array of 32-bit registers.
2927 * The table is meant to be used in a way similar to how the MTA is used
2928 * however due to certain limitations in the hardware it is necessary to
2929 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2930 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2931 **/
ixgbe_set_uta(struct ixgbe_adapter * adapter)2932 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2933 {
2934 struct ixgbe_hw *hw = &adapter->hw;
2935 int i;
2936
2937 /* The UTA table only exists on 82599 hardware and newer */
2938 if (hw->mac.type < ixgbe_mac_82599EB)
2939 return;
2940
2941 /* we only need to do this if VMDq is enabled */
2942 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2943 return;
2944
2945 for (i = 0; i < 128; i++)
2946 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2947 }
2948
2949 #define IXGBE_MAX_RX_DESC_POLL 10
ixgbe_rx_desc_queue_enable(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)2950 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2951 struct ixgbe_ring *ring)
2952 {
2953 struct ixgbe_hw *hw = &adapter->hw;
2954 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2955 u32 rxdctl;
2956 u8 reg_idx = ring->reg_idx;
2957
2958 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2959 if (hw->mac.type == ixgbe_mac_82598EB &&
2960 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2961 return;
2962
2963 do {
2964 usleep_range(1000, 2000);
2965 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2966 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2967
2968 if (!wait_loop) {
2969 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2970 "the polling period\n", reg_idx);
2971 }
2972 }
2973
ixgbe_disable_rx_queue(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)2974 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2975 struct ixgbe_ring *ring)
2976 {
2977 struct ixgbe_hw *hw = &adapter->hw;
2978 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2979 u32 rxdctl;
2980 u8 reg_idx = ring->reg_idx;
2981
2982 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2983 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2984
2985 /* write value back with RXDCTL.ENABLE bit cleared */
2986 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2987
2988 if (hw->mac.type == ixgbe_mac_82598EB &&
2989 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2990 return;
2991
2992 /* the hardware may take up to 100us to really disable the rx queue */
2993 do {
2994 udelay(10);
2995 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2996 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2997
2998 if (!wait_loop) {
2999 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3000 "the polling period\n", reg_idx);
3001 }
3002 }
3003
ixgbe_configure_rx_ring(struct ixgbe_adapter * adapter,struct ixgbe_ring * ring)3004 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3005 struct ixgbe_ring *ring)
3006 {
3007 struct ixgbe_hw *hw = &adapter->hw;
3008 u64 rdba = ring->dma;
3009 u32 rxdctl;
3010 u8 reg_idx = ring->reg_idx;
3011
3012 /* disable queue to avoid issues while updating state */
3013 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3014 ixgbe_disable_rx_queue(adapter, ring);
3015
3016 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3017 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3018 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3019 ring->count * sizeof(union ixgbe_adv_rx_desc));
3020 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3021 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3022 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3023
3024 ixgbe_configure_srrctl(adapter, ring);
3025 ixgbe_configure_rscctl(adapter, ring);
3026
3027 /* If operating in IOV mode set RLPML for X540 */
3028 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3029 hw->mac.type == ixgbe_mac_X540) {
3030 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3031 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3032 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3033 }
3034
3035 if (hw->mac.type == ixgbe_mac_82598EB) {
3036 /*
3037 * enable cache line friendly hardware writes:
3038 * PTHRESH=32 descriptors (half the internal cache),
3039 * this also removes ugly rx_no_buffer_count increment
3040 * HTHRESH=4 descriptors (to minimize latency on fetch)
3041 * WTHRESH=8 burst writeback up to two cache lines
3042 */
3043 rxdctl &= ~0x3FFFFF;
3044 rxdctl |= 0x080420;
3045 }
3046
3047 /* enable receive descriptor ring */
3048 rxdctl |= IXGBE_RXDCTL_ENABLE;
3049 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3050
3051 ixgbe_rx_desc_queue_enable(adapter, ring);
3052 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3053 }
3054
ixgbe_setup_psrtype(struct ixgbe_adapter * adapter)3055 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3056 {
3057 struct ixgbe_hw *hw = &adapter->hw;
3058 int p;
3059
3060 /* PSRTYPE must be initialized in non 82598 adapters */
3061 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3062 IXGBE_PSRTYPE_UDPHDR |
3063 IXGBE_PSRTYPE_IPV4HDR |
3064 IXGBE_PSRTYPE_L2HDR |
3065 IXGBE_PSRTYPE_IPV6HDR;
3066
3067 if (hw->mac.type == ixgbe_mac_82598EB)
3068 return;
3069
3070 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3071 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3072
3073 for (p = 0; p < adapter->num_rx_pools; p++)
3074 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3075 psrtype);
3076 }
3077
ixgbe_configure_virtualization(struct ixgbe_adapter * adapter)3078 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3079 {
3080 struct ixgbe_hw *hw = &adapter->hw;
3081 u32 gcr_ext;
3082 u32 vt_reg_bits;
3083 u32 reg_offset, vf_shift;
3084 u32 vmdctl;
3085 int i;
3086
3087 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3088 return;
3089
3090 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3091 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3092 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3093 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3094
3095 vf_shift = adapter->num_vfs % 32;
3096 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3097
3098 /* Enable only the PF's pool for Tx/Rx */
3099 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3100 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3101 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3102 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3103 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3104
3105 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3106 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3107
3108 /*
3109 * Set up VF register offsets for selected VT Mode,
3110 * i.e. 32 or 64 VFs for SR-IOV
3111 */
3112 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3113 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3114 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3115 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3116
3117 /* enable Tx loopback for VF/PF communication */
3118 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3119 /* Enable MAC Anti-Spoofing */
3120 hw->mac.ops.set_mac_anti_spoofing(hw,
3121 (adapter->num_vfs != 0),
3122 adapter->num_vfs);
3123 /* For VFs that have spoof checking turned off */
3124 for (i = 0; i < adapter->num_vfs; i++) {
3125 if (!adapter->vfinfo[i].spoofchk_enabled)
3126 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3127 }
3128 }
3129
ixgbe_set_rx_buffer_len(struct ixgbe_adapter * adapter)3130 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3131 {
3132 struct ixgbe_hw *hw = &adapter->hw;
3133 struct net_device *netdev = adapter->netdev;
3134 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3135 struct ixgbe_ring *rx_ring;
3136 int i;
3137 u32 mhadd, hlreg0;
3138
3139 #ifdef IXGBE_FCOE
3140 /* adjust max frame to be able to do baby jumbo for FCoE */
3141 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3142 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3143 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3144
3145 #endif /* IXGBE_FCOE */
3146 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3147 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3148 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3149 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3150
3151 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3152 }
3153
3154 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3155 max_frame += VLAN_HLEN;
3156
3157 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3158 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3159 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3160 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3161
3162 /*
3163 * Setup the HW Rx Head and Tail Descriptor Pointers and
3164 * the Base and Length of the Rx Descriptor Ring
3165 */
3166 for (i = 0; i < adapter->num_rx_queues; i++) {
3167 rx_ring = adapter->rx_ring[i];
3168 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3169 set_ring_rsc_enabled(rx_ring);
3170 else
3171 clear_ring_rsc_enabled(rx_ring);
3172 }
3173 }
3174
ixgbe_setup_rdrxctl(struct ixgbe_adapter * adapter)3175 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3176 {
3177 struct ixgbe_hw *hw = &adapter->hw;
3178 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3179
3180 switch (hw->mac.type) {
3181 case ixgbe_mac_82598EB:
3182 /*
3183 * For VMDq support of different descriptor types or
3184 * buffer sizes through the use of multiple SRRCTL
3185 * registers, RDRXCTL.MVMEN must be set to 1
3186 *
3187 * also, the manual doesn't mention it clearly but DCA hints
3188 * will only use queue 0's tags unless this bit is set. Side
3189 * effects of setting this bit are only that SRRCTL must be
3190 * fully programmed [0..15]
3191 */
3192 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3193 break;
3194 case ixgbe_mac_82599EB:
3195 case ixgbe_mac_X540:
3196 /* Disable RSC for ACK packets */
3197 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3198 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3199 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3200 /* hardware requires some bits to be set by default */
3201 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3202 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3203 break;
3204 default:
3205 /* We should do nothing since we don't know this hardware */
3206 return;
3207 }
3208
3209 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3210 }
3211
3212 /**
3213 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3214 * @adapter: board private structure
3215 *
3216 * Configure the Rx unit of the MAC after a reset.
3217 **/
ixgbe_configure_rx(struct ixgbe_adapter * adapter)3218 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3219 {
3220 struct ixgbe_hw *hw = &adapter->hw;
3221 int i;
3222 u32 rxctrl;
3223
3224 /* disable receives while setting up the descriptors */
3225 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3226 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3227
3228 ixgbe_setup_psrtype(adapter);
3229 ixgbe_setup_rdrxctl(adapter);
3230
3231 /* Program registers for the distribution of queues */
3232 ixgbe_setup_mrqc(adapter);
3233
3234 ixgbe_set_uta(adapter);
3235
3236 /* set_rx_buffer_len must be called before ring initialization */
3237 ixgbe_set_rx_buffer_len(adapter);
3238
3239 /*
3240 * Setup the HW Rx Head and Tail Descriptor Pointers and
3241 * the Base and Length of the Rx Descriptor Ring
3242 */
3243 for (i = 0; i < adapter->num_rx_queues; i++)
3244 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3245
3246 /* disable drop enable for 82598 parts */
3247 if (hw->mac.type == ixgbe_mac_82598EB)
3248 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3249
3250 /* enable all receives */
3251 rxctrl |= IXGBE_RXCTRL_RXEN;
3252 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3253 }
3254
ixgbe_vlan_rx_add_vid(struct net_device * netdev,u16 vid)3255 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3256 {
3257 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3258 struct ixgbe_hw *hw = &adapter->hw;
3259 int pool_ndx = adapter->num_vfs;
3260
3261 /* add VID to filter table */
3262 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3263 set_bit(vid, adapter->active_vlans);
3264
3265 return 0;
3266 }
3267
ixgbe_vlan_rx_kill_vid(struct net_device * netdev,u16 vid)3268 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3269 {
3270 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3271 struct ixgbe_hw *hw = &adapter->hw;
3272 int pool_ndx = adapter->num_vfs;
3273
3274 /* remove VID from filter table */
3275 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3276 clear_bit(vid, adapter->active_vlans);
3277
3278 return 0;
3279 }
3280
3281 /**
3282 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3283 * @adapter: driver data
3284 */
ixgbe_vlan_filter_disable(struct ixgbe_adapter * adapter)3285 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3286 {
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 u32 vlnctrl;
3289
3290 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3291 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3292 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3293 }
3294
3295 /**
3296 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3297 * @adapter: driver data
3298 */
ixgbe_vlan_filter_enable(struct ixgbe_adapter * adapter)3299 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3300 {
3301 struct ixgbe_hw *hw = &adapter->hw;
3302 u32 vlnctrl;
3303
3304 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3305 vlnctrl |= IXGBE_VLNCTRL_VFE;
3306 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3307 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3308 }
3309
3310 /**
3311 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3312 * @adapter: driver data
3313 */
ixgbe_vlan_strip_disable(struct ixgbe_adapter * adapter)3314 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3315 {
3316 struct ixgbe_hw *hw = &adapter->hw;
3317 u32 vlnctrl;
3318 int i, j;
3319
3320 switch (hw->mac.type) {
3321 case ixgbe_mac_82598EB:
3322 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3323 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3324 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3325 break;
3326 case ixgbe_mac_82599EB:
3327 case ixgbe_mac_X540:
3328 for (i = 0; i < adapter->num_rx_queues; i++) {
3329 j = adapter->rx_ring[i]->reg_idx;
3330 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3331 vlnctrl &= ~IXGBE_RXDCTL_VME;
3332 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3333 }
3334 break;
3335 default:
3336 break;
3337 }
3338 }
3339
3340 /**
3341 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3342 * @adapter: driver data
3343 */
ixgbe_vlan_strip_enable(struct ixgbe_adapter * adapter)3344 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3345 {
3346 struct ixgbe_hw *hw = &adapter->hw;
3347 u32 vlnctrl;
3348 int i, j;
3349
3350 switch (hw->mac.type) {
3351 case ixgbe_mac_82598EB:
3352 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3353 vlnctrl |= IXGBE_VLNCTRL_VME;
3354 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3355 break;
3356 case ixgbe_mac_82599EB:
3357 case ixgbe_mac_X540:
3358 for (i = 0; i < adapter->num_rx_queues; i++) {
3359 j = adapter->rx_ring[i]->reg_idx;
3360 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3361 vlnctrl |= IXGBE_RXDCTL_VME;
3362 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3363 }
3364 break;
3365 default:
3366 break;
3367 }
3368 }
3369
ixgbe_restore_vlan(struct ixgbe_adapter * adapter)3370 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3371 {
3372 u16 vid;
3373
3374 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3375
3376 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3377 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3378 }
3379
3380 /**
3381 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3382 * @netdev: network interface device structure
3383 *
3384 * Writes unicast address list to the RAR table.
3385 * Returns: -ENOMEM on failure/insufficient address space
3386 * 0 on no addresses written
3387 * X on writing X addresses to the RAR table
3388 **/
ixgbe_write_uc_addr_list(struct net_device * netdev)3389 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3390 {
3391 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3392 struct ixgbe_hw *hw = &adapter->hw;
3393 unsigned int vfn = adapter->num_vfs;
3394 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3395 int count = 0;
3396
3397 /* return ENOMEM indicating insufficient memory for addresses */
3398 if (netdev_uc_count(netdev) > rar_entries)
3399 return -ENOMEM;
3400
3401 if (!netdev_uc_empty(netdev) && rar_entries) {
3402 struct netdev_hw_addr *ha;
3403 /* return error if we do not support writing to RAR table */
3404 if (!hw->mac.ops.set_rar)
3405 return -ENOMEM;
3406
3407 netdev_for_each_uc_addr(ha, netdev) {
3408 if (!rar_entries)
3409 break;
3410 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3411 vfn, IXGBE_RAH_AV);
3412 count++;
3413 }
3414 }
3415 /* write the addresses in reverse order to avoid write combining */
3416 for (; rar_entries > 0 ; rar_entries--)
3417 hw->mac.ops.clear_rar(hw, rar_entries);
3418
3419 return count;
3420 }
3421
3422 /**
3423 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3424 * @netdev: network interface device structure
3425 *
3426 * The set_rx_method entry point is called whenever the unicast/multicast
3427 * address list or the network interface flags are updated. This routine is
3428 * responsible for configuring the hardware for proper unicast, multicast and
3429 * promiscuous mode.
3430 **/
ixgbe_set_rx_mode(struct net_device * netdev)3431 void ixgbe_set_rx_mode(struct net_device *netdev)
3432 {
3433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3434 struct ixgbe_hw *hw = &adapter->hw;
3435 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3436 int count;
3437
3438 /* Check for Promiscuous and All Multicast modes */
3439
3440 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3441
3442 /* set all bits that we expect to always be set */
3443 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3444 fctrl |= IXGBE_FCTRL_BAM;
3445 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3446 fctrl |= IXGBE_FCTRL_PMCF;
3447
3448 /* clear the bits we are changing the status of */
3449 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3450
3451 if (netdev->flags & IFF_PROMISC) {
3452 hw->addr_ctrl.user_set_promisc = true;
3453 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3454 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3455 /* don't hardware filter vlans in promisc mode */
3456 ixgbe_vlan_filter_disable(adapter);
3457 } else {
3458 if (netdev->flags & IFF_ALLMULTI) {
3459 fctrl |= IXGBE_FCTRL_MPE;
3460 vmolr |= IXGBE_VMOLR_MPE;
3461 } else {
3462 /*
3463 * Write addresses to the MTA, if the attempt fails
3464 * then we should just turn on promiscuous mode so
3465 * that we can at least receive multicast traffic
3466 */
3467 hw->mac.ops.update_mc_addr_list(hw, netdev);
3468 vmolr |= IXGBE_VMOLR_ROMPE;
3469 }
3470 ixgbe_vlan_filter_enable(adapter);
3471 hw->addr_ctrl.user_set_promisc = false;
3472 /*
3473 * Write addresses to available RAR registers, if there is not
3474 * sufficient space to store all the addresses then enable
3475 * unicast promiscuous mode
3476 */
3477 count = ixgbe_write_uc_addr_list(netdev);
3478 if (count < 0) {
3479 fctrl |= IXGBE_FCTRL_UPE;
3480 vmolr |= IXGBE_VMOLR_ROPE;
3481 }
3482 }
3483
3484 if (adapter->num_vfs) {
3485 ixgbe_restore_vf_multicasts(adapter);
3486 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3487 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3488 IXGBE_VMOLR_ROPE);
3489 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3490 }
3491
3492 /* This is useful for sniffing bad packets. */
3493 if (adapter->netdev->features & NETIF_F_RXALL) {
3494 /* UPE and MPE will be handled by normal PROMISC logic
3495 * in e1000e_set_rx_mode */
3496 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3497 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3498 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3499
3500 fctrl &= ~(IXGBE_FCTRL_DPF);
3501 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3502 }
3503
3504 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3505
3506 if (netdev->features & NETIF_F_HW_VLAN_RX)
3507 ixgbe_vlan_strip_enable(adapter);
3508 else
3509 ixgbe_vlan_strip_disable(adapter);
3510 }
3511
ixgbe_napi_enable_all(struct ixgbe_adapter * adapter)3512 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3513 {
3514 int q_idx;
3515 struct ixgbe_q_vector *q_vector;
3516 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3517
3518 /* legacy and MSI only use one vector */
3519 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3520 q_vectors = 1;
3521
3522 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3523 q_vector = adapter->q_vector[q_idx];
3524 napi_enable(&q_vector->napi);
3525 }
3526 }
3527
ixgbe_napi_disable_all(struct ixgbe_adapter * adapter)3528 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3529 {
3530 int q_idx;
3531 struct ixgbe_q_vector *q_vector;
3532 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3533
3534 /* legacy and MSI only use one vector */
3535 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3536 q_vectors = 1;
3537
3538 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3539 q_vector = adapter->q_vector[q_idx];
3540 napi_disable(&q_vector->napi);
3541 }
3542 }
3543
3544 #ifdef CONFIG_IXGBE_DCB
3545 /*
3546 * ixgbe_configure_dcb - Configure DCB hardware
3547 * @adapter: ixgbe adapter struct
3548 *
3549 * This is called by the driver on open to configure the DCB hardware.
3550 * This is also called by the gennetlink interface when reconfiguring
3551 * the DCB state.
3552 */
ixgbe_configure_dcb(struct ixgbe_adapter * adapter)3553 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3554 {
3555 struct ixgbe_hw *hw = &adapter->hw;
3556 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3557
3558 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3559 if (hw->mac.type == ixgbe_mac_82598EB)
3560 netif_set_gso_max_size(adapter->netdev, 65536);
3561 return;
3562 }
3563
3564 if (hw->mac.type == ixgbe_mac_82598EB)
3565 netif_set_gso_max_size(adapter->netdev, 32768);
3566
3567
3568 /* Enable VLAN tag insert/strip */
3569 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3570
3571 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3572
3573 #ifdef IXGBE_FCOE
3574 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3575 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3576 #endif
3577
3578 /* reconfigure the hardware */
3579 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3580 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3581 DCB_TX_CONFIG);
3582 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3583 DCB_RX_CONFIG);
3584 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3585 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3586 ixgbe_dcb_hw_ets(&adapter->hw,
3587 adapter->ixgbe_ieee_ets,
3588 max_frame);
3589 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3590 adapter->ixgbe_ieee_pfc->pfc_en,
3591 adapter->ixgbe_ieee_ets->prio_tc);
3592 }
3593
3594 /* Enable RSS Hash per TC */
3595 if (hw->mac.type != ixgbe_mac_82598EB) {
3596 int i;
3597 u32 reg = 0;
3598
3599 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3600 u8 msb = 0;
3601 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3602
3603 while (cnt >>= 1)
3604 msb++;
3605
3606 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3607 }
3608 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3609 }
3610 }
3611 #endif
3612
3613 /* Additional bittime to account for IXGBE framing */
3614 #define IXGBE_ETH_FRAMING 20
3615
3616 /*
3617 * ixgbe_hpbthresh - calculate high water mark for flow control
3618 *
3619 * @adapter: board private structure to calculate for
3620 * @pb - packet buffer to calculate
3621 */
ixgbe_hpbthresh(struct ixgbe_adapter * adapter,int pb)3622 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3623 {
3624 struct ixgbe_hw *hw = &adapter->hw;
3625 struct net_device *dev = adapter->netdev;
3626 int link, tc, kb, marker;
3627 u32 dv_id, rx_pba;
3628
3629 /* Calculate max LAN frame size */
3630 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3631
3632 #ifdef IXGBE_FCOE
3633 /* FCoE traffic class uses FCOE jumbo frames */
3634 if (dev->features & NETIF_F_FCOE_MTU) {
3635 int fcoe_pb = 0;
3636
3637 #ifdef CONFIG_IXGBE_DCB
3638 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3639
3640 #endif
3641 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3642 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3643 }
3644 #endif
3645
3646 /* Calculate delay value for device */
3647 switch (hw->mac.type) {
3648 case ixgbe_mac_X540:
3649 dv_id = IXGBE_DV_X540(link, tc);
3650 break;
3651 default:
3652 dv_id = IXGBE_DV(link, tc);
3653 break;
3654 }
3655
3656 /* Loopback switch introduces additional latency */
3657 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3658 dv_id += IXGBE_B2BT(tc);
3659
3660 /* Delay value is calculated in bit times convert to KB */
3661 kb = IXGBE_BT2KB(dv_id);
3662 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3663
3664 marker = rx_pba - kb;
3665
3666 /* It is possible that the packet buffer is not large enough
3667 * to provide required headroom. In this case throw an error
3668 * to user and a do the best we can.
3669 */
3670 if (marker < 0) {
3671 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3672 "headroom to support flow control."
3673 "Decrease MTU or number of traffic classes\n", pb);
3674 marker = tc + 1;
3675 }
3676
3677 return marker;
3678 }
3679
3680 /*
3681 * ixgbe_lpbthresh - calculate low water mark for for flow control
3682 *
3683 * @adapter: board private structure to calculate for
3684 * @pb - packet buffer to calculate
3685 */
ixgbe_lpbthresh(struct ixgbe_adapter * adapter)3686 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3687 {
3688 struct ixgbe_hw *hw = &adapter->hw;
3689 struct net_device *dev = adapter->netdev;
3690 int tc;
3691 u32 dv_id;
3692
3693 /* Calculate max LAN frame size */
3694 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3695
3696 /* Calculate delay value for device */
3697 switch (hw->mac.type) {
3698 case ixgbe_mac_X540:
3699 dv_id = IXGBE_LOW_DV_X540(tc);
3700 break;
3701 default:
3702 dv_id = IXGBE_LOW_DV(tc);
3703 break;
3704 }
3705
3706 /* Delay value is calculated in bit times convert to KB */
3707 return IXGBE_BT2KB(dv_id);
3708 }
3709
3710 /*
3711 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3712 */
ixgbe_pbthresh_setup(struct ixgbe_adapter * adapter)3713 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3714 {
3715 struct ixgbe_hw *hw = &adapter->hw;
3716 int num_tc = netdev_get_num_tc(adapter->netdev);
3717 int i;
3718
3719 if (!num_tc)
3720 num_tc = 1;
3721
3722 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3723
3724 for (i = 0; i < num_tc; i++) {
3725 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3726
3727 /* Low water marks must not be larger than high water marks */
3728 if (hw->fc.low_water > hw->fc.high_water[i])
3729 hw->fc.low_water = 0;
3730 }
3731 }
3732
ixgbe_configure_pb(struct ixgbe_adapter * adapter)3733 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3734 {
3735 struct ixgbe_hw *hw = &adapter->hw;
3736 int hdrm;
3737 u8 tc = netdev_get_num_tc(adapter->netdev);
3738
3739 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3740 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3741 hdrm = 32 << adapter->fdir_pballoc;
3742 else
3743 hdrm = 0;
3744
3745 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3746 ixgbe_pbthresh_setup(adapter);
3747 }
3748
ixgbe_fdir_filter_restore(struct ixgbe_adapter * adapter)3749 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3750 {
3751 struct ixgbe_hw *hw = &adapter->hw;
3752 struct hlist_node *node, *node2;
3753 struct ixgbe_fdir_filter *filter;
3754
3755 spin_lock(&adapter->fdir_perfect_lock);
3756
3757 if (!hlist_empty(&adapter->fdir_filter_list))
3758 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3759
3760 hlist_for_each_entry_safe(filter, node, node2,
3761 &adapter->fdir_filter_list, fdir_node) {
3762 ixgbe_fdir_write_perfect_filter_82599(hw,
3763 &filter->filter,
3764 filter->sw_idx,
3765 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3766 IXGBE_FDIR_DROP_QUEUE :
3767 adapter->rx_ring[filter->action]->reg_idx);
3768 }
3769
3770 spin_unlock(&adapter->fdir_perfect_lock);
3771 }
3772
ixgbe_configure(struct ixgbe_adapter * adapter)3773 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3774 {
3775 struct ixgbe_hw *hw = &adapter->hw;
3776
3777 ixgbe_configure_pb(adapter);
3778 #ifdef CONFIG_IXGBE_DCB
3779 ixgbe_configure_dcb(adapter);
3780 #endif
3781
3782 ixgbe_set_rx_mode(adapter->netdev);
3783 ixgbe_restore_vlan(adapter);
3784
3785 #ifdef IXGBE_FCOE
3786 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3787 ixgbe_configure_fcoe(adapter);
3788
3789 #endif /* IXGBE_FCOE */
3790
3791 switch (hw->mac.type) {
3792 case ixgbe_mac_82599EB:
3793 case ixgbe_mac_X540:
3794 hw->mac.ops.disable_rx_buff(hw);
3795 break;
3796 default:
3797 break;
3798 }
3799
3800 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3801 ixgbe_init_fdir_signature_82599(&adapter->hw,
3802 adapter->fdir_pballoc);
3803 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3804 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3805 adapter->fdir_pballoc);
3806 ixgbe_fdir_filter_restore(adapter);
3807 }
3808
3809 switch (hw->mac.type) {
3810 case ixgbe_mac_82599EB:
3811 case ixgbe_mac_X540:
3812 hw->mac.ops.enable_rx_buff(hw);
3813 break;
3814 default:
3815 break;
3816 }
3817
3818 ixgbe_configure_virtualization(adapter);
3819
3820 ixgbe_configure_tx(adapter);
3821 ixgbe_configure_rx(adapter);
3822 }
3823
ixgbe_is_sfp(struct ixgbe_hw * hw)3824 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3825 {
3826 switch (hw->phy.type) {
3827 case ixgbe_phy_sfp_avago:
3828 case ixgbe_phy_sfp_ftl:
3829 case ixgbe_phy_sfp_intel:
3830 case ixgbe_phy_sfp_unknown:
3831 case ixgbe_phy_sfp_passive_tyco:
3832 case ixgbe_phy_sfp_passive_unknown:
3833 case ixgbe_phy_sfp_active_unknown:
3834 case ixgbe_phy_sfp_ftl_active:
3835 return true;
3836 case ixgbe_phy_nl:
3837 if (hw->mac.type == ixgbe_mac_82598EB)
3838 return true;
3839 default:
3840 return false;
3841 }
3842 }
3843
3844 /**
3845 * ixgbe_sfp_link_config - set up SFP+ link
3846 * @adapter: pointer to private adapter struct
3847 **/
ixgbe_sfp_link_config(struct ixgbe_adapter * adapter)3848 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3849 {
3850 /*
3851 * We are assuming the worst case scenario here, and that
3852 * is that an SFP was inserted/removed after the reset
3853 * but before SFP detection was enabled. As such the best
3854 * solution is to just start searching as soon as we start
3855 */
3856 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3857 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3858
3859 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3860 }
3861
3862 /**
3863 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3864 * @hw: pointer to private hardware struct
3865 *
3866 * Returns 0 on success, negative on failure
3867 **/
ixgbe_non_sfp_link_config(struct ixgbe_hw * hw)3868 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3869 {
3870 u32 autoneg;
3871 bool negotiation, link_up = false;
3872 u32 ret = IXGBE_ERR_LINK_SETUP;
3873
3874 if (hw->mac.ops.check_link)
3875 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3876
3877 if (ret)
3878 goto link_cfg_out;
3879
3880 autoneg = hw->phy.autoneg_advertised;
3881 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3882 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3883 &negotiation);
3884 if (ret)
3885 goto link_cfg_out;
3886
3887 if (hw->mac.ops.setup_link)
3888 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3889 link_cfg_out:
3890 return ret;
3891 }
3892
ixgbe_setup_gpie(struct ixgbe_adapter * adapter)3893 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3894 {
3895 struct ixgbe_hw *hw = &adapter->hw;
3896 u32 gpie = 0;
3897
3898 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3899 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3900 IXGBE_GPIE_OCD;
3901 gpie |= IXGBE_GPIE_EIAME;
3902 /*
3903 * use EIAM to auto-mask when MSI-X interrupt is asserted
3904 * this saves a register write for every interrupt
3905 */
3906 switch (hw->mac.type) {
3907 case ixgbe_mac_82598EB:
3908 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3909 break;
3910 case ixgbe_mac_82599EB:
3911 case ixgbe_mac_X540:
3912 default:
3913 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3914 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3915 break;
3916 }
3917 } else {
3918 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3919 * specifically only auto mask tx and rx interrupts */
3920 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3921 }
3922
3923 /* XXX: to interrupt immediately for EICS writes, enable this */
3924 /* gpie |= IXGBE_GPIE_EIMEN; */
3925
3926 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3927 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3928 gpie |= IXGBE_GPIE_VTMODE_64;
3929 }
3930
3931 /* Enable Thermal over heat sensor interrupt */
3932 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3933 switch (adapter->hw.mac.type) {
3934 case ixgbe_mac_82599EB:
3935 gpie |= IXGBE_SDP0_GPIEN;
3936 break;
3937 case ixgbe_mac_X540:
3938 gpie |= IXGBE_EIMS_TS;
3939 break;
3940 default:
3941 break;
3942 }
3943 }
3944
3945 /* Enable fan failure interrupt */
3946 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3947 gpie |= IXGBE_SDP1_GPIEN;
3948
3949 if (hw->mac.type == ixgbe_mac_82599EB) {
3950 gpie |= IXGBE_SDP1_GPIEN;
3951 gpie |= IXGBE_SDP2_GPIEN;
3952 }
3953
3954 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3955 }
3956
ixgbe_up_complete(struct ixgbe_adapter * adapter)3957 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3958 {
3959 struct ixgbe_hw *hw = &adapter->hw;
3960 int err;
3961 u32 ctrl_ext;
3962
3963 ixgbe_get_hw_control(adapter);
3964 ixgbe_setup_gpie(adapter);
3965
3966 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3967 ixgbe_configure_msix(adapter);
3968 else
3969 ixgbe_configure_msi_and_legacy(adapter);
3970
3971 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3972 if (hw->mac.ops.enable_tx_laser &&
3973 ((hw->phy.multispeed_fiber) ||
3974 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3975 (hw->mac.type == ixgbe_mac_82599EB))))
3976 hw->mac.ops.enable_tx_laser(hw);
3977
3978 clear_bit(__IXGBE_DOWN, &adapter->state);
3979 ixgbe_napi_enable_all(adapter);
3980
3981 if (ixgbe_is_sfp(hw)) {
3982 ixgbe_sfp_link_config(adapter);
3983 } else {
3984 err = ixgbe_non_sfp_link_config(hw);
3985 if (err)
3986 e_err(probe, "link_config FAILED %d\n", err);
3987 }
3988
3989 /* clear any pending interrupts, may auto mask */
3990 IXGBE_READ_REG(hw, IXGBE_EICR);
3991 ixgbe_irq_enable(adapter, true, true);
3992
3993 /*
3994 * If this adapter has a fan, check to see if we had a failure
3995 * before we enabled the interrupt.
3996 */
3997 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3998 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3999 if (esdp & IXGBE_ESDP_SDP1)
4000 e_crit(drv, "Fan has stopped, replace the adapter\n");
4001 }
4002
4003 /* enable transmits */
4004 netif_tx_start_all_queues(adapter->netdev);
4005
4006 /* bring the link up in the watchdog, this could race with our first
4007 * link up interrupt but shouldn't be a problem */
4008 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4009 adapter->link_check_timeout = jiffies;
4010 mod_timer(&adapter->service_timer, jiffies);
4011
4012 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4013 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4014 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4015 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4016 }
4017
ixgbe_reinit_locked(struct ixgbe_adapter * adapter)4018 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4019 {
4020 WARN_ON(in_interrupt());
4021 /* put off any impending NetWatchDogTimeout */
4022 adapter->netdev->trans_start = jiffies;
4023
4024 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4025 usleep_range(1000, 2000);
4026 ixgbe_down(adapter);
4027 /*
4028 * If SR-IOV enabled then wait a bit before bringing the adapter
4029 * back up to give the VFs time to respond to the reset. The
4030 * two second wait is based upon the watchdog timer cycle in
4031 * the VF driver.
4032 */
4033 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4034 msleep(2000);
4035 ixgbe_up(adapter);
4036 clear_bit(__IXGBE_RESETTING, &adapter->state);
4037 }
4038
ixgbe_up(struct ixgbe_adapter * adapter)4039 void ixgbe_up(struct ixgbe_adapter *adapter)
4040 {
4041 /* hardware has been reset, we need to reload some things */
4042 ixgbe_configure(adapter);
4043
4044 ixgbe_up_complete(adapter);
4045 }
4046
ixgbe_reset(struct ixgbe_adapter * adapter)4047 void ixgbe_reset(struct ixgbe_adapter *adapter)
4048 {
4049 struct ixgbe_hw *hw = &adapter->hw;
4050 int err;
4051
4052 /* lock SFP init bit to prevent race conditions with the watchdog */
4053 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4054 usleep_range(1000, 2000);
4055
4056 /* clear all SFP and link config related flags while holding SFP_INIT */
4057 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4058 IXGBE_FLAG2_SFP_NEEDS_RESET);
4059 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4060
4061 err = hw->mac.ops.init_hw(hw);
4062 switch (err) {
4063 case 0:
4064 case IXGBE_ERR_SFP_NOT_PRESENT:
4065 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4066 break;
4067 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4068 e_dev_err("master disable timed out\n");
4069 break;
4070 case IXGBE_ERR_EEPROM_VERSION:
4071 /* We are running on a pre-production device, log a warning */
4072 e_dev_warn("This device is a pre-production adapter/LOM. "
4073 "Please be aware there may be issues associated with "
4074 "your hardware. If you are experiencing problems "
4075 "please contact your Intel or hardware "
4076 "representative who provided you with this "
4077 "hardware.\n");
4078 break;
4079 default:
4080 e_dev_err("Hardware Error: %d\n", err);
4081 }
4082
4083 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4084
4085 /* reprogram the RAR[0] in case user changed it. */
4086 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4087 IXGBE_RAH_AV);
4088 }
4089
4090 /**
4091 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4092 * @rx_ring: ring to setup
4093 *
4094 * On many IA platforms the L1 cache has a critical stride of 4K, this
4095 * results in each receive buffer starting in the same cache set. To help
4096 * reduce the pressure on this cache set we can interleave the offsets so
4097 * that only every other buffer will be in the same cache set.
4098 **/
ixgbe_init_rx_page_offset(struct ixgbe_ring * rx_ring)4099 static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4100 {
4101 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4102 u16 i;
4103
4104 for (i = 0; i < rx_ring->count; i += 2) {
4105 rx_buffer[0].page_offset = 0;
4106 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4107 rx_buffer = &rx_buffer[2];
4108 }
4109 }
4110
4111 /**
4112 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4113 * @rx_ring: ring to free buffers from
4114 **/
ixgbe_clean_rx_ring(struct ixgbe_ring * rx_ring)4115 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4116 {
4117 struct device *dev = rx_ring->dev;
4118 unsigned long size;
4119 u16 i;
4120
4121 /* ring already cleared, nothing to do */
4122 if (!rx_ring->rx_buffer_info)
4123 return;
4124
4125 /* Free all the Rx ring sk_buffs */
4126 for (i = 0; i < rx_ring->count; i++) {
4127 struct ixgbe_rx_buffer *rx_buffer;
4128
4129 rx_buffer = &rx_ring->rx_buffer_info[i];
4130 if (rx_buffer->skb) {
4131 struct sk_buff *skb = rx_buffer->skb;
4132 if (IXGBE_CB(skb)->page_released) {
4133 dma_unmap_page(dev,
4134 IXGBE_CB(skb)->dma,
4135 ixgbe_rx_bufsz(rx_ring),
4136 DMA_FROM_DEVICE);
4137 IXGBE_CB(skb)->page_released = false;
4138 }
4139 dev_kfree_skb(skb);
4140 }
4141 rx_buffer->skb = NULL;
4142 if (rx_buffer->dma)
4143 dma_unmap_page(dev, rx_buffer->dma,
4144 ixgbe_rx_pg_size(rx_ring),
4145 DMA_FROM_DEVICE);
4146 rx_buffer->dma = 0;
4147 if (rx_buffer->page)
4148 put_page(rx_buffer->page);
4149 rx_buffer->page = NULL;
4150 }
4151
4152 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4153 memset(rx_ring->rx_buffer_info, 0, size);
4154
4155 ixgbe_init_rx_page_offset(rx_ring);
4156
4157 /* Zero out the descriptor ring */
4158 memset(rx_ring->desc, 0, rx_ring->size);
4159
4160 rx_ring->next_to_alloc = 0;
4161 rx_ring->next_to_clean = 0;
4162 rx_ring->next_to_use = 0;
4163 }
4164
4165 /**
4166 * ixgbe_clean_tx_ring - Free Tx Buffers
4167 * @tx_ring: ring to be cleaned
4168 **/
ixgbe_clean_tx_ring(struct ixgbe_ring * tx_ring)4169 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4170 {
4171 struct ixgbe_tx_buffer *tx_buffer_info;
4172 unsigned long size;
4173 u16 i;
4174
4175 /* ring already cleared, nothing to do */
4176 if (!tx_ring->tx_buffer_info)
4177 return;
4178
4179 /* Free all the Tx ring sk_buffs */
4180 for (i = 0; i < tx_ring->count; i++) {
4181 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4182 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4183 }
4184
4185 netdev_tx_reset_queue(txring_txq(tx_ring));
4186
4187 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4188 memset(tx_ring->tx_buffer_info, 0, size);
4189
4190 /* Zero out the descriptor ring */
4191 memset(tx_ring->desc, 0, tx_ring->size);
4192
4193 tx_ring->next_to_use = 0;
4194 tx_ring->next_to_clean = 0;
4195 }
4196
4197 /**
4198 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4199 * @adapter: board private structure
4200 **/
ixgbe_clean_all_rx_rings(struct ixgbe_adapter * adapter)4201 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4202 {
4203 int i;
4204
4205 for (i = 0; i < adapter->num_rx_queues; i++)
4206 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4207 }
4208
4209 /**
4210 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4211 * @adapter: board private structure
4212 **/
ixgbe_clean_all_tx_rings(struct ixgbe_adapter * adapter)4213 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4214 {
4215 int i;
4216
4217 for (i = 0; i < adapter->num_tx_queues; i++)
4218 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4219 }
4220
ixgbe_fdir_filter_exit(struct ixgbe_adapter * adapter)4221 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4222 {
4223 struct hlist_node *node, *node2;
4224 struct ixgbe_fdir_filter *filter;
4225
4226 spin_lock(&adapter->fdir_perfect_lock);
4227
4228 hlist_for_each_entry_safe(filter, node, node2,
4229 &adapter->fdir_filter_list, fdir_node) {
4230 hlist_del(&filter->fdir_node);
4231 kfree(filter);
4232 }
4233 adapter->fdir_filter_count = 0;
4234
4235 spin_unlock(&adapter->fdir_perfect_lock);
4236 }
4237
ixgbe_down(struct ixgbe_adapter * adapter)4238 void ixgbe_down(struct ixgbe_adapter *adapter)
4239 {
4240 struct net_device *netdev = adapter->netdev;
4241 struct ixgbe_hw *hw = &adapter->hw;
4242 u32 rxctrl;
4243 int i;
4244
4245 /* signal that we are down to the interrupt handler */
4246 set_bit(__IXGBE_DOWN, &adapter->state);
4247
4248 /* disable receives */
4249 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4250 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4251
4252 /* disable all enabled rx queues */
4253 for (i = 0; i < adapter->num_rx_queues; i++)
4254 /* this call also flushes the previous write */
4255 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4256
4257 usleep_range(10000, 20000);
4258
4259 netif_tx_stop_all_queues(netdev);
4260
4261 /* call carrier off first to avoid false dev_watchdog timeouts */
4262 netif_carrier_off(netdev);
4263 netif_tx_disable(netdev);
4264
4265 ixgbe_irq_disable(adapter);
4266
4267 ixgbe_napi_disable_all(adapter);
4268
4269 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4270 IXGBE_FLAG2_RESET_REQUESTED);
4271 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4272
4273 del_timer_sync(&adapter->service_timer);
4274
4275 if (adapter->num_vfs) {
4276 /* Clear EITR Select mapping */
4277 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4278
4279 /* Mark all the VFs as inactive */
4280 for (i = 0 ; i < adapter->num_vfs; i++)
4281 adapter->vfinfo[i].clear_to_send = false;
4282
4283 /* ping all the active vfs to let them know we are going down */
4284 ixgbe_ping_all_vfs(adapter);
4285
4286 /* Disable all VFTE/VFRE TX/RX */
4287 ixgbe_disable_tx_rx(adapter);
4288 }
4289
4290 /* disable transmits in the hardware now that interrupts are off */
4291 for (i = 0; i < adapter->num_tx_queues; i++) {
4292 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4293 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4294 }
4295
4296 /* Disable the Tx DMA engine on 82599 and X540 */
4297 switch (hw->mac.type) {
4298 case ixgbe_mac_82599EB:
4299 case ixgbe_mac_X540:
4300 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4301 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4302 ~IXGBE_DMATXCTL_TE));
4303 break;
4304 default:
4305 break;
4306 }
4307
4308 if (!pci_channel_offline(adapter->pdev))
4309 ixgbe_reset(adapter);
4310
4311 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4312 if (hw->mac.ops.disable_tx_laser &&
4313 ((hw->phy.multispeed_fiber) ||
4314 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4315 (hw->mac.type == ixgbe_mac_82599EB))))
4316 hw->mac.ops.disable_tx_laser(hw);
4317
4318 ixgbe_clean_all_tx_rings(adapter);
4319 ixgbe_clean_all_rx_rings(adapter);
4320
4321 #ifdef CONFIG_IXGBE_DCA
4322 /* since we reset the hardware DCA settings were cleared */
4323 ixgbe_setup_dca(adapter);
4324 #endif
4325 }
4326
4327 /**
4328 * ixgbe_tx_timeout - Respond to a Tx Hang
4329 * @netdev: network interface device structure
4330 **/
ixgbe_tx_timeout(struct net_device * netdev)4331 static void ixgbe_tx_timeout(struct net_device *netdev)
4332 {
4333 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4334
4335 /* Do the reset outside of interrupt context */
4336 ixgbe_tx_timeout_reset(adapter);
4337 }
4338
4339 /**
4340 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4341 * @adapter: board private structure to initialize
4342 *
4343 * ixgbe_sw_init initializes the Adapter private data structure.
4344 * Fields are initialized based on PCI device information and
4345 * OS network device settings (MTU size).
4346 **/
ixgbe_sw_init(struct ixgbe_adapter * adapter)4347 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4348 {
4349 struct ixgbe_hw *hw = &adapter->hw;
4350 struct pci_dev *pdev = adapter->pdev;
4351 unsigned int rss;
4352 #ifdef CONFIG_IXGBE_DCB
4353 int j;
4354 struct tc_configuration *tc;
4355 #endif
4356
4357 /* PCI config space info */
4358
4359 hw->vendor_id = pdev->vendor;
4360 hw->device_id = pdev->device;
4361 hw->revision_id = pdev->revision;
4362 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4363 hw->subsystem_device_id = pdev->subsystem_device;
4364
4365 /* Set capability flags */
4366 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4367 adapter->ring_feature[RING_F_RSS].indices = rss;
4368 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4369 switch (hw->mac.type) {
4370 case ixgbe_mac_82598EB:
4371 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4372 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4373 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4374 break;
4375 case ixgbe_mac_X540:
4376 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4377 case ixgbe_mac_82599EB:
4378 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4379 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4380 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4381 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4382 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4383 /* Flow Director hash filters enabled */
4384 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4385 adapter->atr_sample_rate = 20;
4386 adapter->ring_feature[RING_F_FDIR].indices =
4387 IXGBE_MAX_FDIR_INDICES;
4388 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4389 #ifdef IXGBE_FCOE
4390 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4391 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4392 adapter->ring_feature[RING_F_FCOE].indices = 0;
4393 #ifdef CONFIG_IXGBE_DCB
4394 /* Default traffic class to use for FCoE */
4395 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4396 #endif
4397 #endif /* IXGBE_FCOE */
4398 break;
4399 default:
4400 break;
4401 }
4402
4403 /* n-tuple support exists, always init our spinlock */
4404 spin_lock_init(&adapter->fdir_perfect_lock);
4405
4406 #ifdef CONFIG_IXGBE_DCB
4407 switch (hw->mac.type) {
4408 case ixgbe_mac_X540:
4409 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4410 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4411 break;
4412 default:
4413 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4414 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4415 break;
4416 }
4417
4418 /* Configure DCB traffic classes */
4419 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4420 tc = &adapter->dcb_cfg.tc_config[j];
4421 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4422 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4423 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4424 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4425 tc->dcb_pfc = pfc_disabled;
4426 }
4427
4428 /* Initialize default user to priority mapping, UPx->TC0 */
4429 tc = &adapter->dcb_cfg.tc_config[0];
4430 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4431 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4432
4433 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4434 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4435 adapter->dcb_cfg.pfc_mode_enable = false;
4436 adapter->dcb_set_bitmap = 0x00;
4437 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4438 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4439 sizeof(adapter->temp_dcb_cfg));
4440
4441 #endif
4442
4443 /* default flow control settings */
4444 hw->fc.requested_mode = ixgbe_fc_full;
4445 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4446 #ifdef CONFIG_DCB
4447 adapter->last_lfc_mode = hw->fc.current_mode;
4448 #endif
4449 ixgbe_pbthresh_setup(adapter);
4450 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4451 hw->fc.send_xon = true;
4452 hw->fc.disable_fc_autoneg = false;
4453
4454 /* enable itr by default in dynamic mode */
4455 adapter->rx_itr_setting = 1;
4456 adapter->tx_itr_setting = 1;
4457
4458 /* set default ring sizes */
4459 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4460 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4461
4462 /* set default work limits */
4463 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4464
4465 /* initialize eeprom parameters */
4466 if (ixgbe_init_eeprom_params_generic(hw)) {
4467 e_dev_err("EEPROM initialization failed\n");
4468 return -EIO;
4469 }
4470
4471 set_bit(__IXGBE_DOWN, &adapter->state);
4472
4473 return 0;
4474 }
4475
4476 /**
4477 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4478 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4479 *
4480 * Return 0 on success, negative on failure
4481 **/
ixgbe_setup_tx_resources(struct ixgbe_ring * tx_ring)4482 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4483 {
4484 struct device *dev = tx_ring->dev;
4485 int orig_node = dev_to_node(dev);
4486 int numa_node = -1;
4487 int size;
4488
4489 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4490
4491 if (tx_ring->q_vector)
4492 numa_node = tx_ring->q_vector->numa_node;
4493
4494 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4495 if (!tx_ring->tx_buffer_info)
4496 tx_ring->tx_buffer_info = vzalloc(size);
4497 if (!tx_ring->tx_buffer_info)
4498 goto err;
4499
4500 /* round up to nearest 4K */
4501 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4502 tx_ring->size = ALIGN(tx_ring->size, 4096);
4503
4504 set_dev_node(dev, numa_node);
4505 tx_ring->desc = dma_alloc_coherent(dev,
4506 tx_ring->size,
4507 &tx_ring->dma,
4508 GFP_KERNEL);
4509 set_dev_node(dev, orig_node);
4510 if (!tx_ring->desc)
4511 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4512 &tx_ring->dma, GFP_KERNEL);
4513 if (!tx_ring->desc)
4514 goto err;
4515
4516 tx_ring->next_to_use = 0;
4517 tx_ring->next_to_clean = 0;
4518 return 0;
4519
4520 err:
4521 vfree(tx_ring->tx_buffer_info);
4522 tx_ring->tx_buffer_info = NULL;
4523 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4524 return -ENOMEM;
4525 }
4526
4527 /**
4528 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4529 * @adapter: board private structure
4530 *
4531 * If this function returns with an error, then it's possible one or
4532 * more of the rings is populated (while the rest are not). It is the
4533 * callers duty to clean those orphaned rings.
4534 *
4535 * Return 0 on success, negative on failure
4536 **/
ixgbe_setup_all_tx_resources(struct ixgbe_adapter * adapter)4537 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4538 {
4539 int i, err = 0;
4540
4541 for (i = 0; i < adapter->num_tx_queues; i++) {
4542 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4543 if (!err)
4544 continue;
4545 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4546 break;
4547 }
4548
4549 return err;
4550 }
4551
4552 /**
4553 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4554 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4555 *
4556 * Returns 0 on success, negative on failure
4557 **/
ixgbe_setup_rx_resources(struct ixgbe_ring * rx_ring)4558 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4559 {
4560 struct device *dev = rx_ring->dev;
4561 int orig_node = dev_to_node(dev);
4562 int numa_node = -1;
4563 int size;
4564
4565 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4566
4567 if (rx_ring->q_vector)
4568 numa_node = rx_ring->q_vector->numa_node;
4569
4570 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4571 if (!rx_ring->rx_buffer_info)
4572 rx_ring->rx_buffer_info = vzalloc(size);
4573 if (!rx_ring->rx_buffer_info)
4574 goto err;
4575
4576 /* Round up to nearest 4K */
4577 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4578 rx_ring->size = ALIGN(rx_ring->size, 4096);
4579
4580 set_dev_node(dev, numa_node);
4581 rx_ring->desc = dma_alloc_coherent(dev,
4582 rx_ring->size,
4583 &rx_ring->dma,
4584 GFP_KERNEL);
4585 set_dev_node(dev, orig_node);
4586 if (!rx_ring->desc)
4587 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4588 &rx_ring->dma, GFP_KERNEL);
4589 if (!rx_ring->desc)
4590 goto err;
4591
4592 rx_ring->next_to_clean = 0;
4593 rx_ring->next_to_use = 0;
4594
4595 ixgbe_init_rx_page_offset(rx_ring);
4596
4597 return 0;
4598 err:
4599 vfree(rx_ring->rx_buffer_info);
4600 rx_ring->rx_buffer_info = NULL;
4601 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4602 return -ENOMEM;
4603 }
4604
4605 /**
4606 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4607 * @adapter: board private structure
4608 *
4609 * If this function returns with an error, then it's possible one or
4610 * more of the rings is populated (while the rest are not). It is the
4611 * callers duty to clean those orphaned rings.
4612 *
4613 * Return 0 on success, negative on failure
4614 **/
ixgbe_setup_all_rx_resources(struct ixgbe_adapter * adapter)4615 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4616 {
4617 int i, err = 0;
4618
4619 for (i = 0; i < adapter->num_rx_queues; i++) {
4620 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4621 if (!err)
4622 continue;
4623 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4624 break;
4625 }
4626
4627 return err;
4628 }
4629
4630 /**
4631 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4632 * @tx_ring: Tx descriptor ring for a specific queue
4633 *
4634 * Free all transmit software resources
4635 **/
ixgbe_free_tx_resources(struct ixgbe_ring * tx_ring)4636 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4637 {
4638 ixgbe_clean_tx_ring(tx_ring);
4639
4640 vfree(tx_ring->tx_buffer_info);
4641 tx_ring->tx_buffer_info = NULL;
4642
4643 /* if not set, then don't free */
4644 if (!tx_ring->desc)
4645 return;
4646
4647 dma_free_coherent(tx_ring->dev, tx_ring->size,
4648 tx_ring->desc, tx_ring->dma);
4649
4650 tx_ring->desc = NULL;
4651 }
4652
4653 /**
4654 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4655 * @adapter: board private structure
4656 *
4657 * Free all transmit software resources
4658 **/
ixgbe_free_all_tx_resources(struct ixgbe_adapter * adapter)4659 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4660 {
4661 int i;
4662
4663 for (i = 0; i < adapter->num_tx_queues; i++)
4664 if (adapter->tx_ring[i]->desc)
4665 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4666 }
4667
4668 /**
4669 * ixgbe_free_rx_resources - Free Rx Resources
4670 * @rx_ring: ring to clean the resources from
4671 *
4672 * Free all receive software resources
4673 **/
ixgbe_free_rx_resources(struct ixgbe_ring * rx_ring)4674 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4675 {
4676 ixgbe_clean_rx_ring(rx_ring);
4677
4678 vfree(rx_ring->rx_buffer_info);
4679 rx_ring->rx_buffer_info = NULL;
4680
4681 /* if not set, then don't free */
4682 if (!rx_ring->desc)
4683 return;
4684
4685 dma_free_coherent(rx_ring->dev, rx_ring->size,
4686 rx_ring->desc, rx_ring->dma);
4687
4688 rx_ring->desc = NULL;
4689 }
4690
4691 /**
4692 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4693 * @adapter: board private structure
4694 *
4695 * Free all receive software resources
4696 **/
ixgbe_free_all_rx_resources(struct ixgbe_adapter * adapter)4697 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4698 {
4699 int i;
4700
4701 for (i = 0; i < adapter->num_rx_queues; i++)
4702 if (adapter->rx_ring[i]->desc)
4703 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4704 }
4705
4706 /**
4707 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4708 * @netdev: network interface device structure
4709 * @new_mtu: new value for maximum frame size
4710 *
4711 * Returns 0 on success, negative on failure
4712 **/
ixgbe_change_mtu(struct net_device * netdev,int new_mtu)4713 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4714 {
4715 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4716 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4717
4718 /* MTU < 68 is an error and causes problems on some kernels */
4719 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4720 return -EINVAL;
4721
4722 /*
4723 * For 82599EB we cannot allow PF to change MTU greater than 1500
4724 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4725 * don't allocate and chain buffers correctly.
4726 */
4727 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4728 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4729 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4730 return -EINVAL;
4731
4732 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4733
4734 /* must set new MTU before calling down or up */
4735 netdev->mtu = new_mtu;
4736
4737 if (netif_running(netdev))
4738 ixgbe_reinit_locked(adapter);
4739
4740 return 0;
4741 }
4742
4743 /**
4744 * ixgbe_open - Called when a network interface is made active
4745 * @netdev: network interface device structure
4746 *
4747 * Returns 0 on success, negative value on failure
4748 *
4749 * The open entry point is called when a network interface is made
4750 * active by the system (IFF_UP). At this point all resources needed
4751 * for transmit and receive operations are allocated, the interrupt
4752 * handler is registered with the OS, the watchdog timer is started,
4753 * and the stack is notified that the interface is ready.
4754 **/
ixgbe_open(struct net_device * netdev)4755 static int ixgbe_open(struct net_device *netdev)
4756 {
4757 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4758 int err;
4759
4760 /* disallow open during test */
4761 if (test_bit(__IXGBE_TESTING, &adapter->state))
4762 return -EBUSY;
4763
4764 netif_carrier_off(netdev);
4765
4766 /* allocate transmit descriptors */
4767 err = ixgbe_setup_all_tx_resources(adapter);
4768 if (err)
4769 goto err_setup_tx;
4770
4771 /* allocate receive descriptors */
4772 err = ixgbe_setup_all_rx_resources(adapter);
4773 if (err)
4774 goto err_setup_rx;
4775
4776 ixgbe_configure(adapter);
4777
4778 err = ixgbe_request_irq(adapter);
4779 if (err)
4780 goto err_req_irq;
4781
4782 ixgbe_up_complete(adapter);
4783
4784 return 0;
4785
4786 err_req_irq:
4787 err_setup_rx:
4788 ixgbe_free_all_rx_resources(adapter);
4789 err_setup_tx:
4790 ixgbe_free_all_tx_resources(adapter);
4791 ixgbe_reset(adapter);
4792
4793 return err;
4794 }
4795
4796 /**
4797 * ixgbe_close - Disables a network interface
4798 * @netdev: network interface device structure
4799 *
4800 * Returns 0, this is not allowed to fail
4801 *
4802 * The close entry point is called when an interface is de-activated
4803 * by the OS. The hardware is still under the drivers control, but
4804 * needs to be disabled. A global MAC reset is issued to stop the
4805 * hardware, and all transmit and receive resources are freed.
4806 **/
ixgbe_close(struct net_device * netdev)4807 static int ixgbe_close(struct net_device *netdev)
4808 {
4809 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4810
4811 ixgbe_down(adapter);
4812 ixgbe_free_irq(adapter);
4813
4814 ixgbe_fdir_filter_exit(adapter);
4815
4816 ixgbe_free_all_tx_resources(adapter);
4817 ixgbe_free_all_rx_resources(adapter);
4818
4819 ixgbe_release_hw_control(adapter);
4820
4821 return 0;
4822 }
4823
4824 #ifdef CONFIG_PM
ixgbe_resume(struct pci_dev * pdev)4825 static int ixgbe_resume(struct pci_dev *pdev)
4826 {
4827 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4828 struct net_device *netdev = adapter->netdev;
4829 u32 err;
4830
4831 pci_set_power_state(pdev, PCI_D0);
4832 pci_restore_state(pdev);
4833 /*
4834 * pci_restore_state clears dev->state_saved so call
4835 * pci_save_state to restore it.
4836 */
4837 pci_save_state(pdev);
4838
4839 err = pci_enable_device_mem(pdev);
4840 if (err) {
4841 e_dev_err("Cannot enable PCI device from suspend\n");
4842 return err;
4843 }
4844 pci_set_master(pdev);
4845
4846 pci_wake_from_d3(pdev, false);
4847
4848 rtnl_lock();
4849 err = ixgbe_init_interrupt_scheme(adapter);
4850 rtnl_unlock();
4851 if (err) {
4852 e_dev_err("Cannot initialize interrupts for device\n");
4853 return err;
4854 }
4855
4856 ixgbe_reset(adapter);
4857
4858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4859
4860 if (netif_running(netdev)) {
4861 err = ixgbe_open(netdev);
4862 if (err)
4863 return err;
4864 }
4865
4866 netif_device_attach(netdev);
4867
4868 return 0;
4869 }
4870 #endif /* CONFIG_PM */
4871
__ixgbe_shutdown(struct pci_dev * pdev,bool * enable_wake)4872 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4873 {
4874 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4875 struct net_device *netdev = adapter->netdev;
4876 struct ixgbe_hw *hw = &adapter->hw;
4877 u32 ctrl, fctrl;
4878 u32 wufc = adapter->wol;
4879 #ifdef CONFIG_PM
4880 int retval = 0;
4881 #endif
4882
4883 netif_device_detach(netdev);
4884
4885 if (netif_running(netdev)) {
4886 rtnl_lock();
4887 ixgbe_down(adapter);
4888 ixgbe_free_irq(adapter);
4889 ixgbe_free_all_tx_resources(adapter);
4890 ixgbe_free_all_rx_resources(adapter);
4891 rtnl_unlock();
4892 }
4893
4894 ixgbe_clear_interrupt_scheme(adapter);
4895
4896 #ifdef CONFIG_PM
4897 retval = pci_save_state(pdev);
4898 if (retval)
4899 return retval;
4900
4901 #endif
4902 if (wufc) {
4903 ixgbe_set_rx_mode(netdev);
4904
4905 /*
4906 * enable the optics for both mult-speed fiber and
4907 * 82599 SFP+ fiber as we can WoL.
4908 */
4909 if (hw->mac.ops.enable_tx_laser &&
4910 (hw->phy.multispeed_fiber ||
4911 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4912 hw->mac.type == ixgbe_mac_82599EB)))
4913 hw->mac.ops.enable_tx_laser(hw);
4914
4915 /* turn on all-multi mode if wake on multicast is enabled */
4916 if (wufc & IXGBE_WUFC_MC) {
4917 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4918 fctrl |= IXGBE_FCTRL_MPE;
4919 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4920 }
4921
4922 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4923 ctrl |= IXGBE_CTRL_GIO_DIS;
4924 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4925
4926 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4927 } else {
4928 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4929 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4930 }
4931
4932 switch (hw->mac.type) {
4933 case ixgbe_mac_82598EB:
4934 pci_wake_from_d3(pdev, false);
4935 break;
4936 case ixgbe_mac_82599EB:
4937 case ixgbe_mac_X540:
4938 pci_wake_from_d3(pdev, !!wufc);
4939 break;
4940 default:
4941 break;
4942 }
4943
4944 *enable_wake = !!wufc;
4945
4946 ixgbe_release_hw_control(adapter);
4947
4948 pci_disable_device(pdev);
4949
4950 return 0;
4951 }
4952
4953 #ifdef CONFIG_PM
ixgbe_suspend(struct pci_dev * pdev,pm_message_t state)4954 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4955 {
4956 int retval;
4957 bool wake;
4958
4959 retval = __ixgbe_shutdown(pdev, &wake);
4960 if (retval)
4961 return retval;
4962
4963 if (wake) {
4964 pci_prepare_to_sleep(pdev);
4965 } else {
4966 pci_wake_from_d3(pdev, false);
4967 pci_set_power_state(pdev, PCI_D3hot);
4968 }
4969
4970 return 0;
4971 }
4972 #endif /* CONFIG_PM */
4973
ixgbe_shutdown(struct pci_dev * pdev)4974 static void ixgbe_shutdown(struct pci_dev *pdev)
4975 {
4976 bool wake;
4977
4978 __ixgbe_shutdown(pdev, &wake);
4979
4980 if (system_state == SYSTEM_POWER_OFF) {
4981 pci_wake_from_d3(pdev, wake);
4982 pci_set_power_state(pdev, PCI_D3hot);
4983 }
4984 }
4985
4986 /**
4987 * ixgbe_update_stats - Update the board statistics counters.
4988 * @adapter: board private structure
4989 **/
ixgbe_update_stats(struct ixgbe_adapter * adapter)4990 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4991 {
4992 struct net_device *netdev = adapter->netdev;
4993 struct ixgbe_hw *hw = &adapter->hw;
4994 struct ixgbe_hw_stats *hwstats = &adapter->stats;
4995 u64 total_mpc = 0;
4996 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4997 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
4998 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
4999 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
5000 #ifdef IXGBE_FCOE
5001 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5002 unsigned int cpu;
5003 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5004 #endif /* IXGBE_FCOE */
5005
5006 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5007 test_bit(__IXGBE_RESETTING, &adapter->state))
5008 return;
5009
5010 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5011 u64 rsc_count = 0;
5012 u64 rsc_flush = 0;
5013 for (i = 0; i < 16; i++)
5014 adapter->hw_rx_no_dma_resources +=
5015 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5016 for (i = 0; i < adapter->num_rx_queues; i++) {
5017 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5018 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5019 }
5020 adapter->rsc_total_count = rsc_count;
5021 adapter->rsc_total_flush = rsc_flush;
5022 }
5023
5024 for (i = 0; i < adapter->num_rx_queues; i++) {
5025 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5026 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5027 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5028 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5029 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5030 bytes += rx_ring->stats.bytes;
5031 packets += rx_ring->stats.packets;
5032 }
5033 adapter->non_eop_descs = non_eop_descs;
5034 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5035 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5036 adapter->hw_csum_rx_error = hw_csum_rx_error;
5037 netdev->stats.rx_bytes = bytes;
5038 netdev->stats.rx_packets = packets;
5039
5040 bytes = 0;
5041 packets = 0;
5042 /* gather some stats to the adapter struct that are per queue */
5043 for (i = 0; i < adapter->num_tx_queues; i++) {
5044 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5045 restart_queue += tx_ring->tx_stats.restart_queue;
5046 tx_busy += tx_ring->tx_stats.tx_busy;
5047 bytes += tx_ring->stats.bytes;
5048 packets += tx_ring->stats.packets;
5049 }
5050 adapter->restart_queue = restart_queue;
5051 adapter->tx_busy = tx_busy;
5052 netdev->stats.tx_bytes = bytes;
5053 netdev->stats.tx_packets = packets;
5054
5055 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5056
5057 /* 8 register reads */
5058 for (i = 0; i < 8; i++) {
5059 /* for packet buffers not used, the register should read 0 */
5060 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5061 missed_rx += mpc;
5062 hwstats->mpc[i] += mpc;
5063 total_mpc += hwstats->mpc[i];
5064 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5065 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5066 switch (hw->mac.type) {
5067 case ixgbe_mac_82598EB:
5068 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5069 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5070 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5071 hwstats->pxonrxc[i] +=
5072 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5073 break;
5074 case ixgbe_mac_82599EB:
5075 case ixgbe_mac_X540:
5076 hwstats->pxonrxc[i] +=
5077 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5078 break;
5079 default:
5080 break;
5081 }
5082 }
5083
5084 /*16 register reads */
5085 for (i = 0; i < 16; i++) {
5086 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5087 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5088 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5089 (hw->mac.type == ixgbe_mac_X540)) {
5090 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5091 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5092 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5093 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5094 }
5095 }
5096
5097 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5098 /* work around hardware counting issue */
5099 hwstats->gprc -= missed_rx;
5100
5101 ixgbe_update_xoff_received(adapter);
5102
5103 /* 82598 hardware only has a 32 bit counter in the high register */
5104 switch (hw->mac.type) {
5105 case ixgbe_mac_82598EB:
5106 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5107 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5108 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5109 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5110 break;
5111 case ixgbe_mac_X540:
5112 /* OS2BMC stats are X540 only*/
5113 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5114 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5115 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5116 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5117 case ixgbe_mac_82599EB:
5118 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5119 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5120 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5121 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5122 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5123 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5124 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5125 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5126 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5127 #ifdef IXGBE_FCOE
5128 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5129 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5130 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5131 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5132 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5133 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5134 /* Add up per cpu counters for total ddp aloc fail */
5135 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5136 for_each_possible_cpu(cpu) {
5137 fcoe_noddp_counts_sum +=
5138 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5139 fcoe_noddp_ext_buff_counts_sum +=
5140 *per_cpu_ptr(fcoe->
5141 pcpu_noddp_ext_buff, cpu);
5142 }
5143 }
5144 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5145 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5146 #endif /* IXGBE_FCOE */
5147 break;
5148 default:
5149 break;
5150 }
5151 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5152 hwstats->bprc += bprc;
5153 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5154 if (hw->mac.type == ixgbe_mac_82598EB)
5155 hwstats->mprc -= bprc;
5156 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5157 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5158 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5159 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5160 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5161 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5162 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5163 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5164 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5165 hwstats->lxontxc += lxon;
5166 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5167 hwstats->lxofftxc += lxoff;
5168 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5169 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5170 /*
5171 * 82598 errata - tx of flow control packets is included in tx counters
5172 */
5173 xon_off_tot = lxon + lxoff;
5174 hwstats->gptc -= xon_off_tot;
5175 hwstats->mptc -= xon_off_tot;
5176 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5177 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5178 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5179 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5180 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5181 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5182 hwstats->ptc64 -= xon_off_tot;
5183 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5184 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5185 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5186 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5187 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5188 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5189
5190 /* Fill out the OS statistics structure */
5191 netdev->stats.multicast = hwstats->mprc;
5192
5193 /* Rx Errors */
5194 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5195 netdev->stats.rx_dropped = 0;
5196 netdev->stats.rx_length_errors = hwstats->rlec;
5197 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5198 netdev->stats.rx_missed_errors = total_mpc;
5199 }
5200
5201 /**
5202 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5203 * @adapter - pointer to the device adapter structure
5204 **/
ixgbe_fdir_reinit_subtask(struct ixgbe_adapter * adapter)5205 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5206 {
5207 struct ixgbe_hw *hw = &adapter->hw;
5208 int i;
5209
5210 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5211 return;
5212
5213 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5214
5215 /* if interface is down do nothing */
5216 if (test_bit(__IXGBE_DOWN, &adapter->state))
5217 return;
5218
5219 /* do nothing if we are not using signature filters */
5220 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5221 return;
5222
5223 adapter->fdir_overflow++;
5224
5225 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5226 for (i = 0; i < adapter->num_tx_queues; i++)
5227 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5228 &(adapter->tx_ring[i]->state));
5229 /* re-enable flow director interrupts */
5230 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5231 } else {
5232 e_err(probe, "failed to finish FDIR re-initialization, "
5233 "ignored adding FDIR ATR filters\n");
5234 }
5235 }
5236
5237 /**
5238 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5239 * @adapter - pointer to the device adapter structure
5240 *
5241 * This function serves two purposes. First it strobes the interrupt lines
5242 * in order to make certain interrupts are occurring. Secondly it sets the
5243 * bits needed to check for TX hangs. As a result we should immediately
5244 * determine if a hang has occurred.
5245 */
ixgbe_check_hang_subtask(struct ixgbe_adapter * adapter)5246 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5247 {
5248 struct ixgbe_hw *hw = &adapter->hw;
5249 u64 eics = 0;
5250 int i;
5251
5252 /* If we're down or resetting, just bail */
5253 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5254 test_bit(__IXGBE_RESETTING, &adapter->state))
5255 return;
5256
5257 /* Force detection of hung controller */
5258 if (netif_carrier_ok(adapter->netdev)) {
5259 for (i = 0; i < adapter->num_tx_queues; i++)
5260 set_check_for_tx_hang(adapter->tx_ring[i]);
5261 }
5262
5263 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5264 /*
5265 * for legacy and MSI interrupts don't set any bits
5266 * that are enabled for EIAM, because this operation
5267 * would set *both* EIMS and EICS for any bit in EIAM
5268 */
5269 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5270 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5271 } else {
5272 /* get one bit for every active tx/rx interrupt vector */
5273 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5274 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5275 if (qv->rx.ring || qv->tx.ring)
5276 eics |= ((u64)1 << i);
5277 }
5278 }
5279
5280 /* Cause software interrupt to ensure rings are cleaned */
5281 ixgbe_irq_rearm_queues(adapter, eics);
5282
5283 }
5284
5285 /**
5286 * ixgbe_watchdog_update_link - update the link status
5287 * @adapter - pointer to the device adapter structure
5288 * @link_speed - pointer to a u32 to store the link_speed
5289 **/
ixgbe_watchdog_update_link(struct ixgbe_adapter * adapter)5290 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5291 {
5292 struct ixgbe_hw *hw = &adapter->hw;
5293 u32 link_speed = adapter->link_speed;
5294 bool link_up = adapter->link_up;
5295 int i;
5296
5297 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5298 return;
5299
5300 if (hw->mac.ops.check_link) {
5301 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5302 } else {
5303 /* always assume link is up, if no check link function */
5304 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5305 link_up = true;
5306 }
5307 if (link_up) {
5308 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5309 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5310 hw->mac.ops.fc_enable(hw, i);
5311 } else {
5312 hw->mac.ops.fc_enable(hw, 0);
5313 }
5314 }
5315
5316 if (link_up ||
5317 time_after(jiffies, (adapter->link_check_timeout +
5318 IXGBE_TRY_LINK_TIMEOUT))) {
5319 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5320 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5321 IXGBE_WRITE_FLUSH(hw);
5322 }
5323
5324 adapter->link_up = link_up;
5325 adapter->link_speed = link_speed;
5326 }
5327
5328 /**
5329 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5330 * print link up message
5331 * @adapter - pointer to the device adapter structure
5332 **/
ixgbe_watchdog_link_is_up(struct ixgbe_adapter * adapter)5333 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5334 {
5335 struct net_device *netdev = adapter->netdev;
5336 struct ixgbe_hw *hw = &adapter->hw;
5337 u32 link_speed = adapter->link_speed;
5338 bool flow_rx, flow_tx;
5339
5340 /* only continue if link was previously down */
5341 if (netif_carrier_ok(netdev))
5342 return;
5343
5344 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5345
5346 switch (hw->mac.type) {
5347 case ixgbe_mac_82598EB: {
5348 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5349 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5350 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5351 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5352 }
5353 break;
5354 case ixgbe_mac_X540:
5355 case ixgbe_mac_82599EB: {
5356 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5357 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5358 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5359 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5360 }
5361 break;
5362 default:
5363 flow_tx = false;
5364 flow_rx = false;
5365 break;
5366 }
5367 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5368 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5369 "10 Gbps" :
5370 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5371 "1 Gbps" :
5372 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5373 "100 Mbps" :
5374 "unknown speed"))),
5375 ((flow_rx && flow_tx) ? "RX/TX" :
5376 (flow_rx ? "RX" :
5377 (flow_tx ? "TX" : "None"))));
5378
5379 netif_carrier_on(netdev);
5380 ixgbe_check_vf_rate_limit(adapter);
5381 }
5382
5383 /**
5384 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5385 * print link down message
5386 * @adapter - pointer to the adapter structure
5387 **/
ixgbe_watchdog_link_is_down(struct ixgbe_adapter * adapter)5388 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5389 {
5390 struct net_device *netdev = adapter->netdev;
5391 struct ixgbe_hw *hw = &adapter->hw;
5392
5393 adapter->link_up = false;
5394 adapter->link_speed = 0;
5395
5396 /* only continue if link was up previously */
5397 if (!netif_carrier_ok(netdev))
5398 return;
5399
5400 /* poll for SFP+ cable when link is down */
5401 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5402 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5403
5404 e_info(drv, "NIC Link is Down\n");
5405 netif_carrier_off(netdev);
5406 }
5407
5408 /**
5409 * ixgbe_watchdog_flush_tx - flush queues on link down
5410 * @adapter - pointer to the device adapter structure
5411 **/
ixgbe_watchdog_flush_tx(struct ixgbe_adapter * adapter)5412 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5413 {
5414 int i;
5415 int some_tx_pending = 0;
5416
5417 if (!netif_carrier_ok(adapter->netdev)) {
5418 for (i = 0; i < adapter->num_tx_queues; i++) {
5419 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5420 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5421 some_tx_pending = 1;
5422 break;
5423 }
5424 }
5425
5426 if (some_tx_pending) {
5427 /* We've lost link, so the controller stops DMA,
5428 * but we've got queued Tx work that's never going
5429 * to get done, so reset controller to flush Tx.
5430 * (Do the reset outside of interrupt context).
5431 */
5432 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5433 }
5434 }
5435 }
5436
ixgbe_spoof_check(struct ixgbe_adapter * adapter)5437 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5438 {
5439 u32 ssvpc;
5440
5441 /* Do not perform spoof check for 82598 */
5442 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5443 return;
5444
5445 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5446
5447 /*
5448 * ssvpc register is cleared on read, if zero then no
5449 * spoofed packets in the last interval.
5450 */
5451 if (!ssvpc)
5452 return;
5453
5454 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5455 }
5456
5457 /**
5458 * ixgbe_watchdog_subtask - check and bring link up
5459 * @adapter - pointer to the device adapter structure
5460 **/
ixgbe_watchdog_subtask(struct ixgbe_adapter * adapter)5461 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5462 {
5463 /* if interface is down do nothing */
5464 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5465 test_bit(__IXGBE_RESETTING, &adapter->state))
5466 return;
5467
5468 ixgbe_watchdog_update_link(adapter);
5469
5470 if (adapter->link_up)
5471 ixgbe_watchdog_link_is_up(adapter);
5472 else
5473 ixgbe_watchdog_link_is_down(adapter);
5474
5475 ixgbe_spoof_check(adapter);
5476 ixgbe_update_stats(adapter);
5477
5478 ixgbe_watchdog_flush_tx(adapter);
5479 }
5480
5481 /**
5482 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5483 * @adapter - the ixgbe adapter structure
5484 **/
ixgbe_sfp_detection_subtask(struct ixgbe_adapter * adapter)5485 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5486 {
5487 struct ixgbe_hw *hw = &adapter->hw;
5488 s32 err;
5489
5490 /* not searching for SFP so there is nothing to do here */
5491 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5492 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5493 return;
5494
5495 /* someone else is in init, wait until next service event */
5496 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5497 return;
5498
5499 err = hw->phy.ops.identify_sfp(hw);
5500 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5501 goto sfp_out;
5502
5503 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5504 /* If no cable is present, then we need to reset
5505 * the next time we find a good cable. */
5506 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5507 }
5508
5509 /* exit on error */
5510 if (err)
5511 goto sfp_out;
5512
5513 /* exit if reset not needed */
5514 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5515 goto sfp_out;
5516
5517 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5518
5519 /*
5520 * A module may be identified correctly, but the EEPROM may not have
5521 * support for that module. setup_sfp() will fail in that case, so
5522 * we should not allow that module to load.
5523 */
5524 if (hw->mac.type == ixgbe_mac_82598EB)
5525 err = hw->phy.ops.reset(hw);
5526 else
5527 err = hw->mac.ops.setup_sfp(hw);
5528
5529 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5530 goto sfp_out;
5531
5532 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5533 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5534
5535 sfp_out:
5536 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5537
5538 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5539 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5540 e_dev_err("failed to initialize because an unsupported "
5541 "SFP+ module type was detected.\n");
5542 e_dev_err("Reload the driver after installing a "
5543 "supported module.\n");
5544 unregister_netdev(adapter->netdev);
5545 }
5546 }
5547
5548 /**
5549 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5550 * @adapter - the ixgbe adapter structure
5551 **/
ixgbe_sfp_link_config_subtask(struct ixgbe_adapter * adapter)5552 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5553 {
5554 struct ixgbe_hw *hw = &adapter->hw;
5555 u32 autoneg;
5556 bool negotiation;
5557
5558 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5559 return;
5560
5561 /* someone else is in init, wait until next service event */
5562 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5563 return;
5564
5565 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5566
5567 autoneg = hw->phy.autoneg_advertised;
5568 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5569 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5570 if (hw->mac.ops.setup_link)
5571 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5572
5573 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5574 adapter->link_check_timeout = jiffies;
5575 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5576 }
5577
5578 #ifdef CONFIG_PCI_IOV
ixgbe_check_for_bad_vf(struct ixgbe_adapter * adapter)5579 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5580 {
5581 int vf;
5582 struct ixgbe_hw *hw = &adapter->hw;
5583 struct net_device *netdev = adapter->netdev;
5584 u32 gpc;
5585 u32 ciaa, ciad;
5586
5587 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5588 if (gpc) /* If incrementing then no need for the check below */
5589 return;
5590 /*
5591 * Check to see if a bad DMA write target from an errant or
5592 * malicious VF has caused a PCIe error. If so then we can
5593 * issue a VFLR to the offending VF(s) and then resume without
5594 * requesting a full slot reset.
5595 */
5596
5597 for (vf = 0; vf < adapter->num_vfs; vf++) {
5598 ciaa = (vf << 16) | 0x80000000;
5599 /* 32 bit read so align, we really want status at offset 6 */
5600 ciaa |= PCI_COMMAND;
5601 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5602 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5603 ciaa &= 0x7FFFFFFF;
5604 /* disable debug mode asap after reading data */
5605 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5606 /* Get the upper 16 bits which will be the PCI status reg */
5607 ciad >>= 16;
5608 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5609 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5610 /* Issue VFLR */
5611 ciaa = (vf << 16) | 0x80000000;
5612 ciaa |= 0xA8;
5613 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5614 ciad = 0x00008000; /* VFLR */
5615 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5616 ciaa &= 0x7FFFFFFF;
5617 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5618 }
5619 }
5620 }
5621
5622 #endif
5623 /**
5624 * ixgbe_service_timer - Timer Call-back
5625 * @data: pointer to adapter cast into an unsigned long
5626 **/
ixgbe_service_timer(unsigned long data)5627 static void ixgbe_service_timer(unsigned long data)
5628 {
5629 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5630 unsigned long next_event_offset;
5631 bool ready = true;
5632
5633 /* poll faster when waiting for link */
5634 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5635 next_event_offset = HZ / 10;
5636 else
5637 next_event_offset = HZ * 2;
5638
5639 #ifdef CONFIG_PCI_IOV
5640 /*
5641 * don't bother with SR-IOV VF DMA hang check if there are
5642 * no VFs or the link is down
5643 */
5644 if (!adapter->num_vfs ||
5645 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5646 goto normal_timer_service;
5647
5648 /* If we have VFs allocated then we must check for DMA hangs */
5649 ixgbe_check_for_bad_vf(adapter);
5650 next_event_offset = HZ / 50;
5651 adapter->timer_event_accumulator++;
5652
5653 if (adapter->timer_event_accumulator >= 100)
5654 adapter->timer_event_accumulator = 0;
5655 else
5656 ready = false;
5657
5658 normal_timer_service:
5659 #endif
5660 /* Reset the timer */
5661 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5662
5663 if (ready)
5664 ixgbe_service_event_schedule(adapter);
5665 }
5666
ixgbe_reset_subtask(struct ixgbe_adapter * adapter)5667 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5668 {
5669 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5670 return;
5671
5672 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5673
5674 /* If we're already down or resetting, just bail */
5675 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5676 test_bit(__IXGBE_RESETTING, &adapter->state))
5677 return;
5678
5679 ixgbe_dump(adapter);
5680 netdev_err(adapter->netdev, "Reset adapter\n");
5681 adapter->tx_timeout_count++;
5682
5683 ixgbe_reinit_locked(adapter);
5684 }
5685
5686 /**
5687 * ixgbe_service_task - manages and runs subtasks
5688 * @work: pointer to work_struct containing our data
5689 **/
ixgbe_service_task(struct work_struct * work)5690 static void ixgbe_service_task(struct work_struct *work)
5691 {
5692 struct ixgbe_adapter *adapter = container_of(work,
5693 struct ixgbe_adapter,
5694 service_task);
5695
5696 ixgbe_reset_subtask(adapter);
5697 ixgbe_sfp_detection_subtask(adapter);
5698 ixgbe_sfp_link_config_subtask(adapter);
5699 ixgbe_check_overtemp_subtask(adapter);
5700 ixgbe_watchdog_subtask(adapter);
5701 ixgbe_fdir_reinit_subtask(adapter);
5702 ixgbe_check_hang_subtask(adapter);
5703
5704 ixgbe_service_event_complete(adapter);
5705 }
5706
ixgbe_tso(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,u8 * hdr_len)5707 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5708 struct ixgbe_tx_buffer *first,
5709 u8 *hdr_len)
5710 {
5711 struct sk_buff *skb = first->skb;
5712 u32 vlan_macip_lens, type_tucmd;
5713 u32 mss_l4len_idx, l4len;
5714
5715 if (!skb_is_gso(skb))
5716 return 0;
5717
5718 if (skb_header_cloned(skb)) {
5719 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5720 if (err)
5721 return err;
5722 }
5723
5724 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5725 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5726
5727 if (first->protocol == __constant_htons(ETH_P_IP)) {
5728 struct iphdr *iph = ip_hdr(skb);
5729 iph->tot_len = 0;
5730 iph->check = 0;
5731 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5732 iph->daddr, 0,
5733 IPPROTO_TCP,
5734 0);
5735 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5736 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5737 IXGBE_TX_FLAGS_CSUM |
5738 IXGBE_TX_FLAGS_IPV4;
5739 } else if (skb_is_gso_v6(skb)) {
5740 ipv6_hdr(skb)->payload_len = 0;
5741 tcp_hdr(skb)->check =
5742 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5743 &ipv6_hdr(skb)->daddr,
5744 0, IPPROTO_TCP, 0);
5745 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5746 IXGBE_TX_FLAGS_CSUM;
5747 }
5748
5749 /* compute header lengths */
5750 l4len = tcp_hdrlen(skb);
5751 *hdr_len = skb_transport_offset(skb) + l4len;
5752
5753 /* update gso size and bytecount with header size */
5754 first->gso_segs = skb_shinfo(skb)->gso_segs;
5755 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5756
5757 /* mss_l4len_id: use 1 as index for TSO */
5758 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5759 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5760 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5761
5762 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5763 vlan_macip_lens = skb_network_header_len(skb);
5764 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5765 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5766
5767 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5768 mss_l4len_idx);
5769
5770 return 1;
5771 }
5772
ixgbe_tx_csum(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first)5773 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5774 struct ixgbe_tx_buffer *first)
5775 {
5776 struct sk_buff *skb = first->skb;
5777 u32 vlan_macip_lens = 0;
5778 u32 mss_l4len_idx = 0;
5779 u32 type_tucmd = 0;
5780
5781 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5782 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5783 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5784 return;
5785 } else {
5786 u8 l4_hdr = 0;
5787 switch (first->protocol) {
5788 case __constant_htons(ETH_P_IP):
5789 vlan_macip_lens |= skb_network_header_len(skb);
5790 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5791 l4_hdr = ip_hdr(skb)->protocol;
5792 break;
5793 case __constant_htons(ETH_P_IPV6):
5794 vlan_macip_lens |= skb_network_header_len(skb);
5795 l4_hdr = ipv6_hdr(skb)->nexthdr;
5796 break;
5797 default:
5798 if (unlikely(net_ratelimit())) {
5799 dev_warn(tx_ring->dev,
5800 "partial checksum but proto=%x!\n",
5801 first->protocol);
5802 }
5803 break;
5804 }
5805
5806 switch (l4_hdr) {
5807 case IPPROTO_TCP:
5808 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5809 mss_l4len_idx = tcp_hdrlen(skb) <<
5810 IXGBE_ADVTXD_L4LEN_SHIFT;
5811 break;
5812 case IPPROTO_SCTP:
5813 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5814 mss_l4len_idx = sizeof(struct sctphdr) <<
5815 IXGBE_ADVTXD_L4LEN_SHIFT;
5816 break;
5817 case IPPROTO_UDP:
5818 mss_l4len_idx = sizeof(struct udphdr) <<
5819 IXGBE_ADVTXD_L4LEN_SHIFT;
5820 break;
5821 default:
5822 if (unlikely(net_ratelimit())) {
5823 dev_warn(tx_ring->dev,
5824 "partial checksum but l4 proto=%x!\n",
5825 l4_hdr);
5826 }
5827 break;
5828 }
5829
5830 /* update TX checksum flag */
5831 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
5832 }
5833
5834 /* vlan_macip_lens: MACLEN, VLAN tag */
5835 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5836 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5837
5838 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5839 type_tucmd, mss_l4len_idx);
5840 }
5841
ixgbe_tx_cmd_type(u32 tx_flags)5842 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
5843 {
5844 /* set type for advanced descriptor with frame checksum insertion */
5845 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5846 IXGBE_ADVTXD_DCMD_IFCS |
5847 IXGBE_ADVTXD_DCMD_DEXT);
5848
5849 /* set HW vlan bit if vlan is present */
5850 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
5851 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
5852
5853 /* set segmentation enable bits for TSO/FSO */
5854 #ifdef IXGBE_FCOE
5855 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
5856 #else
5857 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5858 #endif
5859 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
5860
5861 return cmd_type;
5862 }
5863
ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc * tx_desc,u32 tx_flags,unsigned int paylen)5864 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5865 u32 tx_flags, unsigned int paylen)
5866 {
5867 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
5868
5869 /* enable L4 checksum for TSO and TX checksum offload */
5870 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5871 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
5872
5873 /* enble IPv4 checksum for TSO */
5874 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5875 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
5876
5877 /* use index 1 context for TSO/FSO/FCOE */
5878 #ifdef IXGBE_FCOE
5879 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5880 #else
5881 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5882 #endif
5883 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5884
5885 /*
5886 * Check Context must be set if Tx switch is enabled, which it
5887 * always is for case where virtual functions are running
5888 */
5889 #ifdef IXGBE_FCOE
5890 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5891 #else
5892 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
5893 #endif
5894 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5895
5896 tx_desc->read.olinfo_status = olinfo_status;
5897 }
5898
5899 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5900 IXGBE_TXD_CMD_RS)
5901
ixgbe_tx_map(struct ixgbe_ring * tx_ring,struct ixgbe_tx_buffer * first,const u8 hdr_len)5902 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
5903 struct ixgbe_tx_buffer *first,
5904 const u8 hdr_len)
5905 {
5906 dma_addr_t dma;
5907 struct sk_buff *skb = first->skb;
5908 struct ixgbe_tx_buffer *tx_buffer;
5909 union ixgbe_adv_tx_desc *tx_desc;
5910 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
5911 unsigned int data_len = skb->data_len;
5912 unsigned int size = skb_headlen(skb);
5913 unsigned int paylen = skb->len - hdr_len;
5914 u32 tx_flags = first->tx_flags;
5915 __le32 cmd_type;
5916 u16 i = tx_ring->next_to_use;
5917
5918 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5919
5920 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5921 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5922
5923 #ifdef IXGBE_FCOE
5924 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5925 if (data_len < sizeof(struct fcoe_crc_eof)) {
5926 size -= sizeof(struct fcoe_crc_eof) - data_len;
5927 data_len = 0;
5928 } else {
5929 data_len -= sizeof(struct fcoe_crc_eof);
5930 }
5931 }
5932
5933 #endif
5934 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5935 if (dma_mapping_error(tx_ring->dev, dma))
5936 goto dma_error;
5937
5938 /* record length, and DMA address */
5939 dma_unmap_len_set(first, len, size);
5940 dma_unmap_addr_set(first, dma, dma);
5941
5942 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5943
5944 for (;;) {
5945 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
5946 tx_desc->read.cmd_type_len =
5947 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
5948
5949 i++;
5950 tx_desc++;
5951 if (i == tx_ring->count) {
5952 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5953 i = 0;
5954 }
5955
5956 dma += IXGBE_MAX_DATA_PER_TXD;
5957 size -= IXGBE_MAX_DATA_PER_TXD;
5958
5959 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5960 tx_desc->read.olinfo_status = 0;
5961 }
5962
5963 if (likely(!data_len))
5964 break;
5965
5966 if (unlikely(skb->no_fcs))
5967 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
5968 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
5969
5970 i++;
5971 tx_desc++;
5972 if (i == tx_ring->count) {
5973 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5974 i = 0;
5975 }
5976
5977 #ifdef IXGBE_FCOE
5978 size = min_t(unsigned int, data_len, skb_frag_size(frag));
5979 #else
5980 size = skb_frag_size(frag);
5981 #endif
5982 data_len -= size;
5983
5984 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
5985 DMA_TO_DEVICE);
5986 if (dma_mapping_error(tx_ring->dev, dma))
5987 goto dma_error;
5988
5989 tx_buffer = &tx_ring->tx_buffer_info[i];
5990 dma_unmap_len_set(tx_buffer, len, size);
5991 dma_unmap_addr_set(tx_buffer, dma, dma);
5992
5993 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5994 tx_desc->read.olinfo_status = 0;
5995
5996 frag++;
5997 }
5998
5999 /* write last descriptor with RS and EOP bits */
6000 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6001 tx_desc->read.cmd_type_len = cmd_type;
6002
6003 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6004
6005 /* set the timestamp */
6006 first->time_stamp = jiffies;
6007
6008 /*
6009 * Force memory writes to complete before letting h/w know there
6010 * are new descriptors to fetch. (Only applicable for weak-ordered
6011 * memory model archs, such as IA-64).
6012 *
6013 * We also need this memory barrier to make certain all of the
6014 * status bits have been updated before next_to_watch is written.
6015 */
6016 wmb();
6017
6018 /* set next_to_watch value indicating a packet is present */
6019 first->next_to_watch = tx_desc;
6020
6021 i++;
6022 if (i == tx_ring->count)
6023 i = 0;
6024
6025 tx_ring->next_to_use = i;
6026
6027 /* notify HW of packet */
6028 writel(i, tx_ring->tail);
6029
6030 return;
6031 dma_error:
6032 dev_err(tx_ring->dev, "TX DMA map failed\n");
6033
6034 /* clear dma mappings for failed tx_buffer_info map */
6035 for (;;) {
6036 tx_buffer = &tx_ring->tx_buffer_info[i];
6037 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6038 if (tx_buffer == first)
6039 break;
6040 if (i == 0)
6041 i = tx_ring->count;
6042 i--;
6043 }
6044
6045 tx_ring->next_to_use = i;
6046 }
6047
ixgbe_atr(struct ixgbe_ring * ring,struct ixgbe_tx_buffer * first)6048 static void ixgbe_atr(struct ixgbe_ring *ring,
6049 struct ixgbe_tx_buffer *first)
6050 {
6051 struct ixgbe_q_vector *q_vector = ring->q_vector;
6052 union ixgbe_atr_hash_dword input = { .dword = 0 };
6053 union ixgbe_atr_hash_dword common = { .dword = 0 };
6054 union {
6055 unsigned char *network;
6056 struct iphdr *ipv4;
6057 struct ipv6hdr *ipv6;
6058 } hdr;
6059 struct tcphdr *th;
6060 __be16 vlan_id;
6061
6062 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6063 if (!q_vector)
6064 return;
6065
6066 /* do nothing if sampling is disabled */
6067 if (!ring->atr_sample_rate)
6068 return;
6069
6070 ring->atr_count++;
6071
6072 /* snag network header to get L4 type and address */
6073 hdr.network = skb_network_header(first->skb);
6074
6075 /* Currently only IPv4/IPv6 with TCP is supported */
6076 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6077 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6078 (first->protocol != __constant_htons(ETH_P_IP) ||
6079 hdr.ipv4->protocol != IPPROTO_TCP))
6080 return;
6081
6082 th = tcp_hdr(first->skb);
6083
6084 /* skip this packet since it is invalid or the socket is closing */
6085 if (!th || th->fin)
6086 return;
6087
6088 /* sample on all syn packets or once every atr sample count */
6089 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6090 return;
6091
6092 /* reset sample count */
6093 ring->atr_count = 0;
6094
6095 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6096
6097 /*
6098 * src and dst are inverted, think how the receiver sees them
6099 *
6100 * The input is broken into two sections, a non-compressed section
6101 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6102 * is XORed together and stored in the compressed dword.
6103 */
6104 input.formatted.vlan_id = vlan_id;
6105
6106 /*
6107 * since src port and flex bytes occupy the same word XOR them together
6108 * and write the value to source port portion of compressed dword
6109 */
6110 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6111 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6112 else
6113 common.port.src ^= th->dest ^ first->protocol;
6114 common.port.dst ^= th->source;
6115
6116 if (first->protocol == __constant_htons(ETH_P_IP)) {
6117 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6118 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6119 } else {
6120 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6121 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6122 hdr.ipv6->saddr.s6_addr32[1] ^
6123 hdr.ipv6->saddr.s6_addr32[2] ^
6124 hdr.ipv6->saddr.s6_addr32[3] ^
6125 hdr.ipv6->daddr.s6_addr32[0] ^
6126 hdr.ipv6->daddr.s6_addr32[1] ^
6127 hdr.ipv6->daddr.s6_addr32[2] ^
6128 hdr.ipv6->daddr.s6_addr32[3];
6129 }
6130
6131 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6132 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6133 input, common, ring->queue_index);
6134 }
6135
__ixgbe_maybe_stop_tx(struct ixgbe_ring * tx_ring,u16 size)6136 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6137 {
6138 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6139 /* Herbert's original patch had:
6140 * smp_mb__after_netif_stop_queue();
6141 * but since that doesn't exist yet, just open code it. */
6142 smp_mb();
6143
6144 /* We need to check again in a case another CPU has just
6145 * made room available. */
6146 if (likely(ixgbe_desc_unused(tx_ring) < size))
6147 return -EBUSY;
6148
6149 /* A reprieve! - use start_queue because it doesn't call schedule */
6150 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6151 ++tx_ring->tx_stats.restart_queue;
6152 return 0;
6153 }
6154
ixgbe_maybe_stop_tx(struct ixgbe_ring * tx_ring,u16 size)6155 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6156 {
6157 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6158 return 0;
6159 return __ixgbe_maybe_stop_tx(tx_ring, size);
6160 }
6161
ixgbe_select_queue(struct net_device * dev,struct sk_buff * skb)6162 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6163 {
6164 struct ixgbe_adapter *adapter = netdev_priv(dev);
6165 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6166 smp_processor_id();
6167 #ifdef IXGBE_FCOE
6168 __be16 protocol = vlan_get_protocol(skb);
6169
6170 if (((protocol == htons(ETH_P_FCOE)) ||
6171 (protocol == htons(ETH_P_FIP))) &&
6172 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6173 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6174 txq += adapter->ring_feature[RING_F_FCOE].mask;
6175 return txq;
6176 }
6177 #endif
6178
6179 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6180 while (unlikely(txq >= dev->real_num_tx_queues))
6181 txq -= dev->real_num_tx_queues;
6182 return txq;
6183 }
6184
6185 return skb_tx_hash(dev, skb);
6186 }
6187
ixgbe_xmit_frame_ring(struct sk_buff * skb,struct ixgbe_adapter * adapter,struct ixgbe_ring * tx_ring)6188 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6189 struct ixgbe_adapter *adapter,
6190 struct ixgbe_ring *tx_ring)
6191 {
6192 struct ixgbe_tx_buffer *first;
6193 int tso;
6194 u32 tx_flags = 0;
6195 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6196 unsigned short f;
6197 #endif
6198 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6199 __be16 protocol = skb->protocol;
6200 u8 hdr_len = 0;
6201
6202 /*
6203 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6204 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6205 * + 2 desc gap to keep tail from touching head,
6206 * + 1 desc for context descriptor,
6207 * otherwise try next time
6208 */
6209 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6210 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6211 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6212 #else
6213 count += skb_shinfo(skb)->nr_frags;
6214 #endif
6215 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6216 tx_ring->tx_stats.tx_busy++;
6217 return NETDEV_TX_BUSY;
6218 }
6219
6220 /* record the location of the first descriptor for this packet */
6221 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6222 first->skb = skb;
6223 first->bytecount = skb->len;
6224 first->gso_segs = 1;
6225
6226 /* if we have a HW VLAN tag being added default to the HW one */
6227 if (vlan_tx_tag_present(skb)) {
6228 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6229 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6230 /* else if it is a SW VLAN check the next protocol and store the tag */
6231 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6232 struct vlan_hdr *vhdr, _vhdr;
6233 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6234 if (!vhdr)
6235 goto out_drop;
6236
6237 protocol = vhdr->h_vlan_encapsulated_proto;
6238 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6239 IXGBE_TX_FLAGS_VLAN_SHIFT;
6240 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6241 }
6242
6243 #ifdef CONFIG_PCI_IOV
6244 /*
6245 * Use the l2switch_enable flag - would be false if the DMA
6246 * Tx switch had been disabled.
6247 */
6248 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6249 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6250
6251 #endif
6252 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6253 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6254 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6255 (skb->priority != TC_PRIO_CONTROL))) {
6256 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6257 tx_flags |= (skb->priority & 0x7) <<
6258 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6259 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6260 struct vlan_ethhdr *vhdr;
6261 if (skb_header_cloned(skb) &&
6262 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6263 goto out_drop;
6264 vhdr = (struct vlan_ethhdr *)skb->data;
6265 vhdr->h_vlan_TCI = htons(tx_flags >>
6266 IXGBE_TX_FLAGS_VLAN_SHIFT);
6267 } else {
6268 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6269 }
6270 }
6271
6272 /* record initial flags and protocol */
6273 first->tx_flags = tx_flags;
6274 first->protocol = protocol;
6275
6276 #ifdef IXGBE_FCOE
6277 /* setup tx offload for FCoE */
6278 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6279 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6280 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6281 if (tso < 0)
6282 goto out_drop;
6283
6284 goto xmit_fcoe;
6285 }
6286
6287 #endif /* IXGBE_FCOE */
6288 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6289 if (tso < 0)
6290 goto out_drop;
6291 else if (!tso)
6292 ixgbe_tx_csum(tx_ring, first);
6293
6294 /* add the ATR filter if ATR is on */
6295 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6296 ixgbe_atr(tx_ring, first);
6297
6298 #ifdef IXGBE_FCOE
6299 xmit_fcoe:
6300 #endif /* IXGBE_FCOE */
6301 ixgbe_tx_map(tx_ring, first, hdr_len);
6302
6303 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6304
6305 return NETDEV_TX_OK;
6306
6307 out_drop:
6308 dev_kfree_skb_any(first->skb);
6309 first->skb = NULL;
6310
6311 return NETDEV_TX_OK;
6312 }
6313
ixgbe_xmit_frame(struct sk_buff * skb,struct net_device * netdev)6314 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6315 struct net_device *netdev)
6316 {
6317 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6318 struct ixgbe_ring *tx_ring;
6319
6320 if (skb->len <= 0) {
6321 dev_kfree_skb_any(skb);
6322 return NETDEV_TX_OK;
6323 }
6324
6325 /*
6326 * The minimum packet size for olinfo paylen is 17 so pad the skb
6327 * in order to meet this minimum size requirement.
6328 */
6329 if (skb->len < 17) {
6330 if (skb_padto(skb, 17))
6331 return NETDEV_TX_OK;
6332 skb->len = 17;
6333 }
6334
6335 tx_ring = adapter->tx_ring[skb->queue_mapping];
6336 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6337 }
6338
6339 /**
6340 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6341 * @netdev: network interface device structure
6342 * @p: pointer to an address structure
6343 *
6344 * Returns 0 on success, negative on failure
6345 **/
ixgbe_set_mac(struct net_device * netdev,void * p)6346 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6347 {
6348 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6349 struct ixgbe_hw *hw = &adapter->hw;
6350 struct sockaddr *addr = p;
6351
6352 if (!is_valid_ether_addr(addr->sa_data))
6353 return -EADDRNOTAVAIL;
6354
6355 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6356 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6357
6358 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6359 IXGBE_RAH_AV);
6360
6361 return 0;
6362 }
6363
6364 static int
ixgbe_mdio_read(struct net_device * netdev,int prtad,int devad,u16 addr)6365 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6366 {
6367 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6368 struct ixgbe_hw *hw = &adapter->hw;
6369 u16 value;
6370 int rc;
6371
6372 if (prtad != hw->phy.mdio.prtad)
6373 return -EINVAL;
6374 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6375 if (!rc)
6376 rc = value;
6377 return rc;
6378 }
6379
ixgbe_mdio_write(struct net_device * netdev,int prtad,int devad,u16 addr,u16 value)6380 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6381 u16 addr, u16 value)
6382 {
6383 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6384 struct ixgbe_hw *hw = &adapter->hw;
6385
6386 if (prtad != hw->phy.mdio.prtad)
6387 return -EINVAL;
6388 return hw->phy.ops.write_reg(hw, addr, devad, value);
6389 }
6390
ixgbe_ioctl(struct net_device * netdev,struct ifreq * req,int cmd)6391 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6392 {
6393 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6394
6395 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6396 }
6397
6398 /**
6399 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6400 * netdev->dev_addrs
6401 * @netdev: network interface device structure
6402 *
6403 * Returns non-zero on failure
6404 **/
ixgbe_add_sanmac_netdev(struct net_device * dev)6405 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6406 {
6407 int err = 0;
6408 struct ixgbe_adapter *adapter = netdev_priv(dev);
6409 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6410
6411 if (is_valid_ether_addr(mac->san_addr)) {
6412 rtnl_lock();
6413 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6414 rtnl_unlock();
6415 }
6416 return err;
6417 }
6418
6419 /**
6420 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6421 * netdev->dev_addrs
6422 * @netdev: network interface device structure
6423 *
6424 * Returns non-zero on failure
6425 **/
ixgbe_del_sanmac_netdev(struct net_device * dev)6426 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6427 {
6428 int err = 0;
6429 struct ixgbe_adapter *adapter = netdev_priv(dev);
6430 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6431
6432 if (is_valid_ether_addr(mac->san_addr)) {
6433 rtnl_lock();
6434 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6435 rtnl_unlock();
6436 }
6437 return err;
6438 }
6439
6440 #ifdef CONFIG_NET_POLL_CONTROLLER
6441 /*
6442 * Polling 'interrupt' - used by things like netconsole to send skbs
6443 * without having to re-enable interrupts. It's not called while
6444 * the interrupt routine is executing.
6445 */
ixgbe_netpoll(struct net_device * netdev)6446 static void ixgbe_netpoll(struct net_device *netdev)
6447 {
6448 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6449 int i;
6450
6451 /* if interface is down do nothing */
6452 if (test_bit(__IXGBE_DOWN, &adapter->state))
6453 return;
6454
6455 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6456 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6457 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6458 for (i = 0; i < num_q_vectors; i++) {
6459 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6460 ixgbe_msix_clean_rings(0, q_vector);
6461 }
6462 } else {
6463 ixgbe_intr(adapter->pdev->irq, netdev);
6464 }
6465 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6466 }
6467
6468 #endif
ixgbe_get_stats64(struct net_device * netdev,struct rtnl_link_stats64 * stats)6469 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6470 struct rtnl_link_stats64 *stats)
6471 {
6472 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6473 int i;
6474
6475 rcu_read_lock();
6476 for (i = 0; i < adapter->num_rx_queues; i++) {
6477 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6478 u64 bytes, packets;
6479 unsigned int start;
6480
6481 if (ring) {
6482 do {
6483 start = u64_stats_fetch_begin_bh(&ring->syncp);
6484 packets = ring->stats.packets;
6485 bytes = ring->stats.bytes;
6486 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6487 stats->rx_packets += packets;
6488 stats->rx_bytes += bytes;
6489 }
6490 }
6491
6492 for (i = 0; i < adapter->num_tx_queues; i++) {
6493 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6494 u64 bytes, packets;
6495 unsigned int start;
6496
6497 if (ring) {
6498 do {
6499 start = u64_stats_fetch_begin_bh(&ring->syncp);
6500 packets = ring->stats.packets;
6501 bytes = ring->stats.bytes;
6502 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6503 stats->tx_packets += packets;
6504 stats->tx_bytes += bytes;
6505 }
6506 }
6507 rcu_read_unlock();
6508 /* following stats updated by ixgbe_watchdog_task() */
6509 stats->multicast = netdev->stats.multicast;
6510 stats->rx_errors = netdev->stats.rx_errors;
6511 stats->rx_length_errors = netdev->stats.rx_length_errors;
6512 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6513 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6514 return stats;
6515 }
6516
6517 #ifdef CONFIG_IXGBE_DCB
6518 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6519 * #adapter: pointer to ixgbe_adapter
6520 * @tc: number of traffic classes currently enabled
6521 *
6522 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6523 * 802.1Q priority maps to a packet buffer that exists.
6524 */
ixgbe_validate_rtr(struct ixgbe_adapter * adapter,u8 tc)6525 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6526 {
6527 struct ixgbe_hw *hw = &adapter->hw;
6528 u32 reg, rsave;
6529 int i;
6530
6531 /* 82598 have a static priority to TC mapping that can not
6532 * be changed so no validation is needed.
6533 */
6534 if (hw->mac.type == ixgbe_mac_82598EB)
6535 return;
6536
6537 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6538 rsave = reg;
6539
6540 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6541 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6542
6543 /* If up2tc is out of bounds default to zero */
6544 if (up2tc > tc)
6545 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6546 }
6547
6548 if (reg != rsave)
6549 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6550
6551 return;
6552 }
6553
6554 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6555 * classes.
6556 *
6557 * @netdev: net device to configure
6558 * @tc: number of traffic classes to enable
6559 */
ixgbe_setup_tc(struct net_device * dev,u8 tc)6560 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6561 {
6562 struct ixgbe_adapter *adapter = netdev_priv(dev);
6563 struct ixgbe_hw *hw = &adapter->hw;
6564
6565 /* Multiple traffic classes requires multiple queues */
6566 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6567 e_err(drv, "Enable failed, needs MSI-X\n");
6568 return -EINVAL;
6569 }
6570
6571 /* Hardware supports up to 8 traffic classes */
6572 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6573 (hw->mac.type == ixgbe_mac_82598EB &&
6574 tc < MAX_TRAFFIC_CLASS))
6575 return -EINVAL;
6576
6577 /* Hardware has to reinitialize queues and interrupts to
6578 * match packet buffer alignment. Unfortunately, the
6579 * hardware is not flexible enough to do this dynamically.
6580 */
6581 if (netif_running(dev))
6582 ixgbe_close(dev);
6583 ixgbe_clear_interrupt_scheme(adapter);
6584
6585 if (tc) {
6586 netdev_set_num_tc(dev, tc);
6587 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6588 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6589 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6590
6591 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6592 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6593 } else {
6594 netdev_reset_tc(dev);
6595 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6596
6597 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6598 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6599
6600 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6601 adapter->dcb_cfg.pfc_mode_enable = false;
6602 }
6603
6604 ixgbe_init_interrupt_scheme(adapter);
6605 ixgbe_validate_rtr(adapter, tc);
6606 if (netif_running(dev))
6607 ixgbe_open(dev);
6608
6609 return 0;
6610 }
6611
6612 #endif /* CONFIG_IXGBE_DCB */
ixgbe_do_reset(struct net_device * netdev)6613 void ixgbe_do_reset(struct net_device *netdev)
6614 {
6615 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6616
6617 if (netif_running(netdev))
6618 ixgbe_reinit_locked(adapter);
6619 else
6620 ixgbe_reset(adapter);
6621 }
6622
ixgbe_fix_features(struct net_device * netdev,netdev_features_t features)6623 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6624 netdev_features_t features)
6625 {
6626 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6627
6628 #ifdef CONFIG_DCB
6629 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6630 features &= ~NETIF_F_HW_VLAN_RX;
6631 #endif
6632
6633 /* return error if RXHASH is being enabled when RSS is not supported */
6634 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6635 features &= ~NETIF_F_RXHASH;
6636
6637 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6638 if (!(features & NETIF_F_RXCSUM))
6639 features &= ~NETIF_F_LRO;
6640
6641 /* Turn off LRO if not RSC capable */
6642 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6643 features &= ~NETIF_F_LRO;
6644
6645
6646 return features;
6647 }
6648
ixgbe_set_features(struct net_device * netdev,netdev_features_t features)6649 static int ixgbe_set_features(struct net_device *netdev,
6650 netdev_features_t features)
6651 {
6652 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6653 netdev_features_t changed = netdev->features ^ features;
6654 bool need_reset = false;
6655
6656 /* Make sure RSC matches LRO, reset if change */
6657 if (!(features & NETIF_F_LRO)) {
6658 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6659 need_reset = true;
6660 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6661 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6662 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6663 if (adapter->rx_itr_setting == 1 ||
6664 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6665 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6666 need_reset = true;
6667 } else if ((changed ^ features) & NETIF_F_LRO) {
6668 e_info(probe, "rx-usecs set too low, "
6669 "disabling RSC\n");
6670 }
6671 }
6672
6673 /*
6674 * Check if Flow Director n-tuple support was enabled or disabled. If
6675 * the state changed, we need to reset.
6676 */
6677 if (!(features & NETIF_F_NTUPLE)) {
6678 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6679 /* turn off Flow Director, set ATR and reset */
6680 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6681 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6682 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6683 need_reset = true;
6684 }
6685 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6686 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6687 /* turn off ATR, enable perfect filters and reset */
6688 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6689 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6690 need_reset = true;
6691 }
6692
6693 if (changed & NETIF_F_RXALL)
6694 need_reset = true;
6695
6696 netdev->features = features;
6697 if (need_reset)
6698 ixgbe_do_reset(netdev);
6699
6700 return 0;
6701 }
6702
6703 static const struct net_device_ops ixgbe_netdev_ops = {
6704 .ndo_open = ixgbe_open,
6705 .ndo_stop = ixgbe_close,
6706 .ndo_start_xmit = ixgbe_xmit_frame,
6707 .ndo_select_queue = ixgbe_select_queue,
6708 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6709 .ndo_validate_addr = eth_validate_addr,
6710 .ndo_set_mac_address = ixgbe_set_mac,
6711 .ndo_change_mtu = ixgbe_change_mtu,
6712 .ndo_tx_timeout = ixgbe_tx_timeout,
6713 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6714 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6715 .ndo_do_ioctl = ixgbe_ioctl,
6716 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6717 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6718 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6719 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
6720 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6721 .ndo_get_stats64 = ixgbe_get_stats64,
6722 #ifdef CONFIG_IXGBE_DCB
6723 .ndo_setup_tc = ixgbe_setup_tc,
6724 #endif
6725 #ifdef CONFIG_NET_POLL_CONTROLLER
6726 .ndo_poll_controller = ixgbe_netpoll,
6727 #endif
6728 #ifdef IXGBE_FCOE
6729 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6730 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6731 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6732 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6733 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6734 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6735 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
6736 #endif /* IXGBE_FCOE */
6737 .ndo_set_features = ixgbe_set_features,
6738 .ndo_fix_features = ixgbe_fix_features,
6739 };
6740
ixgbe_probe_vf(struct ixgbe_adapter * adapter,const struct ixgbe_info * ii)6741 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6742 const struct ixgbe_info *ii)
6743 {
6744 #ifdef CONFIG_PCI_IOV
6745 struct ixgbe_hw *hw = &adapter->hw;
6746
6747 if (hw->mac.type == ixgbe_mac_82598EB)
6748 return;
6749
6750 /* The 82599 supports up to 64 VFs per physical function
6751 * but this implementation limits allocation to 63 so that
6752 * basic networking resources are still available to the
6753 * physical function
6754 */
6755 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6756 ixgbe_enable_sriov(adapter, ii);
6757 #endif /* CONFIG_PCI_IOV */
6758 }
6759
6760 /**
6761 * ixgbe_probe - Device Initialization Routine
6762 * @pdev: PCI device information struct
6763 * @ent: entry in ixgbe_pci_tbl
6764 *
6765 * Returns 0 on success, negative on failure
6766 *
6767 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6768 * The OS initialization, configuring of the adapter private structure,
6769 * and a hardware reset occur.
6770 **/
ixgbe_probe(struct pci_dev * pdev,const struct pci_device_id * ent)6771 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6772 const struct pci_device_id *ent)
6773 {
6774 struct net_device *netdev;
6775 struct ixgbe_adapter *adapter = NULL;
6776 struct ixgbe_hw *hw;
6777 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6778 static int cards_found;
6779 int i, err, pci_using_dac;
6780 u8 part_str[IXGBE_PBANUM_LENGTH];
6781 unsigned int indices = num_possible_cpus();
6782 #ifdef IXGBE_FCOE
6783 u16 device_caps;
6784 #endif
6785 u32 eec;
6786 u16 wol_cap;
6787
6788 /* Catch broken hardware that put the wrong VF device ID in
6789 * the PCIe SR-IOV capability.
6790 */
6791 if (pdev->is_virtfn) {
6792 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6793 pci_name(pdev), pdev->vendor, pdev->device);
6794 return -EINVAL;
6795 }
6796
6797 err = pci_enable_device_mem(pdev);
6798 if (err)
6799 return err;
6800
6801 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6802 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6803 pci_using_dac = 1;
6804 } else {
6805 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6806 if (err) {
6807 err = dma_set_coherent_mask(&pdev->dev,
6808 DMA_BIT_MASK(32));
6809 if (err) {
6810 dev_err(&pdev->dev,
6811 "No usable DMA configuration, aborting\n");
6812 goto err_dma;
6813 }
6814 }
6815 pci_using_dac = 0;
6816 }
6817
6818 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6819 IORESOURCE_MEM), ixgbe_driver_name);
6820 if (err) {
6821 dev_err(&pdev->dev,
6822 "pci_request_selected_regions failed 0x%x\n", err);
6823 goto err_pci_reg;
6824 }
6825
6826 pci_enable_pcie_error_reporting(pdev);
6827
6828 pci_set_master(pdev);
6829 pci_save_state(pdev);
6830
6831 #ifdef CONFIG_IXGBE_DCB
6832 indices *= MAX_TRAFFIC_CLASS;
6833 #endif
6834
6835 if (ii->mac == ixgbe_mac_82598EB)
6836 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6837 else
6838 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6839
6840 #ifdef IXGBE_FCOE
6841 indices += min_t(unsigned int, num_possible_cpus(),
6842 IXGBE_MAX_FCOE_INDICES);
6843 #endif
6844 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6845 if (!netdev) {
6846 err = -ENOMEM;
6847 goto err_alloc_etherdev;
6848 }
6849
6850 SET_NETDEV_DEV(netdev, &pdev->dev);
6851
6852 adapter = netdev_priv(netdev);
6853 pci_set_drvdata(pdev, adapter);
6854
6855 adapter->netdev = netdev;
6856 adapter->pdev = pdev;
6857 hw = &adapter->hw;
6858 hw->back = adapter;
6859 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
6860
6861 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6862 pci_resource_len(pdev, 0));
6863 if (!hw->hw_addr) {
6864 err = -EIO;
6865 goto err_ioremap;
6866 }
6867
6868 for (i = 1; i <= 5; i++) {
6869 if (pci_resource_len(pdev, i) == 0)
6870 continue;
6871 }
6872
6873 netdev->netdev_ops = &ixgbe_netdev_ops;
6874 ixgbe_set_ethtool_ops(netdev);
6875 netdev->watchdog_timeo = 5 * HZ;
6876 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6877
6878 adapter->bd_number = cards_found;
6879
6880 /* Setup hw api */
6881 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6882 hw->mac.type = ii->mac;
6883
6884 /* EEPROM */
6885 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6886 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6887 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6888 if (!(eec & (1 << 8)))
6889 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6890
6891 /* PHY */
6892 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6893 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6894 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6895 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6896 hw->phy.mdio.mmds = 0;
6897 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6898 hw->phy.mdio.dev = netdev;
6899 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6900 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6901
6902 ii->get_invariants(hw);
6903
6904 /* setup the private structure */
6905 err = ixgbe_sw_init(adapter);
6906 if (err)
6907 goto err_sw_init;
6908
6909 /* Make it possible the adapter to be woken up via WOL */
6910 switch (adapter->hw.mac.type) {
6911 case ixgbe_mac_82599EB:
6912 case ixgbe_mac_X540:
6913 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6914 break;
6915 default:
6916 break;
6917 }
6918
6919 /*
6920 * If there is a fan on this device and it has failed log the
6921 * failure.
6922 */
6923 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6924 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6925 if (esdp & IXGBE_ESDP_SDP1)
6926 e_crit(probe, "Fan has stopped, replace the adapter\n");
6927 }
6928
6929 if (allow_unsupported_sfp)
6930 hw->allow_unsupported_sfp = allow_unsupported_sfp;
6931
6932 /* reset_hw fills in the perm_addr as well */
6933 hw->phy.reset_if_overtemp = true;
6934 err = hw->mac.ops.reset_hw(hw);
6935 hw->phy.reset_if_overtemp = false;
6936 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6937 hw->mac.type == ixgbe_mac_82598EB) {
6938 err = 0;
6939 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6940 e_dev_err("failed to load because an unsupported SFP+ "
6941 "module type was detected.\n");
6942 e_dev_err("Reload the driver after installing a supported "
6943 "module.\n");
6944 goto err_sw_init;
6945 } else if (err) {
6946 e_dev_err("HW Init failed: %d\n", err);
6947 goto err_sw_init;
6948 }
6949
6950 ixgbe_probe_vf(adapter, ii);
6951
6952 netdev->features = NETIF_F_SG |
6953 NETIF_F_IP_CSUM |
6954 NETIF_F_IPV6_CSUM |
6955 NETIF_F_HW_VLAN_TX |
6956 NETIF_F_HW_VLAN_RX |
6957 NETIF_F_HW_VLAN_FILTER |
6958 NETIF_F_TSO |
6959 NETIF_F_TSO6 |
6960 NETIF_F_RXHASH |
6961 NETIF_F_RXCSUM;
6962
6963 netdev->hw_features = netdev->features;
6964
6965 switch (adapter->hw.mac.type) {
6966 case ixgbe_mac_82599EB:
6967 case ixgbe_mac_X540:
6968 netdev->features |= NETIF_F_SCTP_CSUM;
6969 netdev->hw_features |= NETIF_F_SCTP_CSUM |
6970 NETIF_F_NTUPLE;
6971 break;
6972 default:
6973 break;
6974 }
6975
6976 netdev->hw_features |= NETIF_F_RXALL;
6977
6978 netdev->vlan_features |= NETIF_F_TSO;
6979 netdev->vlan_features |= NETIF_F_TSO6;
6980 netdev->vlan_features |= NETIF_F_IP_CSUM;
6981 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6982 netdev->vlan_features |= NETIF_F_SG;
6983
6984 netdev->priv_flags |= IFF_UNICAST_FLT;
6985 netdev->priv_flags |= IFF_SUPP_NOFCS;
6986
6987 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6988 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6989 IXGBE_FLAG_DCB_ENABLED);
6990
6991 #ifdef CONFIG_IXGBE_DCB
6992 netdev->dcbnl_ops = &dcbnl_ops;
6993 #endif
6994
6995 #ifdef IXGBE_FCOE
6996 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6997 if (hw->mac.ops.get_device_caps) {
6998 hw->mac.ops.get_device_caps(hw, &device_caps);
6999 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7000 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7001 }
7002 }
7003 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7004 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7005 netdev->vlan_features |= NETIF_F_FSO;
7006 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7007 }
7008 #endif /* IXGBE_FCOE */
7009 if (pci_using_dac) {
7010 netdev->features |= NETIF_F_HIGHDMA;
7011 netdev->vlan_features |= NETIF_F_HIGHDMA;
7012 }
7013
7014 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7015 netdev->hw_features |= NETIF_F_LRO;
7016 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7017 netdev->features |= NETIF_F_LRO;
7018
7019 /* make sure the EEPROM is good */
7020 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7021 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7022 err = -EIO;
7023 goto err_sw_init;
7024 }
7025
7026 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7027 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7028
7029 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7030 e_dev_err("invalid MAC address\n");
7031 err = -EIO;
7032 goto err_sw_init;
7033 }
7034
7035 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7036 (unsigned long) adapter);
7037
7038 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7039 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7040
7041 err = ixgbe_init_interrupt_scheme(adapter);
7042 if (err)
7043 goto err_sw_init;
7044
7045 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7046 netdev->hw_features &= ~NETIF_F_RXHASH;
7047 netdev->features &= ~NETIF_F_RXHASH;
7048 }
7049
7050 /* WOL not supported for all but the following */
7051 adapter->wol = 0;
7052 switch (pdev->device) {
7053 case IXGBE_DEV_ID_82599_SFP:
7054 /* Only these subdevice supports WOL */
7055 switch (pdev->subsystem_device) {
7056 case IXGBE_SUBDEV_ID_82599_560FLR:
7057 /* only support first port */
7058 if (hw->bus.func != 0)
7059 break;
7060 case IXGBE_SUBDEV_ID_82599_SFP:
7061 adapter->wol = IXGBE_WUFC_MAG;
7062 break;
7063 }
7064 break;
7065 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7066 /* All except this subdevice support WOL */
7067 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7068 adapter->wol = IXGBE_WUFC_MAG;
7069 break;
7070 case IXGBE_DEV_ID_82599_KX4:
7071 adapter->wol = IXGBE_WUFC_MAG;
7072 break;
7073 case IXGBE_DEV_ID_X540T:
7074 case IXGBE_DEV_ID_X540T1:
7075 /* Check eeprom to see if it is enabled */
7076 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7077 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7078
7079 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7080 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7081 (hw->bus.func == 0)))
7082 adapter->wol = IXGBE_WUFC_MAG;
7083 break;
7084 }
7085 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7086
7087 /* save off EEPROM version number */
7088 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7089 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7090
7091 /* pick up the PCI bus settings for reporting later */
7092 hw->mac.ops.get_bus_info(hw);
7093
7094 /* print bus type/speed/width info */
7095 e_dev_info("(PCI Express:%s:%s) %pM\n",
7096 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7097 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7098 "Unknown"),
7099 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7100 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7101 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7102 "Unknown"),
7103 netdev->dev_addr);
7104
7105 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7106 if (err)
7107 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7108 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7109 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7110 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7111 part_str);
7112 else
7113 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7114 hw->mac.type, hw->phy.type, part_str);
7115
7116 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7117 e_dev_warn("PCI-Express bandwidth available for this card is "
7118 "not sufficient for optimal performance.\n");
7119 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7120 "is required.\n");
7121 }
7122
7123 /* reset the hardware with the new settings */
7124 err = hw->mac.ops.start_hw(hw);
7125 if (err == IXGBE_ERR_EEPROM_VERSION) {
7126 /* We are running on a pre-production device, log a warning */
7127 e_dev_warn("This device is a pre-production adapter/LOM. "
7128 "Please be aware there may be issues associated "
7129 "with your hardware. If you are experiencing "
7130 "problems please contact your Intel or hardware "
7131 "representative who provided you with this "
7132 "hardware.\n");
7133 }
7134 strcpy(netdev->name, "eth%d");
7135 err = register_netdev(netdev);
7136 if (err)
7137 goto err_register;
7138
7139 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7140 if (hw->mac.ops.disable_tx_laser &&
7141 ((hw->phy.multispeed_fiber) ||
7142 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7143 (hw->mac.type == ixgbe_mac_82599EB))))
7144 hw->mac.ops.disable_tx_laser(hw);
7145
7146 /* carrier off reporting is important to ethtool even BEFORE open */
7147 netif_carrier_off(netdev);
7148
7149 #ifdef CONFIG_IXGBE_DCA
7150 if (dca_add_requester(&pdev->dev) == 0) {
7151 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7152 ixgbe_setup_dca(adapter);
7153 }
7154 #endif
7155 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7156 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7157 for (i = 0; i < adapter->num_vfs; i++)
7158 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7159 }
7160
7161 /* firmware requires driver version to be 0xFFFFFFFF
7162 * since os does not support feature
7163 */
7164 if (hw->mac.ops.set_fw_drv_ver)
7165 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7166 0xFF);
7167
7168 /* add san mac addr to netdev */
7169 ixgbe_add_sanmac_netdev(netdev);
7170
7171 e_dev_info("%s\n", ixgbe_default_device_descr);
7172 cards_found++;
7173 return 0;
7174
7175 err_register:
7176 ixgbe_release_hw_control(adapter);
7177 ixgbe_clear_interrupt_scheme(adapter);
7178 err_sw_init:
7179 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7180 ixgbe_disable_sriov(adapter);
7181 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7182 iounmap(hw->hw_addr);
7183 err_ioremap:
7184 free_netdev(netdev);
7185 err_alloc_etherdev:
7186 pci_release_selected_regions(pdev,
7187 pci_select_bars(pdev, IORESOURCE_MEM));
7188 err_pci_reg:
7189 err_dma:
7190 pci_disable_device(pdev);
7191 return err;
7192 }
7193
7194 /**
7195 * ixgbe_remove - Device Removal Routine
7196 * @pdev: PCI device information struct
7197 *
7198 * ixgbe_remove is called by the PCI subsystem to alert the driver
7199 * that it should release a PCI device. The could be caused by a
7200 * Hot-Plug event, or because the driver is going to be removed from
7201 * memory.
7202 **/
ixgbe_remove(struct pci_dev * pdev)7203 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7204 {
7205 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7206 struct net_device *netdev = adapter->netdev;
7207
7208 set_bit(__IXGBE_DOWN, &adapter->state);
7209 cancel_work_sync(&adapter->service_task);
7210
7211 #ifdef CONFIG_IXGBE_DCA
7212 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7213 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7214 dca_remove_requester(&pdev->dev);
7215 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7216 }
7217
7218 #endif
7219 #ifdef IXGBE_FCOE
7220 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7221 ixgbe_cleanup_fcoe(adapter);
7222
7223 #endif /* IXGBE_FCOE */
7224
7225 /* remove the added san mac */
7226 ixgbe_del_sanmac_netdev(netdev);
7227
7228 if (netdev->reg_state == NETREG_REGISTERED)
7229 unregister_netdev(netdev);
7230
7231 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7232 if (!(ixgbe_check_vf_assignment(adapter)))
7233 ixgbe_disable_sriov(adapter);
7234 else
7235 e_dev_warn("Unloading driver while VFs are assigned "
7236 "- VFs will not be deallocated\n");
7237 }
7238
7239 ixgbe_clear_interrupt_scheme(adapter);
7240
7241 ixgbe_release_hw_control(adapter);
7242
7243 #ifdef CONFIG_DCB
7244 kfree(adapter->ixgbe_ieee_pfc);
7245 kfree(adapter->ixgbe_ieee_ets);
7246
7247 #endif
7248 iounmap(adapter->hw.hw_addr);
7249 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7250 IORESOURCE_MEM));
7251
7252 e_dev_info("complete\n");
7253
7254 free_netdev(netdev);
7255
7256 pci_disable_pcie_error_reporting(pdev);
7257
7258 pci_disable_device(pdev);
7259 }
7260
7261 /**
7262 * ixgbe_io_error_detected - called when PCI error is detected
7263 * @pdev: Pointer to PCI device
7264 * @state: The current pci connection state
7265 *
7266 * This function is called after a PCI bus error affecting
7267 * this device has been detected.
7268 */
ixgbe_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7269 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7270 pci_channel_state_t state)
7271 {
7272 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7273 struct net_device *netdev = adapter->netdev;
7274
7275 #ifdef CONFIG_PCI_IOV
7276 struct pci_dev *bdev, *vfdev;
7277 u32 dw0, dw1, dw2, dw3;
7278 int vf, pos;
7279 u16 req_id, pf_func;
7280
7281 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7282 adapter->num_vfs == 0)
7283 goto skip_bad_vf_detection;
7284
7285 bdev = pdev->bus->self;
7286 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7287 bdev = bdev->bus->self;
7288
7289 if (!bdev)
7290 goto skip_bad_vf_detection;
7291
7292 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7293 if (!pos)
7294 goto skip_bad_vf_detection;
7295
7296 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7297 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7298 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7299 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7300
7301 req_id = dw1 >> 16;
7302 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7303 if (!(req_id & 0x0080))
7304 goto skip_bad_vf_detection;
7305
7306 pf_func = req_id & 0x01;
7307 if ((pf_func & 1) == (pdev->devfn & 1)) {
7308 unsigned int device_id;
7309
7310 vf = (req_id & 0x7F) >> 1;
7311 e_dev_err("VF %d has caused a PCIe error\n", vf);
7312 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7313 "%8.8x\tdw3: %8.8x\n",
7314 dw0, dw1, dw2, dw3);
7315 switch (adapter->hw.mac.type) {
7316 case ixgbe_mac_82599EB:
7317 device_id = IXGBE_82599_VF_DEVICE_ID;
7318 break;
7319 case ixgbe_mac_X540:
7320 device_id = IXGBE_X540_VF_DEVICE_ID;
7321 break;
7322 default:
7323 device_id = 0;
7324 break;
7325 }
7326
7327 /* Find the pci device of the offending VF */
7328 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7329 while (vfdev) {
7330 if (vfdev->devfn == (req_id & 0xFF))
7331 break;
7332 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7333 device_id, vfdev);
7334 }
7335 /*
7336 * There's a slim chance the VF could have been hot plugged,
7337 * so if it is no longer present we don't need to issue the
7338 * VFLR. Just clean up the AER in that case.
7339 */
7340 if (vfdev) {
7341 e_dev_err("Issuing VFLR to VF %d\n", vf);
7342 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7343 }
7344
7345 pci_cleanup_aer_uncorrect_error_status(pdev);
7346 }
7347
7348 /*
7349 * Even though the error may have occurred on the other port
7350 * we still need to increment the vf error reference count for
7351 * both ports because the I/O resume function will be called
7352 * for both of them.
7353 */
7354 adapter->vferr_refcount++;
7355
7356 return PCI_ERS_RESULT_RECOVERED;
7357
7358 skip_bad_vf_detection:
7359 #endif /* CONFIG_PCI_IOV */
7360 netif_device_detach(netdev);
7361
7362 if (state == pci_channel_io_perm_failure)
7363 return PCI_ERS_RESULT_DISCONNECT;
7364
7365 if (netif_running(netdev))
7366 ixgbe_down(adapter);
7367 pci_disable_device(pdev);
7368
7369 /* Request a slot reset. */
7370 return PCI_ERS_RESULT_NEED_RESET;
7371 }
7372
7373 /**
7374 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7375 * @pdev: Pointer to PCI device
7376 *
7377 * Restart the card from scratch, as if from a cold-boot.
7378 */
ixgbe_io_slot_reset(struct pci_dev * pdev)7379 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7380 {
7381 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7382 pci_ers_result_t result;
7383 int err;
7384
7385 if (pci_enable_device_mem(pdev)) {
7386 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7387 result = PCI_ERS_RESULT_DISCONNECT;
7388 } else {
7389 pci_set_master(pdev);
7390 pci_restore_state(pdev);
7391 pci_save_state(pdev);
7392
7393 pci_wake_from_d3(pdev, false);
7394
7395 ixgbe_reset(adapter);
7396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7397 result = PCI_ERS_RESULT_RECOVERED;
7398 }
7399
7400 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7401 if (err) {
7402 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7403 "failed 0x%0x\n", err);
7404 /* non-fatal, continue */
7405 }
7406
7407 return result;
7408 }
7409
7410 /**
7411 * ixgbe_io_resume - called when traffic can start flowing again.
7412 * @pdev: Pointer to PCI device
7413 *
7414 * This callback is called when the error recovery driver tells us that
7415 * its OK to resume normal operation.
7416 */
ixgbe_io_resume(struct pci_dev * pdev)7417 static void ixgbe_io_resume(struct pci_dev *pdev)
7418 {
7419 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7420 struct net_device *netdev = adapter->netdev;
7421
7422 #ifdef CONFIG_PCI_IOV
7423 if (adapter->vferr_refcount) {
7424 e_info(drv, "Resuming after VF err\n");
7425 adapter->vferr_refcount--;
7426 return;
7427 }
7428
7429 #endif
7430 if (netif_running(netdev))
7431 ixgbe_up(adapter);
7432
7433 netif_device_attach(netdev);
7434 }
7435
7436 static struct pci_error_handlers ixgbe_err_handler = {
7437 .error_detected = ixgbe_io_error_detected,
7438 .slot_reset = ixgbe_io_slot_reset,
7439 .resume = ixgbe_io_resume,
7440 };
7441
7442 static struct pci_driver ixgbe_driver = {
7443 .name = ixgbe_driver_name,
7444 .id_table = ixgbe_pci_tbl,
7445 .probe = ixgbe_probe,
7446 .remove = __devexit_p(ixgbe_remove),
7447 #ifdef CONFIG_PM
7448 .suspend = ixgbe_suspend,
7449 .resume = ixgbe_resume,
7450 #endif
7451 .shutdown = ixgbe_shutdown,
7452 .err_handler = &ixgbe_err_handler
7453 };
7454
7455 /**
7456 * ixgbe_init_module - Driver Registration Routine
7457 *
7458 * ixgbe_init_module is the first routine called when the driver is
7459 * loaded. All it does is register with the PCI subsystem.
7460 **/
ixgbe_init_module(void)7461 static int __init ixgbe_init_module(void)
7462 {
7463 int ret;
7464 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7465 pr_info("%s\n", ixgbe_copyright);
7466
7467 #ifdef CONFIG_IXGBE_DCA
7468 dca_register_notify(&dca_notifier);
7469 #endif
7470
7471 ret = pci_register_driver(&ixgbe_driver);
7472 return ret;
7473 }
7474
7475 module_init(ixgbe_init_module);
7476
7477 /**
7478 * ixgbe_exit_module - Driver Exit Cleanup Routine
7479 *
7480 * ixgbe_exit_module is called just before the driver is removed
7481 * from memory.
7482 **/
ixgbe_exit_module(void)7483 static void __exit ixgbe_exit_module(void)
7484 {
7485 #ifdef CONFIG_IXGBE_DCA
7486 dca_unregister_notify(&dca_notifier);
7487 #endif
7488 pci_unregister_driver(&ixgbe_driver);
7489 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7490 }
7491
7492 #ifdef CONFIG_IXGBE_DCA
ixgbe_notify_dca(struct notifier_block * nb,unsigned long event,void * p)7493 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7494 void *p)
7495 {
7496 int ret_val;
7497
7498 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7499 __ixgbe_notify_dca);
7500
7501 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7502 }
7503
7504 #endif /* CONFIG_IXGBE_DCA */
7505
7506 module_exit(ixgbe_exit_module);
7507
7508 /* ixgbe_main.c */
7509