1 /******************************************************************************* 2 Header File to describe the DMA descriptors. 3 Enhanced descriptors have been in case of DWMAC1000 Cores. 4 5 This program is free software; you can redistribute it and/or modify it 6 under the terms and conditions of the GNU General Public License, 7 version 2, as published by the Free Software Foundation. 8 9 This program is distributed in the hope it will be useful, but WITHOUT 10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 more details. 13 14 You should have received a copy of the GNU General Public License along with 15 this program; if not, write to the Free Software Foundation, Inc., 16 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 22 *******************************************************************************/ 23 struct dma_desc { 24 /* Receive descriptor */ 25 union { 26 struct { 27 /* RDES0 */ 28 u32 payload_csum_error:1; 29 u32 crc_error:1; 30 u32 dribbling:1; 31 u32 mii_error:1; 32 u32 receive_watchdog:1; 33 u32 frame_type:1; 34 u32 collision:1; 35 u32 ipc_csum_error:1; 36 u32 last_descriptor:1; 37 u32 first_descriptor:1; 38 u32 vlan_tag:1; 39 u32 overflow_error:1; 40 u32 length_error:1; 41 u32 sa_filter_fail:1; 42 u32 descriptor_error:1; 43 u32 error_summary:1; 44 u32 frame_length:14; 45 u32 da_filter_fail:1; 46 u32 own:1; 47 /* RDES1 */ 48 u32 buffer1_size:11; 49 u32 buffer2_size:11; 50 u32 reserved1:2; 51 u32 second_address_chained:1; 52 u32 end_ring:1; 53 u32 reserved2:5; 54 u32 disable_ic:1; 55 56 } rx; 57 struct { 58 /* RDES0 */ 59 u32 payload_csum_error:1; 60 u32 crc_error:1; 61 u32 dribbling:1; 62 u32 error_gmii:1; 63 u32 receive_watchdog:1; 64 u32 frame_type:1; 65 u32 late_collision:1; 66 u32 ipc_csum_error:1; 67 u32 last_descriptor:1; 68 u32 first_descriptor:1; 69 u32 vlan_tag:1; 70 u32 overflow_error:1; 71 u32 length_error:1; 72 u32 sa_filter_fail:1; 73 u32 descriptor_error:1; 74 u32 error_summary:1; 75 u32 frame_length:14; 76 u32 da_filter_fail:1; 77 u32 own:1; 78 /* RDES1 */ 79 u32 buffer1_size:13; 80 u32 reserved1:1; 81 u32 second_address_chained:1; 82 u32 end_ring:1; 83 u32 buffer2_size:13; 84 u32 reserved2:2; 85 u32 disable_ic:1; 86 } erx; /* -- enhanced -- */ 87 88 /* Transmit descriptor */ 89 struct { 90 /* TDES0 */ 91 u32 deferred:1; 92 u32 underflow_error:1; 93 u32 excessive_deferral:1; 94 u32 collision_count:4; 95 u32 vlan_frame:1; 96 u32 excessive_collisions:1; 97 u32 late_collision:1; 98 u32 no_carrier:1; 99 u32 loss_carrier:1; 100 u32 payload_error:1; 101 u32 frame_flushed:1; 102 u32 jabber_timeout:1; 103 u32 error_summary:1; 104 u32 ip_header_error:1; 105 u32 time_stamp_status:1; 106 u32 reserved1:13; 107 u32 own:1; 108 /* TDES1 */ 109 u32 buffer1_size:11; 110 u32 buffer2_size:11; 111 u32 time_stamp_enable:1; 112 u32 disable_padding:1; 113 u32 second_address_chained:1; 114 u32 end_ring:1; 115 u32 crc_disable:1; 116 u32 checksum_insertion:2; 117 u32 first_segment:1; 118 u32 last_segment:1; 119 u32 interrupt:1; 120 } tx; 121 struct { 122 /* TDES0 */ 123 u32 deferred:1; 124 u32 underflow_error:1; 125 u32 excessive_deferral:1; 126 u32 collision_count:4; 127 u32 vlan_frame:1; 128 u32 excessive_collisions:1; 129 u32 late_collision:1; 130 u32 no_carrier:1; 131 u32 loss_carrier:1; 132 u32 payload_error:1; 133 u32 frame_flushed:1; 134 u32 jabber_timeout:1; 135 u32 error_summary:1; 136 u32 ip_header_error:1; 137 u32 time_stamp_status:1; 138 u32 reserved1:2; 139 u32 second_address_chained:1; 140 u32 end_ring:1; 141 u32 checksum_insertion:2; 142 u32 reserved2:1; 143 u32 time_stamp_enable:1; 144 u32 disable_padding:1; 145 u32 crc_disable:1; 146 u32 first_segment:1; 147 u32 last_segment:1; 148 u32 interrupt:1; 149 u32 own:1; 150 /* TDES1 */ 151 u32 buffer1_size:13; 152 u32 reserved3:3; 153 u32 buffer2_size:13; 154 u32 reserved4:3; 155 } etx; /* -- enhanced -- */ 156 } des01; 157 unsigned int des2; 158 unsigned int des3; 159 }; 160 161 /* Transmit checksum insertion control */ 162 enum tdes_csum_insertion { 163 cic_disabled = 0, /* Checksum Insertion Control */ 164 cic_only_ip = 1, /* Only IP header */ 165 cic_no_pseudoheader = 2, /* IP header but pseudoheader 166 * is not calculated */ 167 cic_full = 3, /* IP header and pseudoheader */ 168 }; 169