1 /* 2 * Broadcom AMBA Interconnect definitions. 3 * 4 * Copyright (C) 1999-2013, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * $Id: aidmp.h 385510 2013-02-15 21:02:07Z $ 25 */ 26 27 #ifndef _AIDMP_H 28 #define _AIDMP_H 29 30 /* Manufacturer Ids */ 31 #define MFGID_ARM 0x43b 32 #define MFGID_BRCM 0x4bf 33 #define MFGID_MIPS 0x4a7 34 35 /* Component Classes */ 36 #define CC_SIM 0 37 #define CC_EROM 1 38 #define CC_CORESIGHT 9 39 #define CC_VERIF 0xb 40 #define CC_OPTIMO 0xd 41 #define CC_GEN 0xe 42 #define CC_PRIMECELL 0xf 43 44 /* Enumeration ROM registers */ 45 #define ER_EROMENTRY 0x000 46 #define ER_REMAPCONTROL 0xe00 47 #define ER_REMAPSELECT 0xe04 48 #define ER_MASTERSELECT 0xe10 49 #define ER_ITCR 0xf00 50 #define ER_ITIP 0xf04 51 52 /* Erom entries */ 53 #define ER_TAG 0xe 54 #define ER_TAG1 0x6 55 #define ER_VALID 1 56 #define ER_CI 0 57 #define ER_MP 2 58 #define ER_ADD 4 59 #define ER_END 0xe 60 #define ER_BAD 0xffffffff 61 62 /* EROM CompIdentA */ 63 #define CIA_MFG_MASK 0xfff00000 64 #define CIA_MFG_SHIFT 20 65 #define CIA_CID_MASK 0x000fff00 66 #define CIA_CID_SHIFT 8 67 #define CIA_CCL_MASK 0x000000f0 68 #define CIA_CCL_SHIFT 4 69 70 /* EROM CompIdentB */ 71 #define CIB_REV_MASK 0xff000000 72 #define CIB_REV_SHIFT 24 73 #define CIB_NSW_MASK 0x00f80000 74 #define CIB_NSW_SHIFT 19 75 #define CIB_NMW_MASK 0x0007c000 76 #define CIB_NMW_SHIFT 14 77 #define CIB_NSP_MASK 0x00003e00 78 #define CIB_NSP_SHIFT 9 79 #define CIB_NMP_MASK 0x000001f0 80 #define CIB_NMP_SHIFT 4 81 82 /* EROM MasterPortDesc */ 83 #define MPD_MUI_MASK 0x0000ff00 84 #define MPD_MUI_SHIFT 8 85 #define MPD_MP_MASK 0x000000f0 86 #define MPD_MP_SHIFT 4 87 88 /* EROM AddrDesc */ 89 #define AD_ADDR_MASK 0xfffff000 90 #define AD_SP_MASK 0x00000f00 91 #define AD_SP_SHIFT 8 92 #define AD_ST_MASK 0x000000c0 93 #define AD_ST_SHIFT 6 94 #define AD_ST_SLAVE 0x00000000 95 #define AD_ST_BRIDGE 0x00000040 96 #define AD_ST_SWRAP 0x00000080 97 #define AD_ST_MWRAP 0x000000c0 98 #define AD_SZ_MASK 0x00000030 99 #define AD_SZ_SHIFT 4 100 #define AD_SZ_4K 0x00000000 101 #define AD_SZ_8K 0x00000010 102 #define AD_SZ_16K 0x00000020 103 #define AD_SZ_SZD 0x00000030 104 #define AD_AG32 0x00000008 105 #define AD_ADDR_ALIGN 0x00000fff 106 #define AD_SZ_BASE 0x00001000 /* 4KB */ 107 108 /* EROM SizeDesc */ 109 #define SD_SZ_MASK 0xfffff000 110 #define SD_SG32 0x00000008 111 #define SD_SZ_ALIGN 0x00000fff 112 113 114 #ifndef _LANGUAGE_ASSEMBLY 115 116 typedef volatile struct _aidmp { 117 uint32 oobselina30; /* 0x000 */ 118 uint32 oobselina74; /* 0x004 */ 119 uint32 PAD[6]; 120 uint32 oobselinb30; /* 0x020 */ 121 uint32 oobselinb74; /* 0x024 */ 122 uint32 PAD[6]; 123 uint32 oobselinc30; /* 0x040 */ 124 uint32 oobselinc74; /* 0x044 */ 125 uint32 PAD[6]; 126 uint32 oobselind30; /* 0x060 */ 127 uint32 oobselind74; /* 0x064 */ 128 uint32 PAD[38]; 129 uint32 oobselouta30; /* 0x100 */ 130 uint32 oobselouta74; /* 0x104 */ 131 uint32 PAD[6]; 132 uint32 oobseloutb30; /* 0x120 */ 133 uint32 oobseloutb74; /* 0x124 */ 134 uint32 PAD[6]; 135 uint32 oobseloutc30; /* 0x140 */ 136 uint32 oobseloutc74; /* 0x144 */ 137 uint32 PAD[6]; 138 uint32 oobseloutd30; /* 0x160 */ 139 uint32 oobseloutd74; /* 0x164 */ 140 uint32 PAD[38]; 141 uint32 oobsynca; /* 0x200 */ 142 uint32 oobseloutaen; /* 0x204 */ 143 uint32 PAD[6]; 144 uint32 oobsyncb; /* 0x220 */ 145 uint32 oobseloutben; /* 0x224 */ 146 uint32 PAD[6]; 147 uint32 oobsyncc; /* 0x240 */ 148 uint32 oobseloutcen; /* 0x244 */ 149 uint32 PAD[6]; 150 uint32 oobsyncd; /* 0x260 */ 151 uint32 oobseloutden; /* 0x264 */ 152 uint32 PAD[38]; 153 uint32 oobaextwidth; /* 0x300 */ 154 uint32 oobainwidth; /* 0x304 */ 155 uint32 oobaoutwidth; /* 0x308 */ 156 uint32 PAD[5]; 157 uint32 oobbextwidth; /* 0x320 */ 158 uint32 oobbinwidth; /* 0x324 */ 159 uint32 oobboutwidth; /* 0x328 */ 160 uint32 PAD[5]; 161 uint32 oobcextwidth; /* 0x340 */ 162 uint32 oobcinwidth; /* 0x344 */ 163 uint32 oobcoutwidth; /* 0x348 */ 164 uint32 PAD[5]; 165 uint32 oobdextwidth; /* 0x360 */ 166 uint32 oobdinwidth; /* 0x364 */ 167 uint32 oobdoutwidth; /* 0x368 */ 168 uint32 PAD[37]; 169 uint32 ioctrlset; /* 0x400 */ 170 uint32 ioctrlclear; /* 0x404 */ 171 uint32 ioctrl; /* 0x408 */ 172 uint32 PAD[61]; 173 uint32 iostatus; /* 0x500 */ 174 uint32 PAD[127]; 175 uint32 ioctrlwidth; /* 0x700 */ 176 uint32 iostatuswidth; /* 0x704 */ 177 uint32 PAD[62]; 178 uint32 resetctrl; /* 0x800 */ 179 uint32 resetstatus; /* 0x804 */ 180 uint32 resetreadid; /* 0x808 */ 181 uint32 resetwriteid; /* 0x80c */ 182 uint32 PAD[60]; 183 uint32 errlogctrl; /* 0x900 */ 184 uint32 errlogdone; /* 0x904 */ 185 uint32 errlogstatus; /* 0x908 */ 186 uint32 errlogaddrlo; /* 0x90c */ 187 uint32 errlogaddrhi; /* 0x910 */ 188 uint32 errlogid; /* 0x914 */ 189 uint32 errloguser; /* 0x918 */ 190 uint32 errlogflags; /* 0x91c */ 191 uint32 PAD[56]; 192 uint32 intstatus; /* 0xa00 */ 193 uint32 PAD[255]; 194 uint32 config; /* 0xe00 */ 195 uint32 PAD[63]; 196 uint32 itcr; /* 0xf00 */ 197 uint32 PAD[3]; 198 uint32 itipooba; /* 0xf10 */ 199 uint32 itipoobb; /* 0xf14 */ 200 uint32 itipoobc; /* 0xf18 */ 201 uint32 itipoobd; /* 0xf1c */ 202 uint32 PAD[4]; 203 uint32 itipoobaout; /* 0xf30 */ 204 uint32 itipoobbout; /* 0xf34 */ 205 uint32 itipoobcout; /* 0xf38 */ 206 uint32 itipoobdout; /* 0xf3c */ 207 uint32 PAD[4]; 208 uint32 itopooba; /* 0xf50 */ 209 uint32 itopoobb; /* 0xf54 */ 210 uint32 itopoobc; /* 0xf58 */ 211 uint32 itopoobd; /* 0xf5c */ 212 uint32 PAD[4]; 213 uint32 itopoobain; /* 0xf70 */ 214 uint32 itopoobbin; /* 0xf74 */ 215 uint32 itopoobcin; /* 0xf78 */ 216 uint32 itopoobdin; /* 0xf7c */ 217 uint32 PAD[4]; 218 uint32 itopreset; /* 0xf90 */ 219 uint32 PAD[15]; 220 uint32 peripherialid4; /* 0xfd0 */ 221 uint32 peripherialid5; /* 0xfd4 */ 222 uint32 peripherialid6; /* 0xfd8 */ 223 uint32 peripherialid7; /* 0xfdc */ 224 uint32 peripherialid0; /* 0xfe0 */ 225 uint32 peripherialid1; /* 0xfe4 */ 226 uint32 peripherialid2; /* 0xfe8 */ 227 uint32 peripherialid3; /* 0xfec */ 228 uint32 componentid0; /* 0xff0 */ 229 uint32 componentid1; /* 0xff4 */ 230 uint32 componentid2; /* 0xff8 */ 231 uint32 componentid3; /* 0xffc */ 232 } aidmp_t; 233 234 #endif /* _LANGUAGE_ASSEMBLY */ 235 236 /* Out-of-band Router registers */ 237 #define OOB_BUSCONFIG 0x020 238 #define OOB_STATUSA 0x100 239 #define OOB_STATUSB 0x104 240 #define OOB_STATUSC 0x108 241 #define OOB_STATUSD 0x10c 242 #define OOB_ENABLEA0 0x200 243 #define OOB_ENABLEA1 0x204 244 #define OOB_ENABLEA2 0x208 245 #define OOB_ENABLEA3 0x20c 246 #define OOB_ENABLEB0 0x280 247 #define OOB_ENABLEB1 0x284 248 #define OOB_ENABLEB2 0x288 249 #define OOB_ENABLEB3 0x28c 250 #define OOB_ENABLEC0 0x300 251 #define OOB_ENABLEC1 0x304 252 #define OOB_ENABLEC2 0x308 253 #define OOB_ENABLEC3 0x30c 254 #define OOB_ENABLED0 0x380 255 #define OOB_ENABLED1 0x384 256 #define OOB_ENABLED2 0x388 257 #define OOB_ENABLED3 0x38c 258 #define OOB_ITCR 0xf00 259 #define OOB_ITIPOOBA 0xf10 260 #define OOB_ITIPOOBB 0xf14 261 #define OOB_ITIPOOBC 0xf18 262 #define OOB_ITIPOOBD 0xf1c 263 #define OOB_ITOPOOBA 0xf30 264 #define OOB_ITOPOOBB 0xf34 265 #define OOB_ITOPOOBC 0xf38 266 #define OOB_ITOPOOBD 0xf3c 267 268 /* DMP wrapper registers */ 269 #define AI_OOBSELINA30 0x000 270 #define AI_OOBSELINA74 0x004 271 #define AI_OOBSELINB30 0x020 272 #define AI_OOBSELINB74 0x024 273 #define AI_OOBSELINC30 0x040 274 #define AI_OOBSELINC74 0x044 275 #define AI_OOBSELIND30 0x060 276 #define AI_OOBSELIND74 0x064 277 #define AI_OOBSELOUTA30 0x100 278 #define AI_OOBSELOUTA74 0x104 279 #define AI_OOBSELOUTB30 0x120 280 #define AI_OOBSELOUTB74 0x124 281 #define AI_OOBSELOUTC30 0x140 282 #define AI_OOBSELOUTC74 0x144 283 #define AI_OOBSELOUTD30 0x160 284 #define AI_OOBSELOUTD74 0x164 285 #define AI_OOBSYNCA 0x200 286 #define AI_OOBSELOUTAEN 0x204 287 #define AI_OOBSYNCB 0x220 288 #define AI_OOBSELOUTBEN 0x224 289 #define AI_OOBSYNCC 0x240 290 #define AI_OOBSELOUTCEN 0x244 291 #define AI_OOBSYNCD 0x260 292 #define AI_OOBSELOUTDEN 0x264 293 #define AI_OOBAEXTWIDTH 0x300 294 #define AI_OOBAINWIDTH 0x304 295 #define AI_OOBAOUTWIDTH 0x308 296 #define AI_OOBBEXTWIDTH 0x320 297 #define AI_OOBBINWIDTH 0x324 298 #define AI_OOBBOUTWIDTH 0x328 299 #define AI_OOBCEXTWIDTH 0x340 300 #define AI_OOBCINWIDTH 0x344 301 #define AI_OOBCOUTWIDTH 0x348 302 #define AI_OOBDEXTWIDTH 0x360 303 #define AI_OOBDINWIDTH 0x364 304 #define AI_OOBDOUTWIDTH 0x368 305 306 307 #define AI_IOCTRLSET 0x400 308 #define AI_IOCTRLCLEAR 0x404 309 #define AI_IOCTRL 0x408 310 #define AI_IOSTATUS 0x500 311 #define AI_RESETCTRL 0x800 312 #define AI_RESETSTATUS 0x804 313 314 #define AI_IOCTRLWIDTH 0x700 315 #define AI_IOSTATUSWIDTH 0x704 316 317 #define AI_RESETREADID 0x808 318 #define AI_RESETWRITEID 0x80c 319 #define AI_ERRLOGCTRL 0xa00 320 #define AI_ERRLOGDONE 0xa04 321 #define AI_ERRLOGSTATUS 0xa08 322 #define AI_ERRLOGADDRLO 0xa0c 323 #define AI_ERRLOGADDRHI 0xa10 324 #define AI_ERRLOGID 0xa14 325 #define AI_ERRLOGUSER 0xa18 326 #define AI_ERRLOGFLAGS 0xa1c 327 #define AI_INTSTATUS 0xa00 328 #define AI_CONFIG 0xe00 329 #define AI_ITCR 0xf00 330 #define AI_ITIPOOBA 0xf10 331 #define AI_ITIPOOBB 0xf14 332 #define AI_ITIPOOBC 0xf18 333 #define AI_ITIPOOBD 0xf1c 334 #define AI_ITIPOOBAOUT 0xf30 335 #define AI_ITIPOOBBOUT 0xf34 336 #define AI_ITIPOOBCOUT 0xf38 337 #define AI_ITIPOOBDOUT 0xf3c 338 #define AI_ITOPOOBA 0xf50 339 #define AI_ITOPOOBB 0xf54 340 #define AI_ITOPOOBC 0xf58 341 #define AI_ITOPOOBD 0xf5c 342 #define AI_ITOPOOBAIN 0xf70 343 #define AI_ITOPOOBBIN 0xf74 344 #define AI_ITOPOOBCIN 0xf78 345 #define AI_ITOPOOBDIN 0xf7c 346 #define AI_ITOPRESET 0xf90 347 #define AI_PERIPHERIALID4 0xfd0 348 #define AI_PERIPHERIALID5 0xfd4 349 #define AI_PERIPHERIALID6 0xfd8 350 #define AI_PERIPHERIALID7 0xfdc 351 #define AI_PERIPHERIALID0 0xfe0 352 #define AI_PERIPHERIALID1 0xfe4 353 #define AI_PERIPHERIALID2 0xfe8 354 #define AI_PERIPHERIALID3 0xfec 355 #define AI_COMPONENTID0 0xff0 356 #define AI_COMPONENTID1 0xff4 357 #define AI_COMPONENTID2 0xff8 358 #define AI_COMPONENTID3 0xffc 359 360 /* resetctrl */ 361 #define AIRC_RESET 1 362 363 /* config */ 364 #define AICFG_OOB 0x00000020 365 #define AICFG_IOS 0x00000010 366 #define AICFG_IOC 0x00000008 367 #define AICFG_TO 0x00000004 368 #define AICFG_ERRL 0x00000002 369 #define AICFG_RST 0x00000001 370 371 /* bit defines for AI_OOBSELOUTB74 reg */ 372 #define OOB_SEL_OUTEN_B_5 15 373 #define OOB_SEL_OUTEN_B_6 23 374 375 /* AI_OOBSEL for A/B/C/D, 0-7 */ 376 #define AI_OOBSEL_MASK 0x1F 377 #define AI_OOBSEL_0_SHIFT 0 378 #define AI_OOBSEL_1_SHIFT 8 379 #define AI_OOBSEL_2_SHIFT 16 380 #define AI_OOBSEL_3_SHIFT 24 381 #define AI_OOBSEL_4_SHIFT 0 382 #define AI_OOBSEL_5_SHIFT 8 383 #define AI_OOBSEL_6_SHIFT 16 384 #define AI_OOBSEL_7_SHIFT 24 385 386 #endif /* _AIDMP_H */ 387