1 /* 2 * Broadcom SiliconBackplane hardware register definitions. 3 * 4 * Copyright (C) 1999-2013, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * $Id: sbconfig.h 241182 2011-02-17 21:50:03Z $ 25 */ 26 27 #ifndef _SBCONFIG_H 28 #define _SBCONFIG_H 29 30 /* cpp contortions to concatenate w/arg prescan */ 31 #ifndef PAD 32 #define _PADLINE(line) pad ## line 33 #define _XSTR(line) _PADLINE(line) 34 #define PAD _XSTR(__LINE__) 35 #endif 36 37 /* enumeration in SB is based on the premise that cores are contiguos in the 38 * enumeration space. 39 */ 40 #define SB_BUS_SIZE 0x10000 /* Each bus gets 64Kbytes for cores */ 41 #define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE) 42 #define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /* Max cores per bus */ 43 44 /* 45 * Sonics Configuration Space Registers. 46 */ 47 #define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */ 48 #define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */ 49 50 #define SBIPSFLAG 0x08 51 #define SBTPSFLAG 0x18 52 #define SBTMERRLOGA 0x48 /* sonics >= 2.3 */ 53 #define SBTMERRLOG 0x50 /* sonics >= 2.3 */ 54 #define SBADMATCH3 0x60 55 #define SBADMATCH2 0x68 56 #define SBADMATCH1 0x70 57 #define SBIMSTATE 0x90 58 #define SBINTVEC 0x94 59 #define SBTMSTATELOW 0x98 60 #define SBTMSTATEHIGH 0x9c 61 #define SBBWA0 0xa0 62 #define SBIMCONFIGLOW 0xa8 63 #define SBIMCONFIGHIGH 0xac 64 #define SBADMATCH0 0xb0 65 #define SBTMCONFIGLOW 0xb8 66 #define SBTMCONFIGHIGH 0xbc 67 #define SBBCONFIG 0xc0 68 #define SBBSTATE 0xc8 69 #define SBACTCNFG 0xd8 70 #define SBFLAGST 0xe8 71 #define SBIDLOW 0xf8 72 #define SBIDHIGH 0xfc 73 74 /* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have 75 * a few registers *below* that line. I think it would be very confusing to try 76 * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here, 77 */ 78 79 #define SBIMERRLOGA 0xea8 80 #define SBIMERRLOG 0xeb0 81 #define SBTMPORTCONNID0 0xed8 82 #define SBTMPORTLOCK0 0xef8 83 84 #ifndef _LANGUAGE_ASSEMBLY 85 86 typedef volatile struct _sbconfig { 87 uint32 PAD[2]; 88 uint32 sbipsflag; /* initiator port ocp slave flag */ 89 uint32 PAD[3]; 90 uint32 sbtpsflag; /* target port ocp slave flag */ 91 uint32 PAD[11]; 92 uint32 sbtmerrloga; /* (sonics >= 2.3) */ 93 uint32 PAD; 94 uint32 sbtmerrlog; /* (sonics >= 2.3) */ 95 uint32 PAD[3]; 96 uint32 sbadmatch3; /* address match3 */ 97 uint32 PAD; 98 uint32 sbadmatch2; /* address match2 */ 99 uint32 PAD; 100 uint32 sbadmatch1; /* address match1 */ 101 uint32 PAD[7]; 102 uint32 sbimstate; /* initiator agent state */ 103 uint32 sbintvec; /* interrupt mask */ 104 uint32 sbtmstatelow; /* target state */ 105 uint32 sbtmstatehigh; /* target state */ 106 uint32 sbbwa0; /* bandwidth allocation table0 */ 107 uint32 PAD; 108 uint32 sbimconfiglow; /* initiator configuration */ 109 uint32 sbimconfighigh; /* initiator configuration */ 110 uint32 sbadmatch0; /* address match0 */ 111 uint32 PAD; 112 uint32 sbtmconfiglow; /* target configuration */ 113 uint32 sbtmconfighigh; /* target configuration */ 114 uint32 sbbconfig; /* broadcast configuration */ 115 uint32 PAD; 116 uint32 sbbstate; /* broadcast state */ 117 uint32 PAD[3]; 118 uint32 sbactcnfg; /* activate configuration */ 119 uint32 PAD[3]; 120 uint32 sbflagst; /* current sbflags */ 121 uint32 PAD[3]; 122 uint32 sbidlow; /* identification */ 123 uint32 sbidhigh; /* identification */ 124 } sbconfig_t; 125 126 #endif /* _LANGUAGE_ASSEMBLY */ 127 128 /* sbipsflag */ 129 #define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */ 130 #define SBIPS_INT1_SHIFT 0 131 #define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */ 132 #define SBIPS_INT2_SHIFT 8 133 #define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */ 134 #define SBIPS_INT3_SHIFT 16 135 #define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */ 136 #define SBIPS_INT4_SHIFT 24 137 138 /* sbtpsflag */ 139 #define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */ 140 #define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */ 141 142 /* sbtmerrlog */ 143 #define SBTMEL_CM 0x00000007 /* command */ 144 #define SBTMEL_CI 0x0000ff00 /* connection id */ 145 #define SBTMEL_EC 0x0f000000 /* error code */ 146 #define SBTMEL_ME 0x80000000 /* multiple error */ 147 148 /* sbimstate */ 149 #define SBIM_PC 0xf /* pipecount */ 150 #define SBIM_AP_MASK 0x30 /* arbitration policy */ 151 #define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */ 152 #define SBIM_AP_TS 0x10 /* use timesliaces only */ 153 #define SBIM_AP_TK 0x20 /* use token only */ 154 #define SBIM_AP_RSV 0x30 /* reserved */ 155 #define SBIM_IBE 0x20000 /* inbanderror */ 156 #define SBIM_TO 0x40000 /* timeout */ 157 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */ 158 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */ 159 160 /* sbtmstatelow */ 161 #define SBTML_RESET 0x0001 /* reset */ 162 #define SBTML_REJ_MASK 0x0006 /* reject field */ 163 #define SBTML_REJ 0x0002 /* reject */ 164 #define SBTML_TMPREJ 0x0004 /* temporary reject, for error recovery */ 165 166 #define SBTML_SICF_SHIFT 16 /* Shift to locate the SI control flags in sbtml */ 167 168 /* sbtmstatehigh */ 169 #define SBTMH_SERR 0x0001 /* serror */ 170 #define SBTMH_INT 0x0002 /* interrupt */ 171 #define SBTMH_BUSY 0x0004 /* busy */ 172 #define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */ 173 174 #define SBTMH_SISF_SHIFT 16 /* Shift to locate the SI status flags in sbtmh */ 175 176 /* sbbwa0 */ 177 #define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */ 178 #define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */ 179 #define SBBWA_TAB1_SHIFT 16 180 181 /* sbimconfiglow */ 182 #define SBIMCL_STO_MASK 0x7 /* service timeout */ 183 #define SBIMCL_RTO_MASK 0x70 /* request timeout */ 184 #define SBIMCL_RTO_SHIFT 4 185 #define SBIMCL_CID_MASK 0xff0000 /* connection id */ 186 #define SBIMCL_CID_SHIFT 16 187 188 /* sbimconfighigh */ 189 #define SBIMCH_IEM_MASK 0xc /* inband error mode */ 190 #define SBIMCH_TEM_MASK 0x30 /* timeout error mode */ 191 #define SBIMCH_TEM_SHIFT 4 192 #define SBIMCH_BEM_MASK 0xc0 /* bus error mode */ 193 #define SBIMCH_BEM_SHIFT 6 194 195 /* sbadmatch0 */ 196 #define SBAM_TYPE_MASK 0x3 /* address type */ 197 #define SBAM_AD64 0x4 /* reserved */ 198 #define SBAM_ADINT0_MASK 0xf8 /* type0 size */ 199 #define SBAM_ADINT0_SHIFT 3 200 #define SBAM_ADINT1_MASK 0x1f8 /* type1 size */ 201 #define SBAM_ADINT1_SHIFT 3 202 #define SBAM_ADINT2_MASK 0x1f8 /* type2 size */ 203 #define SBAM_ADINT2_SHIFT 3 204 #define SBAM_ADEN 0x400 /* enable */ 205 #define SBAM_ADNEG 0x800 /* negative decode */ 206 #define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */ 207 #define SBAM_BASE0_SHIFT 8 208 #define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */ 209 #define SBAM_BASE1_SHIFT 12 210 #define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */ 211 #define SBAM_BASE2_SHIFT 16 212 213 /* sbtmconfiglow */ 214 #define SBTMCL_CD_MASK 0xff /* clock divide */ 215 #define SBTMCL_CO_MASK 0xf800 /* clock offset */ 216 #define SBTMCL_CO_SHIFT 11 217 #define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */ 218 #define SBTMCL_IF_SHIFT 18 219 #define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */ 220 #define SBTMCL_IM_SHIFT 24 221 222 /* sbtmconfighigh */ 223 #define SBTMCH_BM_MASK 0x3 /* busy mode */ 224 #define SBTMCH_RM_MASK 0x3 /* retry mode */ 225 #define SBTMCH_RM_SHIFT 2 226 #define SBTMCH_SM_MASK 0x30 /* stop mode */ 227 #define SBTMCH_SM_SHIFT 4 228 #define SBTMCH_EM_MASK 0x300 /* sb error mode */ 229 #define SBTMCH_EM_SHIFT 8 230 #define SBTMCH_IM_MASK 0xc00 /* int mode */ 231 #define SBTMCH_IM_SHIFT 10 232 233 /* sbbconfig */ 234 #define SBBC_LAT_MASK 0x3 /* sb latency */ 235 #define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */ 236 #define SBBC_MAX0_SHIFT 16 237 #define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */ 238 #define SBBC_MAX1_SHIFT 20 239 240 /* sbbstate */ 241 #define SBBS_SRD 0x1 /* st reg disable */ 242 #define SBBS_HRD 0x2 /* hold reg disable */ 243 244 /* sbidlow */ 245 #define SBIDL_CS_MASK 0x3 /* config space */ 246 #define SBIDL_AR_MASK 0x38 /* # address ranges supported */ 247 #define SBIDL_AR_SHIFT 3 248 #define SBIDL_SYNCH 0x40 /* sync */ 249 #define SBIDL_INIT 0x80 /* initiator */ 250 #define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */ 251 #define SBIDL_MINLAT_SHIFT 8 252 #define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */ 253 #define SBIDL_MAXLAT_SHIFT 12 254 #define SBIDL_FIRST 0x10000 /* this initiator is first */ 255 #define SBIDL_CW_MASK 0xc0000 /* cycle counter width */ 256 #define SBIDL_CW_SHIFT 18 257 #define SBIDL_TP_MASK 0xf00000 /* target ports */ 258 #define SBIDL_TP_SHIFT 20 259 #define SBIDL_IP_MASK 0xf000000 /* initiator ports */ 260 #define SBIDL_IP_SHIFT 24 261 #define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */ 262 #define SBIDL_RV_SHIFT 28 263 #define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */ 264 #define SBIDL_RV_2_3 0x10000000 /* version 2.3 */ 265 266 /* sbidhigh */ 267 #define SBIDH_RC_MASK 0x000f /* revision code */ 268 #define SBIDH_RCE_MASK 0x7000 /* revision code extension field */ 269 #define SBIDH_RCE_SHIFT 8 270 #define SBCOREREV(sbidh) \ 271 ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK)) 272 #define SBIDH_CC_MASK 0x8ff0 /* core code */ 273 #define SBIDH_CC_SHIFT 4 274 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */ 275 #define SBIDH_VC_SHIFT 16 276 277 #define SB_COMMIT 0xfd8 /* update buffered registers value */ 278 279 /* vendor codes */ 280 #define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */ 281 282 #endif /* _SBCONFIG_H */ 283