1 /* 2 * Include file private to the SOC Interconnect support files. 3 * 4 * Copyright (C) 1999-2013, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * $Id: siutils_priv.h 385510 2013-02-15 21:02:07Z $ 25 */ 26 27 #ifndef _siutils_priv_h_ 28 #define _siutils_priv_h_ 29 30 #define SI_ERROR(args) 31 32 #define SI_MSG(args) 33 34 #ifdef BCMDBG_SI 35 #define SI_VMSG(args) printf args 36 #else 37 #define SI_VMSG(args) 38 #endif 39 40 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 41 42 typedef uint32 (*si_intrsoff_t)(void *intr_arg); 43 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 44 typedef bool (*si_intrsenabled_t)(void *intr_arg); 45 46 typedef struct gpioh_item { 47 void *arg; 48 bool level; 49 gpio_handler_t handler; 50 uint32 event; 51 struct gpioh_item *next; 52 } gpioh_item_t; 53 54 /* misc si info needed by some of the routines */ 55 typedef struct si_info { 56 struct si_pub pub; /* back plane public state (must be first field) */ 57 58 void *osh; /* osl os handle */ 59 void *sdh; /* bcmsdh handle */ 60 61 uint dev_coreid; /* the core provides driver functions */ 62 void *intr_arg; /* interrupt callback function arg */ 63 si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */ 64 si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */ 65 si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */ 66 67 void *pch; /* PCI/E core handle */ 68 69 gpioh_item_t *gpioh_head; /* GPIO event handlers list */ 70 71 bool memseg; /* flag to toggle MEM_SEG register */ 72 73 char *vars; 74 uint varsz; 75 76 void *curmap; /* current regs va */ 77 void *regs[SI_MAXCORES]; /* other regs va */ 78 79 uint curidx; /* current core index */ 80 uint numcores; /* # discovered cores */ 81 uint coreid[SI_MAXCORES]; /* id of each core */ 82 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */ 83 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */ 84 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */ 85 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */ 86 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */ 87 88 void *curwrap; /* current wrapper va */ 89 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */ 90 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */ 91 92 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */ 93 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */ 94 uint32 oob_router; /* oob router registers for axi */ 95 } si_info_t; 96 97 #define SI_INFO(sih) (si_info_t *)(uintptr)sih 98 99 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 100 ISALIGNED((x), SI_CORE_SIZE)) 101 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 102 #define BADCOREADDR 0 103 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES) 104 #define NOREV -1 /* Invalid rev */ 105 106 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 107 ((si)->pub.buscoretype == PCI_CORE_ID)) 108 109 #define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 110 ((si)->pub.buscoretype == PCIE_CORE_ID)) 111 112 #define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 113 ((si)->pub.buscoretype == PCIE2_CORE_ID)) 114 115 #define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si)) 116 117 #define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE)) 118 119 /* Newer chips can access PCI/PCIE and CC core without requiring to change 120 * PCI BAR0 WIN 121 */ 122 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13))) 123 124 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 125 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 126 127 /* 128 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ 129 * after core switching to avoid invalid register accesss inside ISR. 130 */ 131 #define INTR_OFF(si, intr_val) \ 132 if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \ 133 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); } 134 #define INTR_RESTORE(si, intr_val) \ 135 if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \ 136 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 137 138 /* dynamic clock control defines */ 139 #define LPOMINFREQ 25000 /* low power oscillator min */ 140 #define LPOMAXFREQ 43000 /* low power oscillator max */ 141 #define XTALMINFREQ 19800000 /* 20 MHz - 1% */ 142 #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */ 143 #define PCIMINFREQ 25000000 /* 25 MHz */ 144 #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */ 145 146 #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */ 147 #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */ 148 149 /* Force fast clock for 4360b0 */ 150 #define PCI_FORCEHT(si) \ 151 (((PCIE_GEN1(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \ 152 ((PCI(si) || PCIE_GEN1(si)) && (si->pub.chip == BCM4321_CHIP_ID)) || \ 153 (PCIE_GEN1(si) && (si->pub.chip == BCM4716_CHIP_ID)) || \ 154 (PCIE_GEN1(si) && (si->pub.chip == BCM4748_CHIP_ID))) 155 156 /* GPIO Based LED powersave defines */ 157 #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */ 158 #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */ 159 160 #ifndef DEFAULT_GPIOTIMERVAL 161 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 162 #endif 163 164 /* Silicon Backplane externs */ 165 extern void sb_scan(si_t *sih, void *regs, uint devid); 166 extern uint sb_coreid(si_t *sih); 167 extern uint sb_intflag(si_t *sih); 168 extern uint sb_flag(si_t *sih); 169 extern void sb_setint(si_t *sih, int siflag); 170 extern uint sb_corevendor(si_t *sih); 171 extern uint sb_corerev(si_t *sih); 172 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 173 extern bool sb_iscoreup(si_t *sih); 174 extern void *sb_setcoreidx(si_t *sih, uint coreidx); 175 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val); 176 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 177 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val); 178 extern void sb_commit(si_t *sih); 179 extern uint32 sb_base(uint32 admatch); 180 extern uint32 sb_size(uint32 admatch); 181 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 182 extern void sb_core_disable(si_t *sih, uint32 bits); 183 extern uint32 sb_addrspace(si_t *sih, uint asidx); 184 extern uint32 sb_addrspacesize(si_t *sih, uint asidx); 185 extern int sb_numaddrspaces(si_t *sih); 186 187 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx); 188 189 extern bool sb_taclear(si_t *sih, bool details); 190 191 192 /* Wake-on-wireless-LAN (WOWL) */ 193 extern bool sb_pci_pmecap(si_t *sih); 194 struct osl_info; 195 extern bool sb_pci_fastpmecap(struct osl_info *osh); 196 extern bool sb_pci_pmeclr(si_t *sih); 197 extern void sb_pci_pmeen(si_t *sih); 198 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset); 199 200 /* AMBA Interconnect exported externs */ 201 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 202 void *sdh, char **vars, uint *varsz); 203 extern si_t *ai_kattach(osl_t *osh); 204 extern void ai_scan(si_t *sih, void *regs, uint devid); 205 206 extern uint ai_flag(si_t *sih); 207 extern uint ai_flag_alt(si_t *sih); 208 extern void ai_setint(si_t *sih, int siflag); 209 extern uint ai_coreidx(si_t *sih); 210 extern uint ai_corevendor(si_t *sih); 211 extern uint ai_corerev(si_t *sih); 212 extern bool ai_iscoreup(si_t *sih); 213 extern void *ai_setcoreidx(si_t *sih, uint coreidx); 214 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 215 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 216 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 217 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 218 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 219 extern void ai_core_disable(si_t *sih, uint32 bits); 220 extern int ai_numaddrspaces(si_t *sih); 221 extern uint32 ai_addrspace(si_t *sih, uint asidx); 222 extern uint32 ai_addrspacesize(si_t *sih, uint asidx); 223 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 224 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 225 226 227 228 #define ub_scan(a, b, c) do {} while (0) 229 #define ub_flag(a) (0) 230 #define ub_setint(a, b) do {} while (0) 231 #define ub_coreidx(a) (0) 232 #define ub_corevendor(a) (0) 233 #define ub_corerev(a) (0) 234 #define ub_iscoreup(a) (0) 235 #define ub_setcoreidx(a, b) (0) 236 #define ub_core_cflags(a, b, c) (0) 237 #define ub_core_cflags_wo(a, b, c) do {} while (0) 238 #define ub_core_sflags(a, b, c) (0) 239 #define ub_corereg(a, b, c, d, e) (0) 240 #define ub_core_reset(a, b, c) do {} while (0) 241 #define ub_core_disable(a, b) do {} while (0) 242 #define ub_numaddrspaces(a) (0) 243 #define ub_addrspace(a, b) (0) 244 #define ub_addrspacesize(a, b) (0) 245 #define ub_view(a, b) do {} while (0) 246 #define ub_dumpregs(a, b) do {} while (0) 247 248 #endif /* _siutils_priv_h_ */ 249