1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #ifndef __iwl_trans_int_pcie_h__
30 #define __iwl_trans_int_pcie_h__
31
32 #include <linux/spinlock.h>
33 #include <linux/interrupt.h>
34 #include <linux/skbuff.h>
35 #include <linux/wait.h>
36 #include <linux/pci.h>
37
38 #include "iwl-fh.h"
39 #include "iwl-csr.h"
40 #include "iwl-shared.h"
41 #include "iwl-trans.h"
42 #include "iwl-debug.h"
43 #include "iwl-io.h"
44 #include "iwl-op-mode.h"
45
46 struct iwl_tx_queue;
47 struct iwl_queue;
48 struct iwl_host_cmd;
49
50 /*This file includes the declaration that are internal to the
51 * trans_pcie layer */
52
53 struct iwl_rx_mem_buffer {
54 dma_addr_t page_dma;
55 struct page *page;
56 struct list_head list;
57 };
58
59 /**
60 * struct isr_statistics - interrupt statistics
61 *
62 */
63 struct isr_statistics {
64 u32 hw;
65 u32 sw;
66 u32 err_code;
67 u32 sch;
68 u32 alive;
69 u32 rfkill;
70 u32 ctkill;
71 u32 wakeup;
72 u32 rx;
73 u32 tx;
74 u32 unhandled;
75 };
76
77 /**
78 * struct iwl_rx_queue - Rx queue
79 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
80 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
81 * @pool:
82 * @queue:
83 * @read: Shared index to newest available Rx buffer
84 * @write: Shared index to oldest written Rx packet
85 * @free_count: Number of pre-allocated buffers in rx_free
86 * @write_actual:
87 * @rx_free: list of free SKBs for use
88 * @rx_used: List of Rx buffers with no SKB
89 * @need_update: flag to indicate we need to update read/write index
90 * @rb_stts: driver's pointer to receive buffer status
91 * @rb_stts_dma: bus address of receive buffer status
92 * @lock:
93 *
94 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
95 */
96 struct iwl_rx_queue {
97 __le32 *bd;
98 dma_addr_t bd_dma;
99 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
100 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
101 u32 read;
102 u32 write;
103 u32 free_count;
104 u32 write_actual;
105 struct list_head rx_free;
106 struct list_head rx_used;
107 int need_update;
108 struct iwl_rb_status *rb_stts;
109 dma_addr_t rb_stts_dma;
110 spinlock_t lock;
111 };
112
113 struct iwl_dma_ptr {
114 dma_addr_t dma;
115 void *addr;
116 size_t size;
117 };
118
119 /**
120 * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
121 * @index -- current index
122 * @n_bd -- total number of entries in queue (must be power of 2)
123 */
iwl_queue_inc_wrap(int index,int n_bd)124 static inline int iwl_queue_inc_wrap(int index, int n_bd)
125 {
126 return ++index & (n_bd - 1);
127 }
128
129 /**
130 * iwl_queue_dec_wrap - decrement queue index, wrap back to end
131 * @index -- current index
132 * @n_bd -- total number of entries in queue (must be power of 2)
133 */
iwl_queue_dec_wrap(int index,int n_bd)134 static inline int iwl_queue_dec_wrap(int index, int n_bd)
135 {
136 return --index & (n_bd - 1);
137 }
138
139 /*
140 * This queue number is required for proper operation
141 * because the ucode will stop/start the scheduler as
142 * required.
143 */
144 #define IWL_IPAN_MCAST_QUEUE 8
145
146 struct iwl_cmd_meta {
147 /* only for SYNC commands, iff the reply skb is wanted */
148 struct iwl_host_cmd *source;
149
150 u32 flags;
151
152 DEFINE_DMA_UNMAP_ADDR(mapping);
153 DEFINE_DMA_UNMAP_LEN(len);
154 };
155
156 /*
157 * Generic queue structure
158 *
159 * Contains common data for Rx and Tx queues.
160 *
161 * Note the difference between n_bd and n_window: the hardware
162 * always assumes 256 descriptors, so n_bd is always 256 (unless
163 * there might be HW changes in the future). For the normal TX
164 * queues, n_window, which is the size of the software queue data
165 * is also 256; however, for the command queue, n_window is only
166 * 32 since we don't need so many commands pending. Since the HW
167 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
168 * the software buffers (in the variables @meta, @txb in struct
169 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
170 * in the same struct) have 256.
171 * This means that we end up with the following:
172 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
173 * SW entries: | 0 | ... | 31 |
174 * where N is a number between 0 and 7. This means that the SW
175 * data is a window overlayed over the HW queue.
176 */
177 struct iwl_queue {
178 int n_bd; /* number of BDs in this queue */
179 int write_ptr; /* 1-st empty entry (index) host_w*/
180 int read_ptr; /* last used entry (index) host_r*/
181 /* use for monitoring and recovering the stuck queue */
182 dma_addr_t dma_addr; /* physical addr for BD's */
183 int n_window; /* safe queue window */
184 u32 id;
185 int low_mark; /* low watermark, resume queue if free
186 * space more than this */
187 int high_mark; /* high watermark, stop queue if free
188 * space less than this */
189 };
190
191 /**
192 * struct iwl_tx_queue - Tx Queue for DMA
193 * @q: generic Rx/Tx queue descriptor
194 * @bd: base of circular buffer of TFDs
195 * @cmd: array of command/TX buffer pointers
196 * @meta: array of meta data for each command/tx buffer
197 * @dma_addr_cmd: physical address of cmd/tx buffer array
198 * @txb: array of per-TFD driver data
199 * lock: queue lock
200 * @time_stamp: time (in jiffies) of last read_ptr change
201 * @need_update: indicates need to update read/write index
202 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
203 * @sta_id: valid if sched_retry is set
204 * @tid: valid if sched_retry is set
205 *
206 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
207 * descriptors) and required locking structures.
208 */
209 #define TFD_TX_CMD_SLOTS 256
210 #define TFD_CMD_SLOTS 32
211
212 struct iwl_tx_queue {
213 struct iwl_queue q;
214 struct iwl_tfd *tfds;
215 struct iwl_device_cmd **cmd;
216 struct iwl_cmd_meta *meta;
217 struct sk_buff **skbs;
218 spinlock_t lock;
219 unsigned long time_stamp;
220 u8 need_update;
221 u8 sched_retry;
222 u8 active;
223 u8 swq_id;
224
225 u16 sta_id;
226 u16 tid;
227 };
228
229 /**
230 * struct iwl_trans_pcie - PCIe transport specific data
231 * @rxq: all the RX queue data
232 * @rx_replenish: work that will be called when buffers need to be allocated
233 * @trans: pointer to the generic transport area
234 * @irq - the irq number for the device
235 * @irq_requested: true when the irq has been requested
236 * @scd_base_addr: scheduler sram base address in SRAM
237 * @scd_bc_tbls: pointer to the byte count table of the scheduler
238 * @kw: keep warm address
239 * @ac_to_fifo: to what fifo is a specifc AC mapped ?
240 * @ac_to_queue: to what tx queue is a specifc AC mapped ?
241 * @mcast_queue:
242 * @txq: Tx DMA processing queues
243 * @txq_ctx_active_msk: what queue is active
244 * queue_stopped: tracks what queue is stopped
245 * queue_stop_count: tracks what SW queue is stopped
246 * @pci_dev: basic pci-network driver stuff
247 * @hw_base: pci hardware address support
248 * @ucode_write_complete: indicates that the ucode has been copied.
249 * @ucode_write_waitq: wait queue for uCode load
250 * @status - transport specific status flags
251 * @cmd_queue - command queue number
252 */
253 struct iwl_trans_pcie {
254 struct iwl_rx_queue rxq;
255 struct work_struct rx_replenish;
256 struct iwl_trans *trans;
257
258 /* INT ICT Table */
259 __le32 *ict_tbl;
260 dma_addr_t ict_tbl_dma;
261 int ict_index;
262 u32 inta;
263 bool use_ict;
264 bool irq_requested;
265 struct tasklet_struct irq_tasklet;
266 struct isr_statistics isr_stats;
267
268 unsigned int irq;
269 spinlock_t irq_lock;
270 u32 inta_mask;
271 u32 scd_base_addr;
272 struct iwl_dma_ptr scd_bc_tbls;
273 struct iwl_dma_ptr kw;
274
275 const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
276 const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
277 u8 mcast_queue[NUM_IWL_RXON_CTX];
278 u8 agg_txq[IWLAGN_STATION_COUNT][IWL_MAX_TID_COUNT];
279
280 struct iwl_tx_queue *txq;
281 unsigned long txq_ctx_active_msk;
282 #define IWL_MAX_HW_QUEUES 32
283 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
284 atomic_t queue_stop_count[4];
285
286 /* PCI bus related data */
287 struct pci_dev *pci_dev;
288 void __iomem *hw_base;
289
290 bool ucode_write_complete;
291 wait_queue_head_t ucode_write_waitq;
292 unsigned long status;
293 u8 cmd_queue;
294 u8 n_no_reclaim_cmds;
295 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS];
296 };
297
298 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
299 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
300
301 /*****************************************************
302 * RX
303 ******************************************************/
304 void iwl_bg_rx_replenish(struct work_struct *data);
305 void iwl_irq_tasklet(struct iwl_trans *trans);
306 void iwlagn_rx_replenish(struct iwl_trans *trans);
307 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
308 struct iwl_rx_queue *q);
309
310 /*****************************************************
311 * ICT
312 ******************************************************/
313 void iwl_reset_ict(struct iwl_trans *trans);
314 void iwl_disable_ict(struct iwl_trans *trans);
315 int iwl_alloc_isr_ict(struct iwl_trans *trans);
316 void iwl_free_isr_ict(struct iwl_trans *trans);
317 irqreturn_t iwl_isr_ict(int irq, void *data);
318
319 /*****************************************************
320 * TX / HCMD
321 ******************************************************/
322 void iwl_txq_update_write_ptr(struct iwl_trans *trans,
323 struct iwl_tx_queue *txq);
324 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
325 struct iwl_tx_queue *txq,
326 dma_addr_t addr, u16 len, u8 reset);
327 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
328 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
329 void iwl_tx_cmd_complete(struct iwl_trans *trans,
330 struct iwl_rx_cmd_buffer *rxb, int handler_status);
331 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
332 struct iwl_tx_queue *txq,
333 u16 byte_cnt);
334 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
335 int sta_id, int tid);
336 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
337 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
338 struct iwl_tx_queue *txq,
339 int tx_fifo_id, int scd_retry);
340 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, int sta_id, int tid);
341 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
342 enum iwl_rxon_context_id ctx,
343 int sta_id, int tid, int frame_limit, u16 ssn);
344 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
345 enum dma_data_direction dma_dir);
346 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
347 struct sk_buff_head *skbs);
348 int iwl_queue_space(const struct iwl_queue *q);
349
350 /*****************************************************
351 * Error handling
352 ******************************************************/
353 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
354 char **buf, bool display);
355 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
356 void iwl_dump_csr(struct iwl_trans *trans);
357
358 /*****************************************************
359 * Helpers
360 ******************************************************/
iwl_disable_interrupts(struct iwl_trans * trans)361 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
362 {
363 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
364 clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
365
366 /* disable interrupts from uCode/NIC to host */
367 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
368
369 /* acknowledge/clear/reset any interrupts still pending
370 * from uCode or flow handler (Rx/Tx DMA) */
371 iwl_write32(trans, CSR_INT, 0xffffffff);
372 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
373 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
374 }
375
iwl_enable_interrupts(struct iwl_trans * trans)376 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
377 {
378 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
379
380 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
381 set_bit(STATUS_INT_ENABLED, &trans_pcie->status);
382 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
383 }
384
iwl_enable_rfkill_int(struct iwl_trans * trans)385 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
386 {
387 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
388 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
389 }
390
391 /*
392 * we have 8 bits used like this:
393 *
394 * 7 6 5 4 3 2 1 0
395 * | | | | | | | |
396 * | | | | | | +-+-------- AC queue (0-3)
397 * | | | | | |
398 * | +-+-+-+-+------------ HW queue ID
399 * |
400 * +---------------------- unused
401 */
iwl_set_swq_id(struct iwl_tx_queue * txq,u8 ac,u8 hwq)402 static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq)
403 {
404 BUG_ON(ac > 3); /* only have 2 bits */
405 BUG_ON(hwq > 31); /* only use 5 bits */
406
407 txq->swq_id = (hwq << 2) | ac;
408 }
409
iwl_get_queue_ac(struct iwl_tx_queue * txq)410 static inline u8 iwl_get_queue_ac(struct iwl_tx_queue *txq)
411 {
412 return txq->swq_id & 0x3;
413 }
414
iwl_wake_queue(struct iwl_trans * trans,struct iwl_tx_queue * txq)415 static inline void iwl_wake_queue(struct iwl_trans *trans,
416 struct iwl_tx_queue *txq)
417 {
418 u8 queue = txq->swq_id;
419 u8 ac = queue & 3;
420 u8 hwq = (queue >> 2) & 0x1f;
421 struct iwl_trans_pcie *trans_pcie =
422 IWL_TRANS_GET_PCIE_TRANS(trans);
423
424 if (test_and_clear_bit(hwq, trans_pcie->queue_stopped)) {
425 if (atomic_dec_return(&trans_pcie->queue_stop_count[ac]) <= 0) {
426 iwl_op_mode_queue_not_full(trans->op_mode, ac);
427 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d ac %d",
428 hwq, ac);
429 } else {
430 IWL_DEBUG_TX_QUEUES(trans,
431 "Don't wake hwq %d ac %d stop count %d",
432 hwq, ac,
433 atomic_read(&trans_pcie->queue_stop_count[ac]));
434 }
435 }
436 }
437
iwl_stop_queue(struct iwl_trans * trans,struct iwl_tx_queue * txq)438 static inline void iwl_stop_queue(struct iwl_trans *trans,
439 struct iwl_tx_queue *txq)
440 {
441 u8 queue = txq->swq_id;
442 u8 ac = queue & 3;
443 u8 hwq = (queue >> 2) & 0x1f;
444 struct iwl_trans_pcie *trans_pcie =
445 IWL_TRANS_GET_PCIE_TRANS(trans);
446
447 if (!test_and_set_bit(hwq, trans_pcie->queue_stopped)) {
448 if (atomic_inc_return(&trans_pcie->queue_stop_count[ac]) > 0) {
449 iwl_op_mode_queue_full(trans->op_mode, ac);
450 IWL_DEBUG_TX_QUEUES(trans,
451 "Stop hwq %d ac %d stop count %d",
452 hwq, ac,
453 atomic_read(&trans_pcie->queue_stop_count[ac]));
454 } else {
455 IWL_DEBUG_TX_QUEUES(trans,
456 "Don't stop hwq %d ac %d stop count %d",
457 hwq, ac,
458 atomic_read(&trans_pcie->queue_stop_count[ac]));
459 }
460 } else {
461 IWL_DEBUG_TX_QUEUES(trans, "stop hwq %d, but it is stopped",
462 hwq);
463 }
464 }
465
iwl_txq_ctx_activate(struct iwl_trans_pcie * trans_pcie,int txq_id)466 static inline void iwl_txq_ctx_activate(struct iwl_trans_pcie *trans_pcie,
467 int txq_id)
468 {
469 set_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
470 }
471
iwl_txq_ctx_deactivate(struct iwl_trans_pcie * trans_pcie,int txq_id)472 static inline void iwl_txq_ctx_deactivate(struct iwl_trans_pcie *trans_pcie,
473 int txq_id)
474 {
475 clear_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
476 }
477
iwl_queue_used(const struct iwl_queue * q,int i)478 static inline int iwl_queue_used(const struct iwl_queue *q, int i)
479 {
480 return q->write_ptr >= q->read_ptr ?
481 (i >= q->read_ptr && i < q->write_ptr) :
482 !(i < q->read_ptr && i >= q->write_ptr);
483 }
484
get_cmd_index(struct iwl_queue * q,u32 index)485 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
486 {
487 return index & (q->n_window - 1);
488 }
489
490 #define IWL_TX_FIFO_BK 0 /* shared */
491 #define IWL_TX_FIFO_BE 1
492 #define IWL_TX_FIFO_VI 2 /* shared */
493 #define IWL_TX_FIFO_VO 3
494 #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
495 #define IWL_TX_FIFO_BE_IPAN 4
496 #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
497 #define IWL_TX_FIFO_VO_IPAN 5
498 /* re-uses the VO FIFO, uCode will properly flush/schedule */
499 #define IWL_TX_FIFO_AUX 5
500 #define IWL_TX_FIFO_UNUSED -1
501
502 /* AUX (TX during scan dwell) queue */
503 #define IWL_AUX_QUEUE 10
504
505 #endif /* __iwl_trans_int_pcie_h__ */
506