1 /* ZD1211 USB-WLAN driver for Linux
2 *
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #include <linux/kernel.h>
22
23 #include "zd_rf.h"
24 #include "zd_usb.h"
25 #include "zd_chip.h"
26
27 static const u32 rf2959_table[][2] = {
28 RF_CHANNEL( 1) = { 0x181979, 0x1e6666 },
29 RF_CHANNEL( 2) = { 0x181989, 0x1e6666 },
30 RF_CHANNEL( 3) = { 0x181999, 0x1e6666 },
31 RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
32 RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 },
33 RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 },
34 RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
35 RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 },
36 RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 },
37 RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
38 RF_CHANNEL(11) = { 0x181a19, 0x1e6666 },
39 RF_CHANNEL(12) = { 0x181a29, 0x1e6666 },
40 RF_CHANNEL(13) = { 0x181a39, 0x1e6666 },
41 RF_CHANNEL(14) = { 0x181a60, 0x1c0000 },
42 };
43
44 #if 0
45 static int bits(u32 rw, int from, int to)
46 {
47 rw &= ~(0xffffffffU << (to+1));
48 rw >>= from;
49 return rw;
50 }
51
52 static int bit(u32 rw, int bit)
53 {
54 return bits(rw, bit, bit);
55 }
56
57 static void dump_regwrite(u32 rw)
58 {
59 int reg = bits(rw, 18, 22);
60 int rw_flag = bits(rw, 23, 23);
61 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
62
63 switch (reg) {
64 case 0:
65 PDEBUG("reg0 CFG1 ref_sel %d hybernate %d rf_vco_reg_en %d"
66 " if_vco_reg_en %d if_vga_en %d",
67 bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
68 bit(rw, 0));
69 break;
70 case 1:
71 PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
72 " cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
73 " ifloopc %d dac1 %d",
74 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
75 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
76 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
77 break;
78 case 2:
79 PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
80 bits(rw, 6, 17), bits(rw, 0, 5));
81 break;
82 case 3:
83 PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
84 break;
85 case 4:
86 PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
87 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
88 break;
89 case 5:
90 PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
91 " pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
92 " dac %d",
93 bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
94 bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
95 bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
96 break;
97 case 6:
98 PDEBUG("reg6 RFPLL2 n %d num %d",
99 bits(rw, 6, 17), bits(rw, 0, 5));
100 break;
101 case 7:
102 PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
103 break;
104 case 8:
105 PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d",
106 bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
107 break;
108 case 9:
109 PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d",
110 bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
111 bits(rw, 0, 2));
112 break;
113 case 10:
114 PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d"
115 " rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d"
116 " intbiasen %d tybypass %d",
117 bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
118 bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
119 bit(rw, 1), bit(rw, 0));
120 break;
121 case 11:
122 PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d"
123 " tx_delay %d",
124 bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
125 bits(rw, 0, 2));
126 break;
127 case 12:
128 PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d",
129 bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
130 break;
131 case 13:
132 PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d"
133 " lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d"
134 " rf_biasvco %d",
135 bit(rw, 17), bit(rw, 16), bit(rw, 15),
136 bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
137 bits(rw, 0, 2));
138 break;
139 case 14:
140 PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d"
141 " tx_acal %d tx_pcal %d",
142 bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
143 bits(rw, 0, 3));
144 break;
145 }
146 }
147 #endif /* 0 */
148
rf2959_init_hw(struct zd_rf * rf)149 static int rf2959_init_hw(struct zd_rf *rf)
150 {
151 int r;
152 struct zd_chip *chip = zd_rf_to_chip(rf);
153
154 static const struct zd_ioreq16 ioreqs[] = {
155 { ZD_CR2, 0x1E }, { ZD_CR9, 0x20 }, { ZD_CR10, 0x89 },
156 { ZD_CR11, 0x00 }, { ZD_CR15, 0xD0 }, { ZD_CR17, 0x68 },
157 { ZD_CR19, 0x4a }, { ZD_CR20, 0x0c }, { ZD_CR21, 0x0E },
158 { ZD_CR23, 0x48 },
159 /* normal size for cca threshold */
160 { ZD_CR24, 0x14 },
161 /* { ZD_CR24, 0x20 }, */
162 { ZD_CR26, 0x90 }, { ZD_CR27, 0x30 }, { ZD_CR29, 0x20 },
163 { ZD_CR31, 0xb2 }, { ZD_CR32, 0x43 }, { ZD_CR33, 0x28 },
164 { ZD_CR38, 0x30 }, { ZD_CR34, 0x0f }, { ZD_CR35, 0xF0 },
165 { ZD_CR41, 0x2a }, { ZD_CR46, 0x7F }, { ZD_CR47, 0x1E },
166 { ZD_CR51, 0xc5 }, { ZD_CR52, 0xc5 }, { ZD_CR53, 0xc5 },
167 { ZD_CR79, 0x58 }, { ZD_CR80, 0x30 }, { ZD_CR81, 0x30 },
168 { ZD_CR82, 0x00 }, { ZD_CR83, 0x24 }, { ZD_CR84, 0x04 },
169 { ZD_CR85, 0x00 }, { ZD_CR86, 0x10 }, { ZD_CR87, 0x2A },
170 { ZD_CR88, 0x10 }, { ZD_CR89, 0x24 }, { ZD_CR90, 0x18 },
171 /* { ZD_CR91, 0x18 }, */
172 /* should solve continuous CTS frame problems */
173 { ZD_CR91, 0x00 },
174 { ZD_CR92, 0x0a }, { ZD_CR93, 0x00 }, { ZD_CR94, 0x01 },
175 { ZD_CR95, 0x00 }, { ZD_CR96, 0x40 }, { ZD_CR97, 0x37 },
176 { ZD_CR98, 0x05 }, { ZD_CR99, 0x28 }, { ZD_CR100, 0x00 },
177 { ZD_CR101, 0x13 }, { ZD_CR102, 0x27 }, { ZD_CR103, 0x27 },
178 { ZD_CR104, 0x18 }, { ZD_CR105, 0x12 },
179 /* normal size */
180 { ZD_CR106, 0x1a },
181 /* { ZD_CR106, 0x22 }, */
182 { ZD_CR107, 0x24 }, { ZD_CR108, 0x0a }, { ZD_CR109, 0x13 },
183 { ZD_CR110, 0x2F }, { ZD_CR111, 0x27 }, { ZD_CR112, 0x27 },
184 { ZD_CR113, 0x27 }, { ZD_CR114, 0x27 }, { ZD_CR115, 0x40 },
185 { ZD_CR116, 0x40 }, { ZD_CR117, 0xF0 }, { ZD_CR118, 0xF0 },
186 { ZD_CR119, 0x16 },
187 /* no TX continuation */
188 { ZD_CR122, 0x00 },
189 /* { ZD_CR122, 0xff }, */
190 { ZD_CR127, 0x03 }, { ZD_CR131, 0x08 }, { ZD_CR138, 0x28 },
191 { ZD_CR148, 0x44 }, { ZD_CR150, 0x10 }, { ZD_CR169, 0xBB },
192 { ZD_CR170, 0xBB },
193 };
194
195 static const u32 rv[] = {
196 0x000007, /* REG0(CFG1) */
197 0x07dd43, /* REG1(IFPLL1) */
198 0x080959, /* REG2(IFPLL2) */
199 0x0e6666,
200 0x116a57, /* REG4 */
201 0x17dd43, /* REG5 */
202 0x1819f9, /* REG6 */
203 0x1e6666,
204 0x214554,
205 0x25e7fa,
206 0x27fffa,
207 /* The Zydas driver somehow forgets to set this value. It's
208 * only set for Japan. We are using internal power control
209 * for now.
210 */
211 0x294128, /* internal power */
212 /* 0x28252c, */ /* External control TX power */
213 /* ZD_CR31_CCK, ZD_CR51_6-36M, ZD_CR52_48M, ZD_CR53_54M */
214 0x2c0000,
215 0x300000,
216 0x340000, /* REG13(0xD) */
217 0x381e0f, /* REG14(0xE) */
218 /* Bogus, RF2959's data sheet doesn't know register 27, which is
219 * actually referenced here. The commented 0x11 is 17.
220 */
221 0x6c180f, /* REG27(0x11) */
222 };
223
224 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
225 if (r)
226 return r;
227
228 return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
229 }
230
rf2959_set_channel(struct zd_rf * rf,u8 channel)231 static int rf2959_set_channel(struct zd_rf *rf, u8 channel)
232 {
233 int i, r;
234 const u32 *rv = rf2959_table[channel-1];
235 struct zd_chip *chip = zd_rf_to_chip(rf);
236
237 for (i = 0; i < 2; i++) {
238 r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS);
239 if (r)
240 return r;
241 }
242 return 0;
243 }
244
rf2959_switch_radio_on(struct zd_rf * rf)245 static int rf2959_switch_radio_on(struct zd_rf *rf)
246 {
247 static const struct zd_ioreq16 ioreqs[] = {
248 { ZD_CR10, 0x89 },
249 { ZD_CR11, 0x00 },
250 };
251 struct zd_chip *chip = zd_rf_to_chip(rf);
252
253 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
254 }
255
rf2959_switch_radio_off(struct zd_rf * rf)256 static int rf2959_switch_radio_off(struct zd_rf *rf)
257 {
258 static const struct zd_ioreq16 ioreqs[] = {
259 { ZD_CR10, 0x15 },
260 { ZD_CR11, 0x81 },
261 };
262 struct zd_chip *chip = zd_rf_to_chip(rf);
263
264 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
265 }
266
zd_rf_init_rf2959(struct zd_rf * rf)267 int zd_rf_init_rf2959(struct zd_rf *rf)
268 {
269 struct zd_chip *chip = zd_rf_to_chip(rf);
270
271 if (zd_chip_is_zd1211b(chip)) {
272 dev_err(zd_chip_dev(chip),
273 "RF2959 is currently not supported for ZD1211B"
274 " devices\n");
275 return -ENODEV;
276 }
277 rf->init_hw = rf2959_init_hw;
278 rf->set_channel = rf2959_set_channel;
279 rf->switch_radio_on = rf2959_switch_radio_on;
280 rf->switch_radio_off = rf2959_switch_radio_off;
281 return 0;
282 }
283