1 /* Driver for Realtek RTS51xx USB card reader 2 * Header file 3 * 4 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2, or (at your option) any 9 * later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 * Author: 20 * wwang (wei_wang@realsil.com.cn) 21 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 22 * Maintainer: 23 * Edwin Rong (edwin_rong@realsil.com.cn) 24 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China 25 */ 26 27 #ifndef __RTS51X_XD_H 28 #define __RTS51X_XD_H 29 30 /* Error Codes */ 31 #define XD_NO_ERROR 0x00 32 #define XD_NO_MEMORY 0x80 33 #define XD_PRG_ERROR 0x40 34 #define XD_NO_CARD 0x20 35 #define XD_READ_FAIL 0x10 36 #define XD_ERASE_FAIL 0x08 37 #define XD_WRITE_FAIL 0x04 38 #define XD_ECC_ERROR 0x02 39 #define XD_TO_ERROR 0x01 40 41 /* XD Commands */ 42 #define READ1_1 0x00 43 #define READ1_2 0x01 44 #define READ2 0x50 45 #define READ_ID 0x90 46 #define RESET 0xff 47 #define PAGE_PRG_1 0x80 48 #define PAGE_PRG_2 0x10 49 #define BLK_ERASE_1 0x60 50 #define BLK_ERASE_2 0xD0 51 #define READ_STS 0x70 52 #define READ_xD_ID 0x9A 53 #define COPY_BACK_512 0x8A 54 #define COPY_BACK_2K 0x85 55 #define READ1_1_2 0x30 56 #define READ1_1_3 0x35 57 #define CHG_DAT_OUT_1 0x05 58 #define RDM_DAT_OUT_1 0x05 59 #define CHG_DAT_OUT_2 0xE0 60 #define RDM_DAT_OUT_2 0xE0 61 #define CHG_DAT_OUT_2 0xE0 62 #define CHG_DAT_IN_1 0x85 63 #define CACHE_PRG 0x15 64 65 /* Redundant Area Related */ 66 #define XD_EXTRA_SIZE 0x10 67 #define XD_2K_EXTRA_SIZE 0x40 68 69 /* Define for XD Status */ 70 #define NOT_WRITE_PROTECTED 0x80 71 #define READY_STATE 0x40 72 #define PROGRAM_ERROR 0x01 73 #define PROGRAM_ERROR_N_1 0x02 74 #define INTERNAL_READY 0x20 75 #define READY_FLAG 0x5F 76 77 /* Define for device code */ 78 #define XD_8M_X8_512 0xE6 79 #define XD_16M_X8_512 0x73 80 #define XD_32M_X8_512 0x75 81 #define XD_64M_X8_512 0x76 82 #define XD_128M_X8_512 0x79 83 #define XD_256M_X8_512 0x71 84 #define XD_128M_X8_2048 0xF1 85 #define XD_256M_X8_2048 0xDA 86 #define XD_512M_X8 0xDC 87 #define XD_128M_X16_2048 0xC1 88 #define XD_4M_X8_512_1 0xE3 89 #define XD_4M_X8_512_2 0xE5 90 #define xD_1G_X8_512 0xD3 91 #define xD_2G_X8_512 0xD5 92 93 #define XD_ID_CODE 0xB5 94 95 #define VENDOR_BLOCK 0xEFFF 96 #define CIS_BLOCK 0xDFFF 97 98 #define BLK_NOT_FOUND 0xFFFFFFFF 99 100 #define NO_NEW_BLK 0xFFFFFFFF 101 102 #define PAGE_CORRECTABLE 0x0 103 #define PAGE_NOTCORRECTABLE 0x1 104 105 #define NO_OFFSET 0x0 106 #define WITH_OFFSET 0x1 107 108 #define Sect_Per_Page 4 109 #define XD_ADDR_MODE_2C XD_ADDR_MODE_2A 110 111 #define ZONE0_BAD_BLOCK 23 112 #define NOT_ZONE0_BAD_BLOCK 24 113 114 /* Assign address mode */ 115 #define XD_RW_ADDR 0x01 116 #define XD_ERASE_ADDR 0x02 117 118 /* Macro Definition */ 119 #define XD_PAGE_512(xd_card) \ 120 do { \ 121 (xd_card)->block_shift = 5; \ 122 (xd_card)->page_off = 0x1F; \ 123 } while (0) 124 125 #define XD_SET_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag |= 0x01) 126 #define XD_CLR_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag &= ~0x01) 127 #define XD_CHK_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag & 0x01) 128 129 #define XD_SET_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag |= 0x02) 130 #define XD_CLR_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag &= ~0x02) 131 #define XD_CHK_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag & 0x02) 132 133 #define XD_SET_MBR_FAIL(xd_card) ((xd_card)->multi_flag |= 0x04) 134 #define XD_CLR_MBR_FAIL(xd_card) ((xd_card)->multi_flag &= ~0x04) 135 #define XD_CHK_MBR_FAIL(xd_card) ((xd_card)->multi_flag & 0x04) 136 137 #define XD_SET_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag |= 0x08) 138 #define XD_CLR_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag &= ~0x08) 139 #define XD_CHK_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag & 0x08) 140 141 #define XD_SET_4MB(xd_card) ((xd_card)->multi_flag |= 0x10) 142 #define XD_CLR_4MB(xd_card) ((xd_card)->multi_flag &= ~0x10) 143 #define XD_CHK_4MB(xd_card) ((xd_card)->multi_flag & 0x10) 144 145 #define XD_SET_ECC_ERR(xd_card) ((xd_card)->multi_flag |= 0x40) 146 #define XD_CLR_ECC_ERR(xd_card) ((xd_card)->multi_flag &= ~0x40) 147 #define XD_CHK_ECC_ERR(xd_card) ((xd_card)->multi_flag & 0x40) 148 149 /* Offset in xD redundant buffer */ 150 #define PAGE_STATUS 0 151 #define BLOCK_STATUS 1 152 #define BLOCK_ADDR1_L 2 153 #define BLOCK_ADDR1_H 3 154 #define BLOCK_ADDR2_L 4 155 #define BLOCK_ADDR2_H 5 156 #define RESERVED0 6 157 #define RESERVED1 7 158 #define RESERVED2 8 159 #define RESERVED3 9 160 #define PARITY 10 161 162 /* For CIS block */ 163 #define CIS0_0 0 164 #define CIS0_1 1 165 #define CIS0_2 2 166 #define CIS0_3 3 167 #define CIS0_4 4 168 #define CIS0_5 5 169 #define CIS0_6 6 170 #define CIS0_7 7 171 #define CIS0_8 8 172 #define CIS0_9 9 173 #define CIS1_0 256 174 #define CIS1_1 (256 + 1) 175 #define CIS1_2 (256 + 2) 176 #define CIS1_3 (256 + 3) 177 #define CIS1_4 (256 + 4) 178 #define CIS1_5 (256 + 5) 179 #define CIS1_6 (256 + 6) 180 #define CIS1_7 (256 + 7) 181 #define CIS1_8 (256 + 8) 182 #define CIS1_9 (256 + 9) 183 184 int reset_xd_card(struct rts51x_chip *chip); 185 int xd_delay_write(struct rts51x_chip *chip); 186 int xd_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector, 187 u16 sector_cnt); 188 void xd_free_l2p_tbl(struct rts51x_chip *chip); 189 void xd_cleanup_work(struct rts51x_chip *chip); 190 int xd_power_off_card3v3(struct rts51x_chip *chip); 191 int release_xd_card(struct rts51x_chip *chip); 192 193 #endif /* __RTS51X_XD_H */ 194