1 #ifndef _VME_PIO2_H_ 2 #define _VME_PIO2_H_ 3 4 #define PIO2_CARDS_MAX 32 5 6 #define PIO2_VARIANT_LENGTH 5 7 8 #define PIO2_NUM_CHANNELS 32 9 #define PIO2_NUM_IRQS 11 10 #define PIO2_NUM_CNTRS 6 11 12 #define PIO2_REGS_SIZE 0x40 13 14 #define PIO2_REGS_DATA0 0x0 15 #define PIO2_REGS_DATA1 0x1 16 #define PIO2_REGS_DATA2 0x2 17 #define PIO2_REGS_DATA3 0x3 18 19 static const int PIO2_REGS_DATA[4] = { PIO2_REGS_DATA0, PIO2_REGS_DATA1, 20 PIO2_REGS_DATA2, PIO2_REGS_DATA3 }; 21 22 #define PIO2_REGS_INT_STAT0 0x8 23 #define PIO2_REGS_INT_STAT1 0x9 24 #define PIO2_REGS_INT_STAT2 0xa 25 #define PIO2_REGS_INT_STAT3 0xb 26 27 static const int PIO2_REGS_INT_STAT[4] = { PIO2_REGS_INT_STAT0, 28 PIO2_REGS_INT_STAT1, 29 PIO2_REGS_INT_STAT2, 30 PIO2_REGS_INT_STAT3 }; 31 32 #define PIO2_REGS_INT_STAT_CNTR 0xc 33 #define PIO2_REGS_INT_MASK0 0x10 34 #define PIO2_REGS_INT_MASK1 0x11 35 #define PIO2_REGS_INT_MASK2 0x12 36 #define PIO2_REGS_INT_MASK3 0x13 37 #define PIO2_REGS_INT_MASK4 0x14 38 #define PIO2_REGS_INT_MASK5 0x15 39 #define PIO2_REGS_INT_MASK6 0x16 40 #define PIO2_REGS_INT_MASK7 0x17 41 42 static const int PIO2_REGS_INT_MASK[8] = { PIO2_REGS_INT_MASK0, 43 PIO2_REGS_INT_MASK1, 44 PIO2_REGS_INT_MASK2, 45 PIO2_REGS_INT_MASK3, 46 PIO2_REGS_INT_MASK4, 47 PIO2_REGS_INT_MASK5, 48 PIO2_REGS_INT_MASK6, 49 PIO2_REGS_INT_MASK7 }; 50 51 52 53 #define PIO2_REGS_CTRL 0x18 54 #define PIO2_REGS_VME_VECTOR 0x19 55 #define PIO2_REGS_CNTR0 0x20 56 #define PIO2_REGS_CNTR1 0x22 57 #define PIO2_REGS_CNTR2 0x24 58 #define PIO2_REGS_CTRL_WRD0 0x26 59 #define PIO2_REGS_CNTR3 0x28 60 #define PIO2_REGS_CNTR4 0x2a 61 #define PIO2_REGS_CNTR5 0x2c 62 #define PIO2_REGS_CTRL_WRD1 0x2e 63 64 #define PIO2_REGS_ID 0x30 65 66 67 /* PIO2_REGS_DATAx (0x0 - 0x3) */ 68 69 static const int PIO2_CHANNEL_BANK[32] = { 0, 0, 0, 0, 0, 0, 0, 0, 70 1, 1, 1, 1, 1, 1, 1, 1, 71 2, 2, 2, 2, 2, 2, 2, 2, 72 3, 3, 3, 3, 3, 3, 3, 3 }; 73 74 #define PIO2_CHANNEL0_BIT (1 << 0) 75 #define PIO2_CHANNEL1_BIT (1 << 1) 76 #define PIO2_CHANNEL2_BIT (1 << 2) 77 #define PIO2_CHANNEL3_BIT (1 << 3) 78 #define PIO2_CHANNEL4_BIT (1 << 4) 79 #define PIO2_CHANNEL5_BIT (1 << 5) 80 #define PIO2_CHANNEL6_BIT (1 << 6) 81 #define PIO2_CHANNEL7_BIT (1 << 7) 82 #define PIO2_CHANNEL8_BIT (1 << 0) 83 #define PIO2_CHANNEL9_BIT (1 << 1) 84 #define PIO2_CHANNEL10_BIT (1 << 2) 85 #define PIO2_CHANNEL11_BIT (1 << 3) 86 #define PIO2_CHANNEL12_BIT (1 << 4) 87 #define PIO2_CHANNEL13_BIT (1 << 5) 88 #define PIO2_CHANNEL14_BIT (1 << 6) 89 #define PIO2_CHANNEL15_BIT (1 << 7) 90 #define PIO2_CHANNEL16_BIT (1 << 0) 91 #define PIO2_CHANNEL17_BIT (1 << 1) 92 #define PIO2_CHANNEL18_BIT (1 << 2) 93 #define PIO2_CHANNEL19_BIT (1 << 3) 94 #define PIO2_CHANNEL20_BIT (1 << 4) 95 #define PIO2_CHANNEL21_BIT (1 << 5) 96 #define PIO2_CHANNEL22_BIT (1 << 6) 97 #define PIO2_CHANNEL23_BIT (1 << 7) 98 #define PIO2_CHANNEL24_BIT (1 << 0) 99 #define PIO2_CHANNEL25_BIT (1 << 1) 100 #define PIO2_CHANNEL26_BIT (1 << 2) 101 #define PIO2_CHANNEL27_BIT (1 << 3) 102 #define PIO2_CHANNEL28_BIT (1 << 4) 103 #define PIO2_CHANNEL29_BIT (1 << 5) 104 #define PIO2_CHANNEL30_BIT (1 << 6) 105 #define PIO2_CHANNEL31_BIT (1 << 7) 106 107 static const int PIO2_CHANNEL_BIT[32] = { PIO2_CHANNEL0_BIT, PIO2_CHANNEL1_BIT, 108 PIO2_CHANNEL2_BIT, PIO2_CHANNEL3_BIT, 109 PIO2_CHANNEL4_BIT, PIO2_CHANNEL5_BIT, 110 PIO2_CHANNEL6_BIT, PIO2_CHANNEL7_BIT, 111 PIO2_CHANNEL8_BIT, PIO2_CHANNEL9_BIT, 112 PIO2_CHANNEL10_BIT, PIO2_CHANNEL11_BIT, 113 PIO2_CHANNEL12_BIT, PIO2_CHANNEL13_BIT, 114 PIO2_CHANNEL14_BIT, PIO2_CHANNEL15_BIT, 115 PIO2_CHANNEL16_BIT, PIO2_CHANNEL17_BIT, 116 PIO2_CHANNEL18_BIT, PIO2_CHANNEL19_BIT, 117 PIO2_CHANNEL20_BIT, PIO2_CHANNEL21_BIT, 118 PIO2_CHANNEL22_BIT, PIO2_CHANNEL23_BIT, 119 PIO2_CHANNEL24_BIT, PIO2_CHANNEL25_BIT, 120 PIO2_CHANNEL26_BIT, PIO2_CHANNEL27_BIT, 121 PIO2_CHANNEL28_BIT, PIO2_CHANNEL29_BIT, 122 PIO2_CHANNEL30_BIT, PIO2_CHANNEL31_BIT 123 }; 124 125 /* PIO2_REGS_INT_STAT_CNTR (0xc) */ 126 #define PIO2_COUNTER0 (1 << 0) 127 #define PIO2_COUNTER1 (1 << 1) 128 #define PIO2_COUNTER2 (1 << 2) 129 #define PIO2_COUNTER3 (1 << 3) 130 #define PIO2_COUNTER4 (1 << 4) 131 #define PIO2_COUNTER5 (1 << 5) 132 133 static const int PIO2_COUNTER[6] = { PIO2_COUNTER0, PIO2_COUNTER1, 134 PIO2_COUNTER2, PIO2_COUNTER3, 135 PIO2_COUNTER4, PIO2_COUNTER5 }; 136 137 /* PIO2_REGS_CTRL (0x18) */ 138 #define PIO2_VME_INT_MASK 0x7 139 #define PIO2_LED (1 << 6) 140 #define PIO2_LOOP (1 << 7) 141 142 /* PIO2_REGS_VME_VECTOR (0x19) */ 143 #define PIO2_VME_VECTOR_SPUR 0x0 144 #define PIO2_VME_VECTOR_BANK0 0x1 145 #define PIO2_VME_VECTOR_BANK1 0x2 146 #define PIO2_VME_VECTOR_BANK2 0x3 147 #define PIO2_VME_VECTOR_BANK3 0x4 148 #define PIO2_VME_VECTOR_CNTR0 0x5 149 #define PIO2_VME_VECTOR_CNTR1 0x6 150 #define PIO2_VME_VECTOR_CNTR2 0x7 151 #define PIO2_VME_VECTOR_CNTR3 0x8 152 #define PIO2_VME_VECTOR_CNTR4 0x9 153 #define PIO2_VME_VECTOR_CNTR5 0xa 154 155 #define PIO2_VME_VECTOR_MASK 0xf0 156 157 static const int PIO2_VECTOR_BANK[4] = { PIO2_VME_VECTOR_BANK0, 158 PIO2_VME_VECTOR_BANK1, 159 PIO2_VME_VECTOR_BANK2, 160 PIO2_VME_VECTOR_BANK3 }; 161 162 static const int PIO2_VECTOR_CNTR[6] = { PIO2_VME_VECTOR_CNTR0, 163 PIO2_VME_VECTOR_CNTR1, 164 PIO2_VME_VECTOR_CNTR2, 165 PIO2_VME_VECTOR_CNTR3, 166 PIO2_VME_VECTOR_CNTR4, 167 PIO2_VME_VECTOR_CNTR5 }; 168 169 /* PIO2_REGS_CNTRx (0x20 - 0x24 & 0x28 - 0x2c) */ 170 171 static const int PIO2_CNTR_DATA[6] = { PIO2_REGS_CNTR0, PIO2_REGS_CNTR1, 172 PIO2_REGS_CNTR2, PIO2_REGS_CNTR3, 173 PIO2_REGS_CNTR4, PIO2_REGS_CNTR5 }; 174 175 /* PIO2_REGS_CTRL_WRDx (0x26 & 0x2e) */ 176 177 static const int PIO2_CNTR_CTRL[6] = { PIO2_REGS_CTRL_WRD0, 178 PIO2_REGS_CTRL_WRD0, 179 PIO2_REGS_CTRL_WRD0, 180 PIO2_REGS_CTRL_WRD1, 181 PIO2_REGS_CTRL_WRD1, 182 PIO2_REGS_CTRL_WRD1 }; 183 184 #define PIO2_CNTR_SC_DEV0 0 185 #define PIO2_CNTR_SC_DEV1 (1 << 6) 186 #define PIO2_CNTR_SC_DEV2 (2 << 6) 187 #define PIO2_CNTR_SC_RDBACK (3 << 6) 188 189 static const int PIO2_CNTR_SC_DEV[6] = { PIO2_CNTR_SC_DEV0, PIO2_CNTR_SC_DEV1, 190 PIO2_CNTR_SC_DEV2, PIO2_CNTR_SC_DEV0, 191 PIO2_CNTR_SC_DEV1, PIO2_CNTR_SC_DEV2 }; 192 193 #define PIO2_CNTR_RW_LATCH 0 194 #define PIO2_CNTR_RW_LSB (1 << 4) 195 #define PIO2_CNTR_RW_MSB (2 << 4) 196 #define PIO2_CNTR_RW_BOTH (3 << 4) 197 198 #define PIO2_CNTR_MODE0 0 199 #define PIO2_CNTR_MODE1 (1 << 1) 200 #define PIO2_CNTR_MODE2 (2 << 1) 201 #define PIO2_CNTR_MODE3 (3 << 1) 202 #define PIO2_CNTR_MODE4 (4 << 1) 203 #define PIO2_CNTR_MODE5 (5 << 1) 204 205 #define PIO2_CNTR_BCD 1 206 207 208 209 enum pio2_bank_config { NOFIT, INPUT, OUTPUT, BOTH }; 210 enum pio2_int_config { NONE = 0, LOW2HIGH = 1, HIGH2LOW = 2, EITHER = 4 }; 211 212 /* Bank configuration structure */ 213 struct pio2_io_bank { 214 enum pio2_bank_config config; 215 u8 value; 216 enum pio2_int_config irq[8]; 217 }; 218 219 /* Counter configuration structure */ 220 struct pio2_cntr { 221 int mode; 222 int count; 223 }; 224 225 struct pio2_card { 226 int id; 227 int bus; 228 long base; 229 int irq_vector; 230 int irq_level; 231 char variant[6]; 232 int led; 233 234 struct vme_dev *vdev; 235 struct vme_resource *window; 236 237 struct gpio_chip gc; 238 struct pio2_io_bank bank[4]; 239 240 struct pio2_cntr cntr[6]; 241 }; 242 243 int pio2_cntr_reset(struct pio2_card *); 244 245 int pio2_gpio_reset(struct pio2_card *); 246 int __devinit pio2_gpio_init(struct pio2_card *); 247 void pio2_gpio_exit(struct pio2_card *); 248 249 #endif /* _VME_PIO2_H_ */ 250