212 	while (!(readw(&reg->control) & CCA)) {  in bfin_can_set_reset_mode()
265 	writew(readw(&reg->control) & ~CCR, &reg->control);  in bfin_can_set_normal_mode()
267 	while (readw(&reg->status) & CCA) {  in bfin_can_set_normal_mode()
333 	u16 cec = readw(&reg->cec);  in bfin_can_get_berr_counter()
403 		cf->can_id = ((readw(&reg->chl[RECEIVE_EXT_CHL].id1)  in bfin_can_rx()
405 			     + readw(&reg->chl[RECEIVE_EXT_CHL].id0);  in bfin_can_rx()
410 		cf->can_id = (readw(&reg->chl[RECEIVE_STD_CHL].id1)  in bfin_can_rx()
414 	if (readw(&reg->chl[obj].id1) & RTR)  in bfin_can_rx()
418 	cf->can_dlc = get_can_dlc(readw(&reg->chl[obj].dlc) & 0xF);  in bfin_can_rx()
422 		val = readw(&reg->chl[obj].data[i]);  in bfin_can_rx()
475 		u16 cec = readw(&reg->cec);  in bfin_can_err()
523 	if ((irq == priv->tx_irq) && readw(&reg->mbtif2)) {  in bfin_can_interrupt()
527 		stats->tx_bytes += readw(&reg->chl[TRANSMIT_CHL].dlc);  in bfin_can_interrupt()
530 	} else if ((irq == priv->rx_irq) && readw(&reg->mbrif1)) {  in bfin_can_interrupt()
532 		isrc = readw(&reg->mbrif1);  in bfin_can_interrupt()
535 	} else if ((irq == priv->err_irq) && readw(&reg->gis)) {  in bfin_can_interrupt()
537 		isrc = readw(&reg->gis);  in bfin_can_interrupt()
538 		status = readw(&reg->esr);  in bfin_can_interrupt()
738 		writew(readw(&reg->control) | SMR, &reg->control);  in bfin_can_suspend()
739 		while (!(readw(&reg->intr) & SMACK)) {  in bfin_can_suspend()