1 /*
2 * Blackfin On-Chip CAN Driver
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/bitops.h>
14 #include <linux/interrupt.h>
15 #include <linux/errno.h>
16 #include <linux/netdevice.h>
17 #include <linux/skbuff.h>
18 #include <linux/platform_device.h>
19
20 #include <linux/can/dev.h>
21 #include <linux/can/error.h>
22
23 #include <asm/portmux.h>
24
25 #define DRV_NAME "bfin_can"
26 #define BFIN_CAN_TIMEOUT 100
27 #define TX_ECHO_SKB_MAX 1
28
29 /* transmit and receive channels */
30 #define TRANSMIT_CHL 24
31 #define RECEIVE_STD_CHL 0
32 #define RECEIVE_EXT_CHL 4
33 #define RECEIVE_RTR_CHL 8
34 #define RECEIVE_EXT_RTR_CHL 12
35 #define MAX_CHL_NUMBER 32
36
37 /* All Blackfin system MMRs are padded to 32bits even if the register
38 * itself is only 16bits. So use a helper macro to streamline this
39 */
40 #define __BFP(m) u16 m; u16 __pad_##m
41
42 /* bfin can registers layout */
43 struct bfin_can_mask_regs {
44 __BFP(aml);
45 __BFP(amh);
46 };
47
48 struct bfin_can_channel_regs {
49 /* data[0,2,4,6] -> data{0,1,2,3} while data[1,3,5,7] is padding */
50 u16 data[8];
51 __BFP(dlc);
52 __BFP(tsv);
53 __BFP(id0);
54 __BFP(id1);
55 };
56
57 struct bfin_can_regs {
58 /* global control and status registers */
59 __BFP(mc1); /* offset 0x00 */
60 __BFP(md1); /* offset 0x04 */
61 __BFP(trs1); /* offset 0x08 */
62 __BFP(trr1); /* offset 0x0c */
63 __BFP(ta1); /* offset 0x10 */
64 __BFP(aa1); /* offset 0x14 */
65 __BFP(rmp1); /* offset 0x18 */
66 __BFP(rml1); /* offset 0x1c */
67 __BFP(mbtif1); /* offset 0x20 */
68 __BFP(mbrif1); /* offset 0x24 */
69 __BFP(mbim1); /* offset 0x28 */
70 __BFP(rfh1); /* offset 0x2c */
71 __BFP(opss1); /* offset 0x30 */
72 u32 __pad1[3];
73 __BFP(mc2); /* offset 0x40 */
74 __BFP(md2); /* offset 0x44 */
75 __BFP(trs2); /* offset 0x48 */
76 __BFP(trr2); /* offset 0x4c */
77 __BFP(ta2); /* offset 0x50 */
78 __BFP(aa2); /* offset 0x54 */
79 __BFP(rmp2); /* offset 0x58 */
80 __BFP(rml2); /* offset 0x5c */
81 __BFP(mbtif2); /* offset 0x60 */
82 __BFP(mbrif2); /* offset 0x64 */
83 __BFP(mbim2); /* offset 0x68 */
84 __BFP(rfh2); /* offset 0x6c */
85 __BFP(opss2); /* offset 0x70 */
86 u32 __pad2[3];
87 __BFP(clock); /* offset 0x80 */
88 __BFP(timing); /* offset 0x84 */
89 __BFP(debug); /* offset 0x88 */
90 __BFP(status); /* offset 0x8c */
91 __BFP(cec); /* offset 0x90 */
92 __BFP(gis); /* offset 0x94 */
93 __BFP(gim); /* offset 0x98 */
94 __BFP(gif); /* offset 0x9c */
95 __BFP(control); /* offset 0xa0 */
96 __BFP(intr); /* offset 0xa4 */
97 __BFP(version); /* offset 0xa8 */
98 __BFP(mbtd); /* offset 0xac */
99 __BFP(ewr); /* offset 0xb0 */
100 __BFP(esr); /* offset 0xb4 */
101 u32 __pad3[2];
102 __BFP(ucreg); /* offset 0xc0 */
103 __BFP(uccnt); /* offset 0xc4 */
104 __BFP(ucrc); /* offset 0xc8 */
105 __BFP(uccnf); /* offset 0xcc */
106 u32 __pad4[1];
107 __BFP(version2); /* offset 0xd4 */
108 u32 __pad5[10];
109
110 /* channel(mailbox) mask and message registers */
111 struct bfin_can_mask_regs msk[MAX_CHL_NUMBER]; /* offset 0x100 */
112 struct bfin_can_channel_regs chl[MAX_CHL_NUMBER]; /* offset 0x200 */
113 };
114
115 #undef __BFP
116
117 #define SRS 0x0001 /* Software Reset */
118 #define SER 0x0008 /* Stuff Error */
119 #define BOIM 0x0008 /* Enable Bus Off Interrupt */
120 #define CCR 0x0080 /* CAN Configuration Mode Request */
121 #define CCA 0x0080 /* Configuration Mode Acknowledge */
122 #define SAM 0x0080 /* Sampling */
123 #define AME 0x8000 /* Acceptance Mask Enable */
124 #define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
125 #define RMLIS 0x0080 /* RX Message Lost IRQ Status */
126 #define RTR 0x4000 /* Remote Frame Transmission Request */
127 #define BOIS 0x0008 /* Bus Off IRQ Status */
128 #define IDE 0x2000 /* Identifier Extension */
129 #define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
130 #define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
131 #define EWTIS 0x0001 /* TX Error Count IRQ Status */
132 #define EWRIS 0x0002 /* RX Error Count IRQ Status */
133 #define BEF 0x0040 /* Bit Error Flag */
134 #define FER 0x0080 /* Form Error Flag */
135 #define SMR 0x0020 /* Sleep Mode Request */
136 #define SMACK 0x0008 /* Sleep Mode Acknowledge */
137
138 /*
139 * bfin can private data
140 */
141 struct bfin_can_priv {
142 struct can_priv can; /* must be the first member */
143 struct net_device *dev;
144 void __iomem *membase;
145 int rx_irq;
146 int tx_irq;
147 int err_irq;
148 unsigned short *pin_list;
149 };
150
151 /*
152 * bfin can timing parameters
153 */
154 static const struct can_bittiming_const bfin_can_bittiming_const = {
155 .name = DRV_NAME,
156 .tseg1_min = 1,
157 .tseg1_max = 16,
158 .tseg2_min = 1,
159 .tseg2_max = 8,
160 .sjw_max = 4,
161 /*
162 * Although the BRP field can be set to any value, it is recommended
163 * that the value be greater than or equal to 4, as restrictions
164 * apply to the bit timing configuration when BRP is less than 4.
165 */
166 .brp_min = 4,
167 .brp_max = 1024,
168 .brp_inc = 1,
169 };
170
bfin_can_set_bittiming(struct net_device * dev)171 static int bfin_can_set_bittiming(struct net_device *dev)
172 {
173 struct bfin_can_priv *priv = netdev_priv(dev);
174 struct bfin_can_regs __iomem *reg = priv->membase;
175 struct can_bittiming *bt = &priv->can.bittiming;
176 u16 clk, timing;
177
178 clk = bt->brp - 1;
179 timing = ((bt->sjw - 1) << 8) | (bt->prop_seg + bt->phase_seg1 - 1) |
180 ((bt->phase_seg2 - 1) << 4);
181
182 /*
183 * If the SAM bit is set, the input signal is oversampled three times
184 * at the SCLK rate.
185 */
186 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
187 timing |= SAM;
188
189 writew(clk, ®->clock);
190 writew(timing, ®->timing);
191
192 netdev_info(dev, "setting CLOCK=0x%04x TIMING=0x%04x\n", clk, timing);
193
194 return 0;
195 }
196
bfin_can_set_reset_mode(struct net_device * dev)197 static void bfin_can_set_reset_mode(struct net_device *dev)
198 {
199 struct bfin_can_priv *priv = netdev_priv(dev);
200 struct bfin_can_regs __iomem *reg = priv->membase;
201 int timeout = BFIN_CAN_TIMEOUT;
202 int i;
203
204 /* disable interrupts */
205 writew(0, ®->mbim1);
206 writew(0, ®->mbim2);
207 writew(0, ®->gim);
208
209 /* reset can and enter configuration mode */
210 writew(SRS | CCR, ®->control);
211 writew(CCR, ®->control);
212 while (!(readw(®->control) & CCA)) {
213 udelay(10);
214 if (--timeout == 0) {
215 netdev_err(dev, "fail to enter configuration mode\n");
216 BUG();
217 }
218 }
219
220 /*
221 * All mailbox configurations are marked as inactive
222 * by writing to CAN Mailbox Configuration Registers 1 and 2
223 * For all bits: 0 - Mailbox disabled, 1 - Mailbox enabled
224 */
225 writew(0, ®->mc1);
226 writew(0, ®->mc2);
227
228 /* Set Mailbox Direction */
229 writew(0xFFFF, ®->md1); /* mailbox 1-16 are RX */
230 writew(0, ®->md2); /* mailbox 17-32 are TX */
231
232 /* RECEIVE_STD_CHL */
233 for (i = 0; i < 2; i++) {
234 writew(0, ®->chl[RECEIVE_STD_CHL + i].id0);
235 writew(AME, ®->chl[RECEIVE_STD_CHL + i].id1);
236 writew(0, ®->chl[RECEIVE_STD_CHL + i].dlc);
237 writew(0x1FFF, ®->msk[RECEIVE_STD_CHL + i].amh);
238 writew(0xFFFF, ®->msk[RECEIVE_STD_CHL + i].aml);
239 }
240
241 /* RECEIVE_EXT_CHL */
242 for (i = 0; i < 2; i++) {
243 writew(0, ®->chl[RECEIVE_EXT_CHL + i].id0);
244 writew(AME | IDE, ®->chl[RECEIVE_EXT_CHL + i].id1);
245 writew(0, ®->chl[RECEIVE_EXT_CHL + i].dlc);
246 writew(0x1FFF, ®->msk[RECEIVE_EXT_CHL + i].amh);
247 writew(0xFFFF, ®->msk[RECEIVE_EXT_CHL + i].aml);
248 }
249
250 writew(BIT(TRANSMIT_CHL - 16), ®->mc2);
251 writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mc1);
252
253 priv->can.state = CAN_STATE_STOPPED;
254 }
255
bfin_can_set_normal_mode(struct net_device * dev)256 static void bfin_can_set_normal_mode(struct net_device *dev)
257 {
258 struct bfin_can_priv *priv = netdev_priv(dev);
259 struct bfin_can_regs __iomem *reg = priv->membase;
260 int timeout = BFIN_CAN_TIMEOUT;
261
262 /*
263 * leave configuration mode
264 */
265 writew(readw(®->control) & ~CCR, ®->control);
266
267 while (readw(®->status) & CCA) {
268 udelay(10);
269 if (--timeout == 0) {
270 netdev_err(dev, "fail to leave configuration mode\n");
271 BUG();
272 }
273 }
274
275 /*
276 * clear _All_ tx and rx interrupts
277 */
278 writew(0xFFFF, ®->mbtif1);
279 writew(0xFFFF, ®->mbtif2);
280 writew(0xFFFF, ®->mbrif1);
281 writew(0xFFFF, ®->mbrif2);
282
283 /*
284 * clear global interrupt status register
285 */
286 writew(0x7FF, ®->gis); /* overwrites with '1' */
287
288 /*
289 * Initialize Interrupts
290 * - set bits in the mailbox interrupt mask register
291 * - global interrupt mask
292 */
293 writew(BIT(RECEIVE_STD_CHL) + BIT(RECEIVE_EXT_CHL), ®->mbim1);
294 writew(BIT(TRANSMIT_CHL - 16), ®->mbim2);
295
296 writew(EPIM | BOIM | RMLIM, ®->gim);
297 }
298
bfin_can_start(struct net_device * dev)299 static void bfin_can_start(struct net_device *dev)
300 {
301 struct bfin_can_priv *priv = netdev_priv(dev);
302
303 /* enter reset mode */
304 if (priv->can.state != CAN_STATE_STOPPED)
305 bfin_can_set_reset_mode(dev);
306
307 /* leave reset mode */
308 bfin_can_set_normal_mode(dev);
309 }
310
bfin_can_set_mode(struct net_device * dev,enum can_mode mode)311 static int bfin_can_set_mode(struct net_device *dev, enum can_mode mode)
312 {
313 switch (mode) {
314 case CAN_MODE_START:
315 bfin_can_start(dev);
316 if (netif_queue_stopped(dev))
317 netif_wake_queue(dev);
318 break;
319
320 default:
321 return -EOPNOTSUPP;
322 }
323
324 return 0;
325 }
326
bfin_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)327 static int bfin_can_get_berr_counter(const struct net_device *dev,
328 struct can_berr_counter *bec)
329 {
330 struct bfin_can_priv *priv = netdev_priv(dev);
331 struct bfin_can_regs __iomem *reg = priv->membase;
332
333 u16 cec = readw(®->cec);
334
335 bec->txerr = cec >> 8;
336 bec->rxerr = cec;
337
338 return 0;
339 }
340
bfin_can_start_xmit(struct sk_buff * skb,struct net_device * dev)341 static int bfin_can_start_xmit(struct sk_buff *skb, struct net_device *dev)
342 {
343 struct bfin_can_priv *priv = netdev_priv(dev);
344 struct bfin_can_regs __iomem *reg = priv->membase;
345 struct can_frame *cf = (struct can_frame *)skb->data;
346 u8 dlc = cf->can_dlc;
347 canid_t id = cf->can_id;
348 u8 *data = cf->data;
349 u16 val;
350 int i;
351
352 if (can_dropped_invalid_skb(dev, skb))
353 return NETDEV_TX_OK;
354
355 netif_stop_queue(dev);
356
357 /* fill id */
358 if (id & CAN_EFF_FLAG) {
359 writew(id, ®->chl[TRANSMIT_CHL].id0);
360 val = ((id & 0x1FFF0000) >> 16) | IDE;
361 } else
362 val = (id << 2);
363 if (id & CAN_RTR_FLAG)
364 val |= RTR;
365 writew(val | AME, ®->chl[TRANSMIT_CHL].id1);
366
367 /* fill payload */
368 for (i = 0; i < 8; i += 2) {
369 val = ((7 - i) < dlc ? (data[7 - i]) : 0) +
370 ((6 - i) < dlc ? (data[6 - i] << 8) : 0);
371 writew(val, ®->chl[TRANSMIT_CHL].data[i]);
372 }
373
374 /* fill data length code */
375 writew(dlc, ®->chl[TRANSMIT_CHL].dlc);
376
377 can_put_echo_skb(skb, dev, 0);
378
379 /* set transmit request */
380 writew(BIT(TRANSMIT_CHL - 16), ®->trs2);
381
382 return 0;
383 }
384
bfin_can_rx(struct net_device * dev,u16 isrc)385 static void bfin_can_rx(struct net_device *dev, u16 isrc)
386 {
387 struct bfin_can_priv *priv = netdev_priv(dev);
388 struct net_device_stats *stats = &dev->stats;
389 struct bfin_can_regs __iomem *reg = priv->membase;
390 struct can_frame *cf;
391 struct sk_buff *skb;
392 int obj;
393 int i;
394 u16 val;
395
396 skb = alloc_can_skb(dev, &cf);
397 if (skb == NULL)
398 return;
399
400 /* get id */
401 if (isrc & BIT(RECEIVE_EXT_CHL)) {
402 /* extended frame format (EFF) */
403 cf->can_id = ((readw(®->chl[RECEIVE_EXT_CHL].id1)
404 & 0x1FFF) << 16)
405 + readw(®->chl[RECEIVE_EXT_CHL].id0);
406 cf->can_id |= CAN_EFF_FLAG;
407 obj = RECEIVE_EXT_CHL;
408 } else {
409 /* standard frame format (SFF) */
410 cf->can_id = (readw(®->chl[RECEIVE_STD_CHL].id1)
411 & 0x1ffc) >> 2;
412 obj = RECEIVE_STD_CHL;
413 }
414 if (readw(®->chl[obj].id1) & RTR)
415 cf->can_id |= CAN_RTR_FLAG;
416
417 /* get data length code */
418 cf->can_dlc = get_can_dlc(readw(®->chl[obj].dlc) & 0xF);
419
420 /* get payload */
421 for (i = 0; i < 8; i += 2) {
422 val = readw(®->chl[obj].data[i]);
423 cf->data[7 - i] = (7 - i) < cf->can_dlc ? val : 0;
424 cf->data[6 - i] = (6 - i) < cf->can_dlc ? (val >> 8) : 0;
425 }
426
427 stats->rx_packets++;
428 stats->rx_bytes += cf->can_dlc;
429 netif_rx(skb);
430 }
431
bfin_can_err(struct net_device * dev,u16 isrc,u16 status)432 static int bfin_can_err(struct net_device *dev, u16 isrc, u16 status)
433 {
434 struct bfin_can_priv *priv = netdev_priv(dev);
435 struct bfin_can_regs __iomem *reg = priv->membase;
436 struct net_device_stats *stats = &dev->stats;
437 struct can_frame *cf;
438 struct sk_buff *skb;
439 enum can_state state = priv->can.state;
440
441 skb = alloc_can_err_skb(dev, &cf);
442 if (skb == NULL)
443 return -ENOMEM;
444
445 if (isrc & RMLIS) {
446 /* data overrun interrupt */
447 netdev_dbg(dev, "data overrun interrupt\n");
448 cf->can_id |= CAN_ERR_CRTL;
449 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
450 stats->rx_over_errors++;
451 stats->rx_errors++;
452 }
453
454 if (isrc & BOIS) {
455 netdev_dbg(dev, "bus-off mode interrupt\n");
456 state = CAN_STATE_BUS_OFF;
457 cf->can_id |= CAN_ERR_BUSOFF;
458 priv->can.can_stats.bus_off++;
459 can_bus_off(dev);
460 }
461
462 if (isrc & EPIS) {
463 /* error passive interrupt */
464 netdev_dbg(dev, "error passive interrupt\n");
465 state = CAN_STATE_ERROR_PASSIVE;
466 }
467
468 if ((isrc & EWTIS) || (isrc & EWRIS)) {
469 netdev_dbg(dev, "Error Warning Transmit/Receive Interrupt\n");
470 state = CAN_STATE_ERROR_WARNING;
471 }
472
473 if (state != priv->can.state && (state == CAN_STATE_ERROR_WARNING ||
474 state == CAN_STATE_ERROR_PASSIVE)) {
475 u16 cec = readw(®->cec);
476 u8 rxerr = cec;
477 u8 txerr = cec >> 8;
478
479 cf->can_id |= CAN_ERR_CRTL;
480 if (state == CAN_STATE_ERROR_WARNING) {
481 priv->can.can_stats.error_warning++;
482 cf->data[1] = (txerr > rxerr) ?
483 CAN_ERR_CRTL_TX_WARNING :
484 CAN_ERR_CRTL_RX_WARNING;
485 } else {
486 priv->can.can_stats.error_passive++;
487 cf->data[1] = (txerr > rxerr) ?
488 CAN_ERR_CRTL_TX_PASSIVE :
489 CAN_ERR_CRTL_RX_PASSIVE;
490 }
491 }
492
493 if (status) {
494 priv->can.can_stats.bus_error++;
495
496 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
497
498 if (status & BEF)
499 cf->data[2] |= CAN_ERR_PROT_BIT;
500 else if (status & FER)
501 cf->data[2] |= CAN_ERR_PROT_FORM;
502 else if (status & SER)
503 cf->data[2] |= CAN_ERR_PROT_STUFF;
504 }
505
506 priv->can.state = state;
507
508 stats->rx_packets++;
509 stats->rx_bytes += cf->can_dlc;
510 netif_rx(skb);
511
512 return 0;
513 }
514
bfin_can_interrupt(int irq,void * dev_id)515 static irqreturn_t bfin_can_interrupt(int irq, void *dev_id)
516 {
517 struct net_device *dev = dev_id;
518 struct bfin_can_priv *priv = netdev_priv(dev);
519 struct bfin_can_regs __iomem *reg = priv->membase;
520 struct net_device_stats *stats = &dev->stats;
521 u16 status, isrc;
522
523 if ((irq == priv->tx_irq) && readw(®->mbtif2)) {
524 /* transmission complete interrupt */
525 writew(0xFFFF, ®->mbtif2);
526 stats->tx_packets++;
527 stats->tx_bytes += readw(®->chl[TRANSMIT_CHL].dlc);
528 can_get_echo_skb(dev, 0);
529 netif_wake_queue(dev);
530 } else if ((irq == priv->rx_irq) && readw(®->mbrif1)) {
531 /* receive interrupt */
532 isrc = readw(®->mbrif1);
533 writew(0xFFFF, ®->mbrif1);
534 bfin_can_rx(dev, isrc);
535 } else if ((irq == priv->err_irq) && readw(®->gis)) {
536 /* error interrupt */
537 isrc = readw(®->gis);
538 status = readw(®->esr);
539 writew(0x7FF, ®->gis);
540 bfin_can_err(dev, isrc, status);
541 } else {
542 return IRQ_NONE;
543 }
544
545 return IRQ_HANDLED;
546 }
547
bfin_can_open(struct net_device * dev)548 static int bfin_can_open(struct net_device *dev)
549 {
550 struct bfin_can_priv *priv = netdev_priv(dev);
551 int err;
552
553 /* set chip into reset mode */
554 bfin_can_set_reset_mode(dev);
555
556 /* common open */
557 err = open_candev(dev);
558 if (err)
559 goto exit_open;
560
561 /* register interrupt handler */
562 err = request_irq(priv->rx_irq, &bfin_can_interrupt, 0,
563 "bfin-can-rx", dev);
564 if (err)
565 goto exit_rx_irq;
566 err = request_irq(priv->tx_irq, &bfin_can_interrupt, 0,
567 "bfin-can-tx", dev);
568 if (err)
569 goto exit_tx_irq;
570 err = request_irq(priv->err_irq, &bfin_can_interrupt, 0,
571 "bfin-can-err", dev);
572 if (err)
573 goto exit_err_irq;
574
575 bfin_can_start(dev);
576
577 netif_start_queue(dev);
578
579 return 0;
580
581 exit_err_irq:
582 free_irq(priv->tx_irq, dev);
583 exit_tx_irq:
584 free_irq(priv->rx_irq, dev);
585 exit_rx_irq:
586 close_candev(dev);
587 exit_open:
588 return err;
589 }
590
bfin_can_close(struct net_device * dev)591 static int bfin_can_close(struct net_device *dev)
592 {
593 struct bfin_can_priv *priv = netdev_priv(dev);
594
595 netif_stop_queue(dev);
596 bfin_can_set_reset_mode(dev);
597
598 close_candev(dev);
599
600 free_irq(priv->rx_irq, dev);
601 free_irq(priv->tx_irq, dev);
602 free_irq(priv->err_irq, dev);
603
604 return 0;
605 }
606
alloc_bfin_candev(void)607 static struct net_device *alloc_bfin_candev(void)
608 {
609 struct net_device *dev;
610 struct bfin_can_priv *priv;
611
612 dev = alloc_candev(sizeof(*priv), TX_ECHO_SKB_MAX);
613 if (!dev)
614 return NULL;
615
616 priv = netdev_priv(dev);
617
618 priv->dev = dev;
619 priv->can.bittiming_const = &bfin_can_bittiming_const;
620 priv->can.do_set_bittiming = bfin_can_set_bittiming;
621 priv->can.do_set_mode = bfin_can_set_mode;
622 priv->can.do_get_berr_counter = bfin_can_get_berr_counter;
623 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
624
625 return dev;
626 }
627
628 static const struct net_device_ops bfin_can_netdev_ops = {
629 .ndo_open = bfin_can_open,
630 .ndo_stop = bfin_can_close,
631 .ndo_start_xmit = bfin_can_start_xmit,
632 .ndo_change_mtu = can_change_mtu,
633 };
634
bfin_can_probe(struct platform_device * pdev)635 static int bfin_can_probe(struct platform_device *pdev)
636 {
637 int err;
638 struct net_device *dev;
639 struct bfin_can_priv *priv;
640 struct resource *res_mem, *rx_irq, *tx_irq, *err_irq;
641 unsigned short *pdata;
642
643 pdata = dev_get_platdata(&pdev->dev);
644 if (!pdata) {
645 dev_err(&pdev->dev, "No platform data provided!\n");
646 err = -EINVAL;
647 goto exit;
648 }
649
650 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
651 rx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
652 tx_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
653 err_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
654 if (!res_mem || !rx_irq || !tx_irq || !err_irq) {
655 err = -EINVAL;
656 goto exit;
657 }
658
659 /* request peripheral pins */
660 err = peripheral_request_list(pdata, dev_name(&pdev->dev));
661 if (err)
662 goto exit;
663
664 dev = alloc_bfin_candev();
665 if (!dev) {
666 err = -ENOMEM;
667 goto exit_peri_pin_free;
668 }
669
670 priv = netdev_priv(dev);
671
672 priv->membase = devm_ioremap_resource(&pdev->dev, res_mem);
673 if (IS_ERR(priv->membase)) {
674 err = PTR_ERR(priv->membase);
675 goto exit_peri_pin_free;
676 }
677
678 priv->rx_irq = rx_irq->start;
679 priv->tx_irq = tx_irq->start;
680 priv->err_irq = err_irq->start;
681 priv->pin_list = pdata;
682 priv->can.clock.freq = get_sclk();
683
684 platform_set_drvdata(pdev, dev);
685 SET_NETDEV_DEV(dev, &pdev->dev);
686
687 dev->flags |= IFF_ECHO; /* we support local echo */
688 dev->netdev_ops = &bfin_can_netdev_ops;
689
690 bfin_can_set_reset_mode(dev);
691
692 err = register_candev(dev);
693 if (err) {
694 dev_err(&pdev->dev, "registering failed (err=%d)\n", err);
695 goto exit_candev_free;
696 }
697
698 dev_info(&pdev->dev,
699 "%s device registered"
700 "(®_base=%p, rx_irq=%d, tx_irq=%d, err_irq=%d, sclk=%d)\n",
701 DRV_NAME, priv->membase, priv->rx_irq,
702 priv->tx_irq, priv->err_irq, priv->can.clock.freq);
703 return 0;
704
705 exit_candev_free:
706 free_candev(dev);
707 exit_peri_pin_free:
708 peripheral_free_list(pdata);
709 exit:
710 return err;
711 }
712
bfin_can_remove(struct platform_device * pdev)713 static int bfin_can_remove(struct platform_device *pdev)
714 {
715 struct net_device *dev = platform_get_drvdata(pdev);
716 struct bfin_can_priv *priv = netdev_priv(dev);
717
718 bfin_can_set_reset_mode(dev);
719
720 unregister_candev(dev);
721
722 peripheral_free_list(priv->pin_list);
723
724 free_candev(dev);
725 return 0;
726 }
727
728 #ifdef CONFIG_PM
bfin_can_suspend(struct platform_device * pdev,pm_message_t mesg)729 static int bfin_can_suspend(struct platform_device *pdev, pm_message_t mesg)
730 {
731 struct net_device *dev = platform_get_drvdata(pdev);
732 struct bfin_can_priv *priv = netdev_priv(dev);
733 struct bfin_can_regs __iomem *reg = priv->membase;
734 int timeout = BFIN_CAN_TIMEOUT;
735
736 if (netif_running(dev)) {
737 /* enter sleep mode */
738 writew(readw(®->control) | SMR, ®->control);
739 while (!(readw(®->intr) & SMACK)) {
740 udelay(10);
741 if (--timeout == 0) {
742 netdev_err(dev, "fail to enter sleep mode\n");
743 BUG();
744 }
745 }
746 }
747
748 return 0;
749 }
750
bfin_can_resume(struct platform_device * pdev)751 static int bfin_can_resume(struct platform_device *pdev)
752 {
753 struct net_device *dev = platform_get_drvdata(pdev);
754 struct bfin_can_priv *priv = netdev_priv(dev);
755 struct bfin_can_regs __iomem *reg = priv->membase;
756
757 if (netif_running(dev)) {
758 /* leave sleep mode */
759 writew(0, ®->intr);
760 }
761
762 return 0;
763 }
764 #else
765 #define bfin_can_suspend NULL
766 #define bfin_can_resume NULL
767 #endif /* CONFIG_PM */
768
769 static struct platform_driver bfin_can_driver = {
770 .probe = bfin_can_probe,
771 .remove = bfin_can_remove,
772 .suspend = bfin_can_suspend,
773 .resume = bfin_can_resume,
774 .driver = {
775 .name = DRV_NAME,
776 },
777 };
778
779 module_platform_driver(bfin_can_driver);
780
781 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
782 MODULE_LICENSE("GPL");
783 MODULE_DESCRIPTION("Blackfin on-chip CAN netdevice driver");
784 MODULE_ALIAS("platform:" DRV_NAME);
785