| /arch/m68k/lib/ |
| D | divsi3.S | 117 jpl L3
120 L3: movel sp@+, d2 label
|
| D | udivsi3.S | 95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
|
| /arch/x86/events/intel/ |
| D | ds.c | 62 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
66 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
70 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
73 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
83 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
84 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
[all …]
|
| /arch/blackfin/kernel/cplb-nompu/ |
| D | Makefile | 9 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
|
| /arch/blackfin/kernel/cplb-mpu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
|
| /arch/arm/boot/dts/ |
| D | gemini-wbd222.dts | 46 label = "wbd111:red:L3";
64 label = "wbd111:green:L3";
|
| D | gemini-wbd111.dts | 46 label = "wbd111:red:L3";
64 label = "wbd111:green:L3";
|
| D | omap4.dtsi | 595 <0x49032000 0x7f>; /* L3 Interconnect */
608 <0x4902e000 0x7f>; /* L3 Interconnect */
620 <0x49022000 0xff>; /* L3 Interconnect */
635 <0x49024000 0xff>; /* L3 Interconnect */
650 <0x49026000 0xff>; /* L3 Interconnect */
|
| D | omap5.dtsi | 646 <0x49032000 0x7f>; /* L3 Interconnect */
659 <0x4902e000 0x7f>; /* L3 Interconnect */
671 <0x49022000 0xff>; /* L3 Interconnect */
686 <0x49024000 0xff>; /* L3 Interconnect */
701 <0x49026000 0xff>; /* L3 Interconnect */
|
| D | omap3-n900.dts | 16 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
21 * There is "unofficial" version of bootloader which enables AES in L3 firewall
23 * There is also no runtime detection code if AES is disabled in L3 firewall...
|
| /arch/metag/tbx/ |
| D | tbidspram.S | 111 $L3:
118 BR $L3
|
| /arch/alpha/kernel/ |
| D | setup.c | 1357 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1368 L3 = -1; in determine_cpu_caches()
1389 L3 = -1; in determine_cpu_caches()
1420 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1434 L3 = -1; in determine_cpu_caches()
1457 L3 = -1; in determine_cpu_caches()
1464 L3 = -1; in determine_cpu_caches()
1469 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1476 alpha_l3_cacheshape = L3; in determine_cpu_caches()
|
| /arch/metag/lib/ |
| D | div64.S | 14 BNE $L3
19 $L3:
|
| /arch/sparc/net/ |
| D | bpf_jit_64.h | 23 #define L3 0x13 macro
|
| D | bpf_jit_comp_64.c | 230 [BPF_REG_9] = L3,
|
| /arch/xtensa/lib/ |
| D | memset.S | 91 bbci.l a4, 2, .L3
95 .L3: label
|
| D | usercopy.S | 187 bbci.l a4, 2, .L3
193 .L3: label
|
| D | memcopy.S | 177 bbsi.l a4, 2, .L3
181 .L3: label
|
| /arch/hexagon/lib/ |
| D | memset.S | 177 if (p0.new) jump:nt .L3
189 .L3: label
|
| /arch/blackfin/mach-bf561/ |
| D | secondary.S | 50 L3 = r6; define
|
| /arch/arm/mach-omap2/ |
| D | sram243x.S | 100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
|
| D | sram242x.S | 100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
|
| /arch/blackfin/mach-common/ |
| D | head.S | 59 L3 = r6; define
|
| /arch/powerpc/perf/ |
| D | isa207-common.c | 176 ret = PH(LVL, L3); in isa207_find_source()
|
| /arch/sparc/lib/ |
| D | M7memcpy.S | 436 ! Gives existing cache lines time to be moved out of L1/L2/L3 cache.
|