1 /*
2 * Common Performance counter support functions for PowerISA v2.07 processors.
3 *
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
5 * Copyright 2013 Michael Ellerman, IBM Corporation.
6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13 #include "isa207-common.h"
14
15 PMU_FORMAT_ATTR(event, "config:0-49");
16 PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
17 PMU_FORMAT_ATTR(mark, "config:8");
18 PMU_FORMAT_ATTR(combine, "config:11");
19 PMU_FORMAT_ATTR(unit, "config:12-15");
20 PMU_FORMAT_ATTR(pmc, "config:16-19");
21 PMU_FORMAT_ATTR(cache_sel, "config:20-23");
22 PMU_FORMAT_ATTR(sample_mode, "config:24-28");
23 PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
24 PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
25 PMU_FORMAT_ATTR(thresh_start, "config:36-39");
26 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
27
28 struct attribute *isa207_pmu_format_attr[] = {
29 &format_attr_event.attr,
30 &format_attr_pmcxsel.attr,
31 &format_attr_mark.attr,
32 &format_attr_combine.attr,
33 &format_attr_unit.attr,
34 &format_attr_pmc.attr,
35 &format_attr_cache_sel.attr,
36 &format_attr_sample_mode.attr,
37 &format_attr_thresh_sel.attr,
38 &format_attr_thresh_stop.attr,
39 &format_attr_thresh_start.attr,
40 &format_attr_thresh_cmp.attr,
41 NULL,
42 };
43
44 struct attribute_group isa207_pmu_format_group = {
45 .name = "format",
46 .attrs = isa207_pmu_format_attr,
47 };
48
event_is_fab_match(u64 event)49 static inline bool event_is_fab_match(u64 event)
50 {
51 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
52 event &= 0xff0fe;
53
54 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
55 return (event == 0x30056 || event == 0x4f052);
56 }
57
is_event_valid(u64 event)58 static bool is_event_valid(u64 event)
59 {
60 u64 valid_mask = EVENT_VALID_MASK;
61
62 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
63 valid_mask = p9_EVENT_VALID_MASK;
64
65 return !(event & ~valid_mask);
66 }
67
is_event_marked(u64 event)68 static inline bool is_event_marked(u64 event)
69 {
70 if (event & EVENT_IS_MARKED)
71 return true;
72
73 return false;
74 }
75
mmcra_sdar_mode(u64 event,unsigned long * mmcra)76 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
77 {
78 /*
79 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in
80 * continous sampling mode.
81 *
82 * Incase of Power8:
83 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling
84 * mode and will be un-changed when setting MMCRA[63] (Marked events).
85 *
86 * Incase of Power9:
87 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
88 * or if group already have any marked events.
89 * Non-Marked events (for DD1):
90 * MMCRA[SDAR_MODE] will be set to 0b01
91 * For rest
92 * MMCRA[SDAR_MODE] will be set from event code.
93 * If sdar_mode from event is zero, default to 0b01. Hardware
94 * requires that we set a non-zero value.
95 */
96 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
97 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
98 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
99 else if (!cpu_has_feature(CPU_FTR_POWER9_DD1) && p9_SDAR_MODE(event))
100 *mmcra |= p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
101 else
102 *mmcra |= MMCRA_SDAR_MODE_DCACHE;
103 } else
104 *mmcra |= MMCRA_SDAR_MODE_TLB;
105 }
106
thresh_cmp_val(u64 value)107 static u64 thresh_cmp_val(u64 value)
108 {
109 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
110 return value << p9_MMCRA_THR_CMP_SHIFT;
111
112 return value << MMCRA_THR_CMP_SHIFT;
113 }
114
combine_from_event(u64 event)115 static unsigned long combine_from_event(u64 event)
116 {
117 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
118 return p9_EVENT_COMBINE(event);
119
120 return EVENT_COMBINE(event);
121 }
122
combine_shift(unsigned long pmc)123 static unsigned long combine_shift(unsigned long pmc)
124 {
125 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1))
126 return p9_MMCR1_COMBINE_SHIFT(pmc);
127
128 return MMCR1_COMBINE_SHIFT(pmc);
129 }
130
event_is_threshold(u64 event)131 static inline bool event_is_threshold(u64 event)
132 {
133 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
134 }
135
is_thresh_cmp_valid(u64 event)136 static bool is_thresh_cmp_valid(u64 event)
137 {
138 unsigned int cmp, exp;
139
140 /*
141 * Check the mantissa upper two bits are not zero, unless the
142 * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
143 */
144 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
145 exp = cmp >> 7;
146
147 if (exp && (cmp & 0x60) == 0)
148 return false;
149
150 return true;
151 }
152
dc_ic_rld_quad_l1_sel(u64 event)153 static unsigned int dc_ic_rld_quad_l1_sel(u64 event)
154 {
155 unsigned int cache;
156
157 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
158 return cache;
159 }
160
isa207_find_source(u64 idx,u32 sub_idx)161 static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
162 {
163 u64 ret = PERF_MEM_NA;
164
165 switch(idx) {
166 case 0:
167 /* Nothing to do */
168 break;
169 case 1:
170 ret = PH(LVL, L1);
171 break;
172 case 2:
173 ret = PH(LVL, L2);
174 break;
175 case 3:
176 ret = PH(LVL, L3);
177 break;
178 case 4:
179 if (sub_idx <= 1)
180 ret = PH(LVL, LOC_RAM);
181 else if (sub_idx > 1 && sub_idx <= 2)
182 ret = PH(LVL, REM_RAM1);
183 else
184 ret = PH(LVL, REM_RAM2);
185 ret |= P(SNOOP, HIT);
186 break;
187 case 5:
188 ret = PH(LVL, REM_CCE1);
189 if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4))
190 ret |= P(SNOOP, HIT);
191 else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5))
192 ret |= P(SNOOP, HITM);
193 break;
194 case 6:
195 ret = PH(LVL, REM_CCE2);
196 if ((sub_idx == 0) || (sub_idx == 2))
197 ret |= P(SNOOP, HIT);
198 else if ((sub_idx == 1) || (sub_idx == 3))
199 ret |= P(SNOOP, HITM);
200 break;
201 case 7:
202 ret = PM(LVL, L1);
203 break;
204 }
205
206 return ret;
207 }
208
isa207_get_mem_data_src(union perf_mem_data_src * dsrc,u32 flags,struct pt_regs * regs)209 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
210 struct pt_regs *regs)
211 {
212 u64 idx;
213 u32 sub_idx;
214 u64 sier;
215 u64 val;
216
217 /* Skip if no SIER support */
218 if (!(flags & PPMU_HAS_SIER)) {
219 dsrc->val = 0;
220 return;
221 }
222
223 sier = mfspr(SPRN_SIER);
224 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
225 if (val == 1 || val == 2) {
226 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
227 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
228
229 dsrc->val = isa207_find_source(idx, sub_idx);
230 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
231 }
232 }
233
isa207_get_mem_weight(u64 * weight)234 void isa207_get_mem_weight(u64 *weight)
235 {
236 u64 mmcra = mfspr(SPRN_MMCRA);
237 u64 exp = MMCRA_THR_CTR_EXP(mmcra);
238 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra);
239 u64 sier = mfspr(SPRN_SIER);
240 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
241
242 if (val == 0 || val == 7)
243 *weight = 0;
244 else
245 *weight = mantissa << (2 * exp);
246 }
247
isa207_get_constraint(u64 event,unsigned long * maskp,unsigned long * valp)248 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
249 {
250 unsigned int unit, pmc, cache, ebb;
251 unsigned long mask, value;
252
253 mask = value = 0;
254
255 if (!is_event_valid(event))
256 return -1;
257
258 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
259 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
260 cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
261 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
262
263 if (pmc) {
264 u64 base_event;
265
266 if (pmc > 6)
267 return -1;
268
269 /* Ignore Linux defined bits when checking event below */
270 base_event = event & ~EVENT_LINUX_MASK;
271
272 if (pmc >= 5 && base_event != 0x500fa &&
273 base_event != 0x600f4)
274 return -1;
275
276 mask |= CNST_PMC_MASK(pmc);
277 value |= CNST_PMC_VAL(pmc);
278 }
279
280 if (pmc <= 4) {
281 /*
282 * Add to number of counters in use. Note this includes events with
283 * a PMC of 0 - they still need a PMC, it's just assigned later.
284 * Don't count events on PMC 5 & 6, there is only one valid event
285 * on each of those counters, and they are handled above.
286 */
287 mask |= CNST_NC_MASK;
288 value |= CNST_NC_VAL;
289 }
290
291 if (unit >= 6 && unit <= 9) {
292 /*
293 * L2/L3 events contain a cache selector field, which is
294 * supposed to be programmed into MMCRC. However MMCRC is only
295 * HV writable, and there is no API for guest kernels to modify
296 * it. The solution is for the hypervisor to initialise the
297 * field to zeroes, and for us to only ever allow events that
298 * have a cache selector of zero. The bank selector (bit 3) is
299 * irrelevant, as long as the rest of the value is 0.
300 */
301 if (!cpu_has_feature(CPU_FTR_ARCH_300) && (cache & 0x7))
302 return -1;
303
304 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) {
305 mask |= CNST_L1_QUAL_MASK;
306 value |= CNST_L1_QUAL_VAL(cache);
307 }
308
309 if (is_event_marked(event)) {
310 mask |= CNST_SAMPLE_MASK;
311 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
312 }
313
314 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
315 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
316 mask |= CNST_THRESH_MASK;
317 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
318 }
319 } else {
320 /*
321 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
322 * the threshold control bits are used for the match value.
323 */
324 if (event_is_fab_match(event)) {
325 mask |= CNST_FAB_MATCH_MASK;
326 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
327 } else {
328 if (!is_thresh_cmp_valid(event))
329 return -1;
330
331 mask |= CNST_THRESH_MASK;
332 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
333 }
334 }
335
336 if (!pmc && ebb)
337 /* EBB events must specify the PMC */
338 return -1;
339
340 if (event & EVENT_WANTS_BHRB) {
341 if (!ebb)
342 /* Only EBB events can request BHRB */
343 return -1;
344
345 mask |= CNST_IFM_MASK;
346 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
347 }
348
349 /*
350 * All events must agree on EBB, either all request it or none.
351 * EBB events are pinned & exclusive, so this should never actually
352 * hit, but we leave it as a fallback in case.
353 */
354 mask |= CNST_EBB_VAL(ebb);
355 value |= CNST_EBB_MASK;
356
357 *maskp = mask;
358 *valp = value;
359
360 return 0;
361 }
362
isa207_compute_mmcr(u64 event[],int n_ev,unsigned int hwc[],unsigned long mmcr[],struct perf_event * pevents[])363 int isa207_compute_mmcr(u64 event[], int n_ev,
364 unsigned int hwc[], unsigned long mmcr[],
365 struct perf_event *pevents[])
366 {
367 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
368 unsigned int pmc, pmc_inuse;
369 int i;
370
371 pmc_inuse = 0;
372
373 /* First pass to count resource use */
374 for (i = 0; i < n_ev; ++i) {
375 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
376 if (pmc)
377 pmc_inuse |= 1 << pmc;
378 }
379
380 mmcra = mmcr1 = mmcr2 = 0;
381
382 /* Second pass: assign PMCs, set all MMCR1 fields */
383 for (i = 0; i < n_ev; ++i) {
384 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
385 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
386 combine = combine_from_event(event[i]);
387 psel = event[i] & EVENT_PSEL_MASK;
388
389 if (!pmc) {
390 for (pmc = 1; pmc <= 4; ++pmc) {
391 if (!(pmc_inuse & (1 << pmc)))
392 break;
393 }
394
395 pmc_inuse |= 1 << pmc;
396 }
397
398 if (pmc <= 4) {
399 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
400 mmcr1 |= combine << combine_shift(pmc);
401 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
402 }
403
404 /* In continuous sampling mode, update SDAR on TLB miss */
405 mmcra_sdar_mode(event[i], &mmcra);
406
407 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
408 cache = dc_ic_rld_quad_l1_sel(event[i]);
409 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
410 } else {
411 if (event[i] & EVENT_IS_L1) {
412 cache = dc_ic_rld_quad_l1_sel(event[i]);
413 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
414 }
415 }
416
417 if (is_event_marked(event[i])) {
418 mmcra |= MMCRA_SAMPLE_ENABLE;
419
420 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
421 if (val) {
422 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
423 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
424 }
425 }
426
427 /*
428 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
429 * the threshold bits are used for the match value.
430 */
431 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
432 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
433 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
434 } else {
435 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
436 mmcra |= val << MMCRA_THR_CTL_SHIFT;
437 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
438 mmcra |= val << MMCRA_THR_SEL_SHIFT;
439 val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
440 mmcra |= thresh_cmp_val(val);
441 }
442
443 if (event[i] & EVENT_WANTS_BHRB) {
444 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
445 mmcra |= val << MMCRA_IFM_SHIFT;
446 }
447
448 if (pevents[i]->attr.exclude_user)
449 mmcr2 |= MMCR2_FCP(pmc);
450
451 if (pevents[i]->attr.exclude_hv)
452 mmcr2 |= MMCR2_FCH(pmc);
453
454 if (pevents[i]->attr.exclude_kernel) {
455 if (cpu_has_feature(CPU_FTR_HVMODE))
456 mmcr2 |= MMCR2_FCH(pmc);
457 else
458 mmcr2 |= MMCR2_FCS(pmc);
459 }
460
461 hwc[i] = pmc - 1;
462 }
463
464 /* Return MMCRx values */
465 mmcr[0] = 0;
466
467 /* pmc_inuse is 1-based */
468 if (pmc_inuse & 2)
469 mmcr[0] = MMCR0_PMC1CE;
470
471 if (pmc_inuse & 0x7c)
472 mmcr[0] |= MMCR0_PMCjCE;
473
474 /* If we're not using PMC 5 or 6, freeze them */
475 if (!(pmc_inuse & 0x60))
476 mmcr[0] |= MMCR0_FC56;
477
478 mmcr[1] = mmcr1;
479 mmcr[2] = mmcra;
480 mmcr[3] = mmcr2;
481
482 return 0;
483 }
484
isa207_disable_pmc(unsigned int pmc,unsigned long mmcr[])485 void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[])
486 {
487 if (pmc <= 3)
488 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
489 }
490
find_alternative(u64 event,const unsigned int ev_alt[][MAX_ALT],int size)491 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
492 {
493 int i, j;
494
495 for (i = 0; i < size; ++i) {
496 if (event < ev_alt[i][0])
497 break;
498
499 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j)
500 if (event == ev_alt[i][j])
501 return i;
502 }
503
504 return -1;
505 }
506
isa207_get_alternatives(u64 event,u64 alt[],int size,unsigned int flags,const unsigned int ev_alt[][MAX_ALT])507 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
508 const unsigned int ev_alt[][MAX_ALT])
509 {
510 int i, j, num_alt = 0;
511 u64 alt_event;
512
513 alt[num_alt++] = event;
514 i = find_alternative(event, ev_alt, size);
515 if (i >= 0) {
516 /* Filter out the original event, it's already in alt[0] */
517 for (j = 0; j < MAX_ALT; ++j) {
518 alt_event = ev_alt[i][j];
519 if (alt_event && alt_event != event)
520 alt[num_alt++] = alt_event;
521 }
522 }
523
524 if (flags & PPMU_ONLY_COUNT_RUN) {
525 /*
526 * We're only counting in RUN state, so PM_CYC is equivalent to
527 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
528 */
529 j = num_alt;
530 for (i = 0; i < num_alt; ++i) {
531 switch (alt[i]) {
532 case 0x1e: /* PMC_CYC */
533 alt[j++] = 0x600f4; /* PM_RUN_CYC */
534 break;
535 case 0x600f4:
536 alt[j++] = 0x1e;
537 break;
538 case 0x2: /* PM_INST_CMPL */
539 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
540 break;
541 case 0x500fa:
542 alt[j++] = 0x2;
543 break;
544 }
545 }
546 num_alt = j;
547 }
548
549 return num_alt;
550 }
551