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Searched refs:M32R_ICUCR_IEN (Results 1 – 10 of 10) sorted by relevance

/arch/m32r/platforms/m32104ut/
Dsetup.c38 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; in enable_m32104ut_irq()
82 cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; in init_IRQ()
89 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; in init_IRQ()
96 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; in init_IRQ()
102 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; in init_IRQ()
/arch/m32r/platforms/mappi2/
Dsetup.c45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; in enable_mappi2_irq()
81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; in init_IRQ()
88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; in init_IRQ()
127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; in init_IRQ()
134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; in init_IRQ()
140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; in init_IRQ()
/arch/m32r/platforms/mappi3/
Dsetup.c45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; in enable_mappi3_irq()
80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; in init_IRQ()
87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; in init_IRQ()
126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; in init_IRQ()
133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; in init_IRQ()
141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; in init_IRQ()
/arch/m32r/platforms/mappi/
Dsetup.c37 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; in enable_mappi_irq()
80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; in init_IRQ()
87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; in init_IRQ()
120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; in init_IRQ()
126 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; in init_IRQ()
/arch/m32r/platforms/oaks32r/
Dsetup.c36 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; in enable_oaks32r_irq()
79 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; in init_IRQ()
86 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; in init_IRQ()
/arch/m32r/platforms/opsput/
Dsetup.c44 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; in enable_opsput_irq()
270 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; in init_IRQ()
339 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; in init_IRQ()
346 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; in init_IRQ()
360 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; in init_IRQ()
369 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; in init_IRQ()
/arch/m32r/platforms/m32700ut/
Dsetup.c43 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; in enable_m32700ut_irq()
272 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; in init_IRQ()
341 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; in init_IRQ()
348 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; in init_IRQ()
363 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; in init_IRQ()
372 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; in init_IRQ()
/arch/m32r/platforms/usrv/
Dsetup.c36 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6; in enable_mappi_irq()
143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; in init_IRQ()
/arch/m32r/include/asm/
Dm32r_mp_fpga.h260 #define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */ macro
Dm32102.h224 #define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */ macro