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Searched refs:MSR_P6_EVNTSEL0 (Results 1 – 7 of 7) sorted by relevance

/arch/x86/events/intel/
Dp6.c143 rdmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all()
145 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_disable_all()
153 rdmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
155 wrmsrl(MSR_P6_EVNTSEL0, val); in p6_pmu_enable_all()
210 .eventsel = MSR_P6_EVNTSEL0,
/arch/x86/oprofile/
Dop_model_ppro.c41 release_evntsel_nmi(MSR_P6_EVNTSEL0 + i); in ppro_shutdown()
52 if (!reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) { in ppro_fill_in_addresses()
58 msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i; in ppro_fill_in_addresses()
/arch/x86/kvm/
Dpmu_intel.c111 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx, in intel_pmc_idx_to_pmc()
112 MSR_P6_EVNTSEL0); in intel_pmc_idx_to_pmc()
167 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) || in intel_is_valid_msr()
198 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { in intel_pmu_get_msr()
255 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) { in intel_pmu_set_msr()
Dx86.c2444 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: in kvm_set_msr_common()
2595 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1: in kvm_get_msr_common()
/arch/x86/kernel/cpu/
Dperfctr-watchdog.c87 return msr - MSR_P6_EVNTSEL0; in nmi_evntsel_msr_to_bit()
/arch/x86/xen/
Dpmu.c163 if ((msr_index >= MSR_P6_EVNTSEL0) && in is_intel_pmu_msr()
164 (msr_index < MSR_P6_EVNTSEL0 + intel_num_arch_counters)) { in is_intel_pmu_msr()
165 *index = msr_index - MSR_P6_EVNTSEL0; in is_intel_pmu_msr()
/arch/x86/include/asm/
Dmsr-index.h336 #define MSR_P6_EVNTSEL0 0x00000186 macro