| /arch/arm/kvm/ |
| D | coproc.c | 315 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
319 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
323 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
327 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
332 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
334 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
336 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
342 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
346 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
348 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
[all …]
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| D | coproc.h | 26 unsigned long Op2; member
38 unsigned long Op2; member
66 p->CRn, p->CRm, p->Op1, p->Op2, in print_cp_instr()
124 if (i1->Op2 != i2->Op2) in cmp_reg()
125 return i1->Op2 - i2->Op2; in cmp_reg()
134 #define Op2(_x) .Op2 = _x macro
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| D | trace.h | 13 unsigned long CRm, unsigned long Op2, bool is_write),
14 TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
21 __field( unsigned int, Op2 )
31 __entry->Op2 = Op2;
37 __entry->CRm, __entry->Op2)
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| D | coproc_a15.c | 36 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
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| D | coproc_a7.c | 39 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
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| /arch/arm64/kvm/ |
| D | sys_regs.h | 30 u8 Op2; member
43 u8 Op2; member
70 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_instr()
118 return i1->Op2 - i2->Op2; in cmp_sys_reg()
130 #define Op2(_x) .Op2 = _x macro
135 Op2(sys_reg_Op2(reg))
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| D | sys_regs.c | 574 if (!(p->Op2 & 1)) in access_pmceid()
608 if (r->Op2 == 2) { in access_pmu_evcntr()
615 } else if (r->Op2 == 0) { in access_pmu_evcntr()
635 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); in access_pmu_evcntr()
666 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { in access_pmu_evtyper()
671 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); in access_pmu_evtyper()
708 if (r->Op2 & 0x1) { in access_pmcnten()
740 if (r->Op2 & 0x1) in access_pminten()
1154 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1156 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
[all …]
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| D | sys_regs_generic_v8.c | 60 { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
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| D | vgic-sys-reg-v3.c | 211 u8 idx = r->Op2 & 3; in access_gic_aprn()
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| /arch/arm/include/asm/ |
| D | cp15.h | 53 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument
54 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
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