/arch/mips/include/asm/ |
D | irqflags.h | 155 LONG_L $5, PT_R5(sp); \ 162 LONG_L $5, PT_R5(sp); \
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D | stackframe.h | 259 cfi_st $5, PT_R5, \docfi 374 cfi_ld $5, PT_R5, \docfi 418 cfi_ld $5, PT_R5, \docfi
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/arch/cris/include/uapi/asm/ |
D | ptrace_v10.h | 23 #define PT_R5 10 macro
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D | ptrace_v32.h | 13 #define PT_R5 6 macro
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/arch/m32r/include/uapi/asm/ |
D | ptrace.h | 18 #define PT_R5 1 macro
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/arch/nios2/include/asm/ |
D | entry.h | 42 stw r5, PT_R5(sp) 69 ldw r5, PT_R5(sp)
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/arch/mips/kernel/ |
D | mcount.S | 27 PTR_S a1, PT_R5(sp) 42 PTR_L a1, PT_R5(sp)
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D | scall64-n32.S | 83 ld a1, PT_R5(sp)
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D | scall64-64.S | 94 ld a1, PT_R5(sp)
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D | asm-offsets.c | 34 OFFSET(PT_R5, pt_regs, regs[5]); in output_ptreg_defines()
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/arch/blackfin/include/uapi/asm/ |
D | ptrace.h | 113 #define PT_R5 184 macro
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/arch/mips/alchemy/common/ |
D | sleeper.S | 33 sw $5, PT_R5(sp) 252 lw $5, PT_R5(sp)
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/arch/score/include/asm/ |
D | asmmacro.h | 29 sw r5, [r0, PT_R5] 126 lw r5, [r0, PT_R5]
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/arch/powerpc/include/uapi/asm/ |
D | ptrace.h | 68 #define PT_R5 5 macro
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/arch/nios2/kernel/ |
D | asm-offsets.c | 46 OFFSET(PT_R5, pt_regs, r5); in main()
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D | entry.S | 185 ldw r5, PT_R5(sp) 254 ldw r5, PT_R5(sp) 312 ldw r5, PT_R5(sp)
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D | insnemu.S | 37 ldw r5, PT_R5(sp)
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/arch/ia64/include/uapi/asm/ |
D | ptrace_offsets.h | 203 #define PT_R5 0x07b8 macro
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/arch/microblaze/kernel/ |
D | entry-nommu.S | 72 swi r5, r1, PT_R5 191 lwi r5, r1, PT_R5 222 swi r5, r1, PT_R5 315 swi r5, r1, PT_R5 566 lwi r5, r1, PT_R5
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D | asm-offsets.c | 35 DEFINE(PT_R5, offsetof(struct pt_regs, r5)); in main()
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D | hw_exception_handler.S | 93 lwi r5, r1, PT_R5; \ 339 swi r5, r1, PT_R5 570 lwi r5, r1, PT_R5
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D | entry.S | 181 swi r5, r1, PT_R5; \ 215 lwi r5, r1, PT_R5; \ 349 lwi r5, r1, PT_R5;
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/arch/score/kernel/ |
D | asm-offsets.c | 41 OFFSET(PT_R5, pt_regs, regs[5]); in output_ptreg_defines()
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/arch/blackfin/kernel/ |
D | asm-offsets.c | 60 DEFINE(PT_R5, offsetof(struct pt_regs, r5)); in main()
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/arch/m32r/kernel/ |
D | ptrace.c | 65 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
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