1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * linux/include/asm-m32r/ptrace.h 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 * 9 * M32R version: 10 * Copyright (C) 2001-2002, 2004 Hirokazu Takata <takata at linux-m32r.org> 11 */ 12 #ifndef _UAPI_ASM_M32R_PTRACE_H 13 #define _UAPI_ASM_M32R_PTRACE_H 14 15 16 /* 0 - 13 are integer registers (general purpose registers). */ 17 #define PT_R4 0 18 #define PT_R5 1 19 #define PT_R6 2 20 #define PT_REGS 3 21 #define PT_R0 4 22 #define PT_R1 5 23 #define PT_R2 6 24 #define PT_R3 7 25 #define PT_R7 8 26 #define PT_R8 9 27 #define PT_R9 10 28 #define PT_R10 11 29 #define PT_R11 12 30 #define PT_R12 13 31 #define PT_SYSCNR 14 32 #define PT_R13 PT_FP 33 #define PT_R14 PT_LR 34 #define PT_R15 PT_SP 35 36 /* processor status and miscellaneous context registers. */ 37 #define PT_ACC0H 15 38 #define PT_ACC0L 16 39 #define PT_ACC1H 17 /* ISA_DSP_LEVEL2 only */ 40 #define PT_ACC1L 18 /* ISA_DSP_LEVEL2 only */ 41 #define PT_PSW 19 42 #define PT_BPC 20 43 #define PT_BBPSW 21 44 #define PT_BBPC 22 45 #define PT_SPU 23 46 #define PT_FP 24 47 #define PT_LR 25 48 #define PT_SPI 26 49 #define PT_ORIGR0 27 50 51 /* virtual pt_reg entry for gdb */ 52 #define PT_PC 30 53 #define PT_CBR 31 54 #define PT_EVB 32 55 56 57 /* Control registers. */ 58 #define SPR_CR0 PT_PSW 59 #define SPR_CR1 PT_CBR /* read only */ 60 #define SPR_CR2 PT_SPI 61 #define SPR_CR3 PT_SPU 62 #define SPR_CR4 63 #define SPR_CR5 PT_EVB /* part of M32R/E, M32R/I core only */ 64 #define SPR_CR6 PT_BPC 65 #define SPR_CR7 66 #define SPR_CR8 PT_BBPSW 67 #define SPR_CR9 68 #define SPR_CR10 69 #define SPR_CR11 70 #define SPR_CR12 71 #define SPR_CR13 PT_WR 72 #define SPR_CR14 PT_BBPC 73 #define SPR_CR15 74 75 /* this struct defines the way the registers are stored on the 76 stack during a system call. */ 77 struct pt_regs { 78 /* Saved main processor registers. */ 79 unsigned long r4; 80 unsigned long r5; 81 unsigned long r6; 82 struct pt_regs *pt_regs; 83 unsigned long r0; 84 unsigned long r1; 85 unsigned long r2; 86 unsigned long r3; 87 unsigned long r7; 88 unsigned long r8; 89 unsigned long r9; 90 unsigned long r10; 91 unsigned long r11; 92 unsigned long r12; 93 long syscall_nr; 94 95 /* Saved main processor status and miscellaneous context registers. */ 96 unsigned long acc0h; 97 unsigned long acc0l; 98 unsigned long acc1h; /* ISA_DSP_LEVEL2 only */ 99 unsigned long acc1l; /* ISA_DSP_LEVEL2 only */ 100 unsigned long psw; 101 unsigned long bpc; /* saved PC for TRAP syscalls */ 102 unsigned long bbpsw; 103 unsigned long bbpc; 104 unsigned long spu; /* saved user stack */ 105 unsigned long fp; 106 unsigned long lr; /* saved PC for JL syscalls */ 107 unsigned long spi; /* saved kernel stack */ 108 unsigned long orig_r0; 109 }; 110 111 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ 112 #define PTRACE_GETREGS 12 113 #define PTRACE_SETREGS 13 114 115 #define PTRACE_OLDSETOPTIONS 21 116 117 118 #endif /* _UAPI_ASM_M32R_PTRACE_H */ 119