| /arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 81 mfspr r0,SPRN_HID0
95 mfspr r0,SPRN_HID0
102 mtspr SPRN_HID0,r0
103 mfspr r0,SPRN_HID0
104 mfspr r0,SPRN_HID0
105 mfspr r0,SPRN_HID0
106 mfspr r0,SPRN_HID0
107 mfspr r0,SPRN_HID0
108 mfspr r0,SPRN_HID0
124 mfspr r3,SPRN_HID0
[all …]
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| D | l2cr_6xx.S | 127 mfspr r8,SPRN_HID0 /* Save HID0 in r8 */
130 mtspr SPRN_HID0,r4 /* Disable DPM */
444 mfspr r3,SPRN_HID0
446 mtspr SPRN_HID0,r3
459 mfspr r3,SPRN_HID0
463 mtspr SPRN_HID0,r3
465 mtspr SPRN_HID0,r3
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| D | cpu_setup_6xx.S | 88 mfspr r11,SPRN_HID0
95 mtspr SPRN_HID0,r8 /* enable and invalidate caches */
97 mtspr SPRN_HID0,r11 /* enable caches */
106 mfspr r11,SPRN_HID0
110 mtspr SPRN_HID0,r8 /* flush branch target address cache */
112 mtspr SPRN_HID0,r11
165 mfspr r11,SPRN_HID0
179 mtspr SPRN_HID0,r11
235 mfspr r11,SPRN_HID0
260 mtspr SPRN_HID0,r11
[all …]
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| D | idle_6xx.S | 34 mfspr r4,SPRN_HID0
36 mtspr SPRN_HID0, r4
123 mfspr r4,SPRN_HID0
133 mtspr SPRN_HID0,r4
171 mfspr r9,SPRN_HID0
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| D | pmc.c | 86 hid0 = mfspr(SPRN_HID0); in power4_enable_pmcs()
99 "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0): in power4_enable_pmcs()
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| D | idle_e500.S | 63 mfspr r4,SPRN_HID0
67 mtspr SPRN_HID0,r4
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| D | cpu_setup_fsl_booke.S | 119 mfspr r3,SPRN_HID0
121 mtspr SPRN_HID0,r3
262 mfspr r8,SPRN_HID0
264 mtspr SPRN_HID0,r9
284 mtspr SPRN_HID0,r8
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| D | misc_32.S | 170 mfspr r5,SPRN_HID0
173 mtspr SPRN_HID0,r5
195 mfspr r5,SPRN_HID0
198 mtspr SPRN_HID0,r5
315 mfspr r3,SPRN_HID0
317 mtspr SPRN_HID0,r3
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| /arch/powerpc/sysdev/ |
| D | 6xx-suspend.S | 22 mfspr r5, SPRN_HID0
25 mtspr SPRN_HID0, r5
47 mfspr r5, SPRN_HID0
49 mtspr SPRN_HID0, r5
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| /arch/powerpc/platforms/powermac/ |
| D | cache.S | 60 mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
63 mtspr SPRN_HID0,r4 /* Disable DPM */
89 mfspr r3,SPRN_HID0
91 mtspr SPRN_HID0,r3
97 mtspr SPRN_HID0,r3
99 mtspr SPRN_HID0,r3
171 mfspr r0,SPRN_HID0
173 mtspr SPRN_HID0,r0
179 mfspr r0,SPRN_HID0
181 mtspr SPRN_HID0,r0
[all …]
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| D | sleep.S | 231 mfspr r2,SPRN_HID0
236 mtspr SPRN_HID0,r2
265 mfspr r3,SPRN_HID0
268 mtspr SPRN_HID0,r3
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| /arch/powerpc/platforms/powernv/ |
| D | subcore.c | 172 opal_slw_set_reg(cpu_pir, SPRN_HID0, hid0); in update_hid_in_slw()
185 while (mfspr(SPRN_HID0) & mask) in unsplit_core()
192 hid0 = mfspr(SPRN_HID0); in unsplit_core()
197 while (mfspr(SPRN_HID0) & mask) in unsplit_core()
229 hid0 = mfspr(SPRN_HID0); in split_core()
235 while (!(mfspr(SPRN_HID0) & split_parms[i].mask)) in split_core()
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| D | subcore-asm.S | 64 1: mfspr r4, SPRN_HID0
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| D | idle.c | 73 uint64_t hid0_val = mfspr(SPRN_HID0); in pnv_save_sprs_for_deep_states()
112 rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); in pnv_save_sprs_for_deep_states()
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| /arch/powerpc/platforms/86xx/ |
| D | common.c | 37 temp = mfspr(SPRN_HID0); in mpc86xx_time_init()
39 mtspr(SPRN_HID0, temp); in mpc86xx_time_init()
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| /arch/powerpc/platforms/52xx/ |
| D | mpc52xx_sleep.S | 38 mfspr r10, SPRN_HID0
41 mtspr SPRN_HID0, r10
54 mfspr r10, SPRN_HID0
58 mtspr SPRN_HID0, r10
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| D | lite5200_sleep.S | 94 mfspr r3, SPRN_HID0
98 mtspr SPRN_HID0, r3
227 mfspr r10, SPRN_HID0
229 mtspr SPRN_HID0, r5 /* invalidate caches */
231 mtspr SPRN_HID0, r10
236 mtspr SPRN_HID0, r10 /* restore (enable caches, DPM) */
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| D | mpc52xx_pm.c | 148 hid0 = mfspr(SPRN_HID0); in mpc52xx_pm_enter()
149 mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP); in mpc52xx_pm_enter()
165 mtspr(SPRN_HID0, hid0); in mpc52xx_pm_enter()
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| /arch/powerpc/platforms/85xx/ |
| D | mpc85xx_pm_ops.c | 38 tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP; in mpc85xx_cpu_die()
39 mtspr(SPRN_HID0, tmp); in mpc85xx_cpu_die()
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| /arch/powerpc/platforms/83xx/ |
| D | suspend-asm.S | 72 mfspr r5, SPRN_HID0
280 mfspr r3, SPRN_HID0
282 mtspr SPRN_HID0, r3
347 mfspr r5, SPRN_HID0
350 mtspr SPRN_HID0, r5
400 mtspr SPRN_HID0, r5
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| /arch/powerpc/platforms/cell/ |
| D | ras.c | 338 hid0 = mfspr(SPRN_HID0); in cbe_ras_init()
341 mtspr(SPRN_HID0, hid0); in cbe_ras_init()
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| /arch/powerpc/kvm/ |
| D | e500_emulate.c | 260 case SPRN_HID0: in kvmppc_core_emulate_mtspr_e500()
388 case SPRN_HID0: in kvmppc_core_emulate_mfspr_e500()
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| D | book3s_emulate.c | 399 case SPRN_HID0: in kvmppc_core_emulate_mtspr_pr()
557 case SPRN_HID0: in kvmppc_core_emulate_mfspr_pr()
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| /arch/powerpc/mm/ |
| D | pgtable-radix.c | 467 hid0 = mfspr(SPRN_HID0); in update_hid_for_radix()
469 mtspr(SPRN_HID0, hid0); in update_hid_for_radix()
473 while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX)) in update_hid_for_radix()
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| D | hash_utils_64.c | 828 hid0 = mfspr(SPRN_HID0); in update_hid_for_hash()
830 mtspr(SPRN_HID0, hid0); in update_hid_for_hash()
834 while ((mfspr(SPRN_HID0) & HID0_POWER9_RADIX)) in update_hid_for_hash()
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