1 /*
2 * Page table handling routines for radix page table.
3 *
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #define pr_fmt(fmt) "radix-mmu: " fmt
13
14 #include <linux/kernel.h>
15 #include <linux/sched/mm.h>
16 #include <linux/memblock.h>
17 #include <linux/of_fdt.h>
18 #include <linux/mm.h>
19 #include <linux/string_helpers.h>
20 #include <linux/stop_machine.h>
21
22 #include <asm/pgtable.h>
23 #include <asm/pgalloc.h>
24 #include <asm/dma.h>
25 #include <asm/machdep.h>
26 #include <asm/mmu.h>
27 #include <asm/firmware.h>
28 #include <asm/powernv.h>
29 #include <asm/sections.h>
30 #include <asm/trace.h>
31
32 #include <trace/events/thp.h>
33
34 unsigned int mmu_pid_bits;
35 unsigned int mmu_base_pid;
36
native_register_process_table(unsigned long base,unsigned long pg_sz,unsigned long table_size)37 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
38 unsigned long table_size)
39 {
40 unsigned long patb0, patb1;
41
42 patb0 = be64_to_cpu(partition_tb[0].patb0);
43 patb1 = base | table_size | PATB_GR;
44
45 mmu_partition_table_set_entry(0, patb0, patb1);
46
47 return 0;
48 }
49
early_alloc_pgtable(unsigned long size)50 static __ref void *early_alloc_pgtable(unsigned long size)
51 {
52 void *pt;
53
54 pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
55 memset(pt, 0, size);
56
57 return pt;
58 }
59
radix__map_kernel_page(unsigned long ea,unsigned long pa,pgprot_t flags,unsigned int map_page_size)60 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
61 pgprot_t flags,
62 unsigned int map_page_size)
63 {
64 pgd_t *pgdp;
65 pud_t *pudp;
66 pmd_t *pmdp;
67 pte_t *ptep;
68 /*
69 * Make sure task size is correct as per the max adddr
70 */
71 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
72 if (slab_is_available()) {
73 pgdp = pgd_offset_k(ea);
74 pudp = pud_alloc(&init_mm, pgdp, ea);
75 if (!pudp)
76 return -ENOMEM;
77 if (map_page_size == PUD_SIZE) {
78 ptep = (pte_t *)pudp;
79 goto set_the_pte;
80 }
81 pmdp = pmd_alloc(&init_mm, pudp, ea);
82 if (!pmdp)
83 return -ENOMEM;
84 if (map_page_size == PMD_SIZE) {
85 ptep = pmdp_ptep(pmdp);
86 goto set_the_pte;
87 }
88 ptep = pte_alloc_kernel(pmdp, ea);
89 if (!ptep)
90 return -ENOMEM;
91 } else {
92 pgdp = pgd_offset_k(ea);
93 if (pgd_none(*pgdp)) {
94 pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
95 BUG_ON(pudp == NULL);
96 pgd_populate(&init_mm, pgdp, pudp);
97 }
98 pudp = pud_offset(pgdp, ea);
99 if (map_page_size == PUD_SIZE) {
100 ptep = (pte_t *)pudp;
101 goto set_the_pte;
102 }
103 if (pud_none(*pudp)) {
104 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
105 BUG_ON(pmdp == NULL);
106 pud_populate(&init_mm, pudp, pmdp);
107 }
108 pmdp = pmd_offset(pudp, ea);
109 if (map_page_size == PMD_SIZE) {
110 ptep = pmdp_ptep(pmdp);
111 goto set_the_pte;
112 }
113 if (!pmd_present(*pmdp)) {
114 ptep = early_alloc_pgtable(PAGE_SIZE);
115 BUG_ON(ptep == NULL);
116 pmd_populate_kernel(&init_mm, pmdp, ptep);
117 }
118 ptep = pte_offset_kernel(pmdp, ea);
119 }
120
121 set_the_pte:
122 set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
123 smp_wmb();
124 return 0;
125 }
126
127 #ifdef CONFIG_STRICT_KERNEL_RWX
radix__change_memory_range(unsigned long start,unsigned long end,unsigned long clear)128 void radix__change_memory_range(unsigned long start, unsigned long end,
129 unsigned long clear)
130 {
131 unsigned long idx;
132 pgd_t *pgdp;
133 pud_t *pudp;
134 pmd_t *pmdp;
135 pte_t *ptep;
136
137 start = ALIGN_DOWN(start, PAGE_SIZE);
138 end = PAGE_ALIGN(end); // aligns up
139
140 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
141 start, end, clear);
142
143 for (idx = start; idx < end; idx += PAGE_SIZE) {
144 pgdp = pgd_offset_k(idx);
145 pudp = pud_alloc(&init_mm, pgdp, idx);
146 if (!pudp)
147 continue;
148 if (pud_huge(*pudp)) {
149 ptep = (pte_t *)pudp;
150 goto update_the_pte;
151 }
152 pmdp = pmd_alloc(&init_mm, pudp, idx);
153 if (!pmdp)
154 continue;
155 if (pmd_huge(*pmdp)) {
156 ptep = pmdp_ptep(pmdp);
157 goto update_the_pte;
158 }
159 ptep = pte_alloc_kernel(pmdp, idx);
160 if (!ptep)
161 continue;
162 update_the_pte:
163 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
164 }
165
166 radix__flush_tlb_kernel_range(start, end);
167 }
168
radix__mark_rodata_ro(void)169 void radix__mark_rodata_ro(void)
170 {
171 unsigned long start, end;
172
173 /*
174 * mark_rodata_ro() will mark itself as !writable at some point.
175 * Due to DD1 workaround in radix__pte_update(), we'll end up with
176 * an invalid pte and the system will crash quite severly.
177 */
178 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
179 pr_warn("Warning: Unable to mark rodata read only on P9 DD1\n");
180 return;
181 }
182
183 start = (unsigned long)_stext;
184 end = (unsigned long)__init_begin;
185
186 radix__change_memory_range(start, end, _PAGE_WRITE);
187 }
188
radix__mark_initmem_nx(void)189 void radix__mark_initmem_nx(void)
190 {
191 unsigned long start = (unsigned long)__init_begin;
192 unsigned long end = (unsigned long)__init_end;
193
194 radix__change_memory_range(start, end, _PAGE_EXEC);
195 }
196 #endif /* CONFIG_STRICT_KERNEL_RWX */
197
print_mapping(unsigned long start,unsigned long end,unsigned long size)198 static inline void __meminit print_mapping(unsigned long start,
199 unsigned long end,
200 unsigned long size)
201 {
202 char buf[10];
203
204 if (end <= start)
205 return;
206
207 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
208
209 pr_info("Mapped 0x%016lx-0x%016lx with %s pages\n", start, end, buf);
210 }
211
create_physical_mapping(unsigned long start,unsigned long end)212 static int __meminit create_physical_mapping(unsigned long start,
213 unsigned long end)
214 {
215 unsigned long vaddr, addr, mapping_size = 0;
216 pgprot_t prot;
217 unsigned long max_mapping_size;
218 #ifdef CONFIG_STRICT_KERNEL_RWX
219 int split_text_mapping = 1;
220 #else
221 int split_text_mapping = 0;
222 #endif
223
224 start = _ALIGN_UP(start, PAGE_SIZE);
225 for (addr = start; addr < end; addr += mapping_size) {
226 unsigned long gap, previous_size;
227 int rc;
228
229 gap = end - addr;
230 previous_size = mapping_size;
231 max_mapping_size = PUD_SIZE;
232
233 retry:
234 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
235 mmu_psize_defs[MMU_PAGE_1G].shift &&
236 PUD_SIZE <= max_mapping_size)
237 mapping_size = PUD_SIZE;
238 else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
239 mmu_psize_defs[MMU_PAGE_2M].shift)
240 mapping_size = PMD_SIZE;
241 else
242 mapping_size = PAGE_SIZE;
243
244 if (split_text_mapping && (mapping_size == PUD_SIZE) &&
245 (addr <= __pa_symbol(__init_begin)) &&
246 (addr + mapping_size) >= __pa_symbol(_stext)) {
247 max_mapping_size = PMD_SIZE;
248 goto retry;
249 }
250
251 if (split_text_mapping && (mapping_size == PMD_SIZE) &&
252 (addr <= __pa_symbol(__init_begin)) &&
253 (addr + mapping_size) >= __pa_symbol(_stext))
254 mapping_size = PAGE_SIZE;
255
256 if (mapping_size != previous_size) {
257 print_mapping(start, addr, previous_size);
258 start = addr;
259 }
260
261 vaddr = (unsigned long)__va(addr);
262
263 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
264 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size))
265 prot = PAGE_KERNEL_X;
266 else
267 prot = PAGE_KERNEL;
268
269 rc = radix__map_kernel_page(vaddr, addr, prot, mapping_size);
270 if (rc)
271 return rc;
272 }
273
274 print_mapping(start, addr, mapping_size);
275 return 0;
276 }
277
radix_init_pgtable(void)278 static void __init radix_init_pgtable(void)
279 {
280 unsigned long rts_field;
281 struct memblock_region *reg;
282
283 /* We don't support slb for radix */
284 mmu_slb_size = 0;
285 /*
286 * Create the linear mapping, using standard page size for now
287 */
288 for_each_memblock(memory, reg)
289 WARN_ON(create_physical_mapping(reg->base,
290 reg->base + reg->size));
291
292 /* Find out how many PID bits are supported */
293 if (cpu_has_feature(CPU_FTR_HVMODE)) {
294 if (!mmu_pid_bits)
295 mmu_pid_bits = 20;
296 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
297 /*
298 * When KVM is possible, we only use the top half of the
299 * PID space to avoid collisions between host and guest PIDs
300 * which can cause problems due to prefetch when exiting the
301 * guest with AIL=3
302 */
303 mmu_base_pid = 1 << (mmu_pid_bits - 1);
304 #else
305 mmu_base_pid = 1;
306 #endif
307 } else {
308 /* The guest uses the bottom half of the PID space */
309 if (!mmu_pid_bits)
310 mmu_pid_bits = 19;
311 mmu_base_pid = 1;
312 }
313
314 /*
315 * Allocate Partition table and process table for the
316 * host.
317 */
318 BUG_ON(PRTB_SIZE_SHIFT > 36);
319 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
320 /*
321 * Fill in the process table.
322 */
323 rts_field = radix__get_tree_size();
324 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
325 /*
326 * Fill in the partition table. We are suppose to use effective address
327 * of process table here. But our linear mapping also enable us to use
328 * physical address here.
329 */
330 register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
331 pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
332 asm volatile("ptesync" : : : "memory");
333 asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
334 "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
335 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
336 trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
337 }
338
radix_init_partition_table(void)339 static void __init radix_init_partition_table(void)
340 {
341 unsigned long rts_field, dw0;
342
343 mmu_partition_table_init();
344 rts_field = radix__get_tree_size();
345 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
346 mmu_partition_table_set_entry(0, dw0, 0);
347
348 pr_info("Initializing Radix MMU\n");
349 pr_info("Partition table %p\n", partition_tb);
350 }
351
radix_init_native(void)352 void __init radix_init_native(void)
353 {
354 register_process_table = native_register_process_table;
355 }
356
get_idx_from_shift(unsigned int shift)357 static int __init get_idx_from_shift(unsigned int shift)
358 {
359 int idx = -1;
360
361 switch (shift) {
362 case 0xc:
363 idx = MMU_PAGE_4K;
364 break;
365 case 0x10:
366 idx = MMU_PAGE_64K;
367 break;
368 case 0x15:
369 idx = MMU_PAGE_2M;
370 break;
371 case 0x1e:
372 idx = MMU_PAGE_1G;
373 break;
374 }
375 return idx;
376 }
377
radix_dt_scan_page_sizes(unsigned long node,const char * uname,int depth,void * data)378 static int __init radix_dt_scan_page_sizes(unsigned long node,
379 const char *uname, int depth,
380 void *data)
381 {
382 int size = 0;
383 int shift, idx;
384 unsigned int ap;
385 const __be32 *prop;
386 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
387
388 /* We are scanning "cpu" nodes only */
389 if (type == NULL || strcmp(type, "cpu") != 0)
390 return 0;
391
392 /* Find MMU PID size */
393 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
394 if (prop && size == 4)
395 mmu_pid_bits = be32_to_cpup(prop);
396
397 /* Grab page size encodings */
398 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
399 if (!prop)
400 return 0;
401
402 pr_info("Page sizes from device-tree:\n");
403 for (; size >= 4; size -= 4, ++prop) {
404
405 struct mmu_psize_def *def;
406
407 /* top 3 bit is AP encoding */
408 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
409 ap = be32_to_cpu(prop[0]) >> 29;
410 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
411
412 idx = get_idx_from_shift(shift);
413 if (idx < 0)
414 continue;
415
416 def = &mmu_psize_defs[idx];
417 def->shift = shift;
418 def->ap = ap;
419 }
420
421 /* needed ? */
422 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
423 return 1;
424 }
425
radix__early_init_devtree(void)426 void __init radix__early_init_devtree(void)
427 {
428 int rc;
429
430 /*
431 * Try to find the available page sizes in the device-tree
432 */
433 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
434 if (rc != 0) /* Found */
435 goto found;
436 /*
437 * let's assume we have page 4k and 64k support
438 */
439 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
440 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
441
442 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
443 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
444 found:
445 return;
446 }
447
update_hid_for_radix(void)448 static void update_hid_for_radix(void)
449 {
450 unsigned long hid0;
451 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
452
453 asm volatile("ptesync": : :"memory");
454 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
455 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
456 : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
457 /* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
458 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
459 : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
460 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
461 trace_tlbie(0, 0, rb, 0, 2, 0, 1);
462 trace_tlbie(0, 0, rb, 0, 2, 1, 1);
463
464 /*
465 * now switch the HID
466 */
467 hid0 = mfspr(SPRN_HID0);
468 hid0 |= HID0_POWER9_RADIX;
469 mtspr(SPRN_HID0, hid0);
470 asm volatile("isync": : :"memory");
471
472 /* Wait for it to happen */
473 while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
474 cpu_relax();
475 }
476
radix_init_amor(void)477 static void radix_init_amor(void)
478 {
479 /*
480 * In HV mode, we init AMOR (Authority Mask Override Register) so that
481 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
482 * Register), enable key 0 and set it to 1.
483 *
484 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
485 */
486 mtspr(SPRN_AMOR, (3ul << 62));
487 }
488
radix_init_iamr(void)489 static void radix_init_iamr(void)
490 {
491 unsigned long iamr;
492
493 /*
494 * The IAMR should set to 0 on DD1.
495 */
496 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
497 iamr = 0;
498 else
499 iamr = (1ul << 62);
500
501 /*
502 * Radix always uses key0 of the IAMR to determine if an access is
503 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
504 * fetch.
505 */
506 mtspr(SPRN_IAMR, iamr);
507 }
508
radix__early_init_mmu(void)509 void __init radix__early_init_mmu(void)
510 {
511 unsigned long lpcr;
512
513 #ifdef CONFIG_PPC_64K_PAGES
514 /* PAGE_SIZE mappings */
515 mmu_virtual_psize = MMU_PAGE_64K;
516 #else
517 mmu_virtual_psize = MMU_PAGE_4K;
518 #endif
519
520 #ifdef CONFIG_SPARSEMEM_VMEMMAP
521 /* vmemmap mapping */
522 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
523 /*
524 * map vmemmap using 2M if available
525 */
526 mmu_vmemmap_psize = MMU_PAGE_2M;
527 } else
528 mmu_vmemmap_psize = mmu_virtual_psize;
529 #endif
530 /*
531 * initialize page table size
532 */
533 __pte_index_size = RADIX_PTE_INDEX_SIZE;
534 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
535 __pud_index_size = RADIX_PUD_INDEX_SIZE;
536 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
537 __pmd_cache_index = RADIX_PMD_INDEX_SIZE;
538 __pte_table_size = RADIX_PTE_TABLE_SIZE;
539 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
540 __pud_table_size = RADIX_PUD_TABLE_SIZE;
541 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
542
543 __pmd_val_bits = RADIX_PMD_VAL_BITS;
544 __pud_val_bits = RADIX_PUD_VAL_BITS;
545 __pgd_val_bits = RADIX_PGD_VAL_BITS;
546
547 __kernel_virt_start = RADIX_KERN_VIRT_START;
548 __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
549 __vmalloc_start = RADIX_VMALLOC_START;
550 __vmalloc_end = RADIX_VMALLOC_END;
551 __kernel_io_start = RADIX_KERN_IO_START;
552 vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
553 ioremap_bot = IOREMAP_BASE;
554
555 #ifdef CONFIG_PCI
556 pci_io_base = ISA_IO_BASE;
557 #endif
558
559 /*
560 * For now radix also use the same frag size
561 */
562 __pte_frag_nr = H_PTE_FRAG_NR;
563 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
564
565 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
566 radix_init_native();
567 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
568 update_hid_for_radix();
569 lpcr = mfspr(SPRN_LPCR);
570 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
571 radix_init_partition_table();
572 radix_init_amor();
573 } else {
574 radix_init_pseries();
575 }
576
577 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
578
579 radix_init_iamr();
580 radix_init_pgtable();
581 }
582
radix__early_init_mmu_secondary(void)583 void radix__early_init_mmu_secondary(void)
584 {
585 unsigned long lpcr;
586 /*
587 * update partition table control register and UPRT
588 */
589 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
590
591 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
592 update_hid_for_radix();
593
594 lpcr = mfspr(SPRN_LPCR);
595 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
596
597 mtspr(SPRN_PTCR,
598 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
599 radix_init_amor();
600 }
601 radix_init_iamr();
602 }
603
radix__mmu_cleanup_all(void)604 void radix__mmu_cleanup_all(void)
605 {
606 unsigned long lpcr;
607
608 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
609 lpcr = mfspr(SPRN_LPCR);
610 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
611 mtspr(SPRN_PTCR, 0);
612 powernv_set_nmmu_ptcr(0);
613 radix__flush_tlb_all();
614 }
615 }
616
radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)617 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
618 phys_addr_t first_memblock_size)
619 {
620 /* We don't currently support the first MEMBLOCK not mapping 0
621 * physical on those processors
622 */
623 BUG_ON(first_memblock_base != 0);
624 /*
625 * We limit the allocation that depend on ppc64_rma_size
626 * to first_memblock_size. We also clamp it to 1GB to
627 * avoid some funky things such as RTAS bugs.
628 *
629 * On radix config we really don't have a limitation
630 * on real mode access. But keeping it as above works
631 * well enough.
632 */
633 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
634 /*
635 * Finally limit subsequent allocations. We really don't want
636 * to limit the memblock allocations to rma_size. FIXME!! should
637 * we even limit at all ?
638 */
639 memblock_set_current_limit(first_memblock_base + first_memblock_size);
640 }
641
642 #ifdef CONFIG_MEMORY_HOTPLUG
free_pte_table(pte_t * pte_start,pmd_t * pmd)643 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
644 {
645 pte_t *pte;
646 int i;
647
648 for (i = 0; i < PTRS_PER_PTE; i++) {
649 pte = pte_start + i;
650 if (!pte_none(*pte))
651 return;
652 }
653
654 pte_free_kernel(&init_mm, pte_start);
655 pmd_clear(pmd);
656 }
657
free_pmd_table(pmd_t * pmd_start,pud_t * pud)658 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
659 {
660 pmd_t *pmd;
661 int i;
662
663 for (i = 0; i < PTRS_PER_PMD; i++) {
664 pmd = pmd_start + i;
665 if (!pmd_none(*pmd))
666 return;
667 }
668
669 pmd_free(&init_mm, pmd_start);
670 pud_clear(pud);
671 }
672
673 struct change_mapping_params {
674 pte_t *pte;
675 unsigned long start;
676 unsigned long end;
677 unsigned long aligned_start;
678 unsigned long aligned_end;
679 };
680
stop_machine_change_mapping(void * data)681 static int stop_machine_change_mapping(void *data)
682 {
683 struct change_mapping_params *params =
684 (struct change_mapping_params *)data;
685
686 if (!data)
687 return -1;
688
689 spin_unlock(&init_mm.page_table_lock);
690 pte_clear(&init_mm, params->aligned_start, params->pte);
691 create_physical_mapping(params->aligned_start, params->start);
692 create_physical_mapping(params->end, params->aligned_end);
693 spin_lock(&init_mm.page_table_lock);
694 return 0;
695 }
696
remove_pte_table(pte_t * pte_start,unsigned long addr,unsigned long end)697 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
698 unsigned long end)
699 {
700 unsigned long next;
701 pte_t *pte;
702
703 pte = pte_start + pte_index(addr);
704 for (; addr < end; addr = next, pte++) {
705 next = (addr + PAGE_SIZE) & PAGE_MASK;
706 if (next > end)
707 next = end;
708
709 if (!pte_present(*pte))
710 continue;
711
712 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
713 /*
714 * The vmemmap_free() and remove_section_mapping()
715 * codepaths call us with aligned addresses.
716 */
717 WARN_ONCE(1, "%s: unaligned range\n", __func__);
718 continue;
719 }
720
721 pte_clear(&init_mm, addr, pte);
722 }
723 }
724
725 /*
726 * clear the pte and potentially split the mapping helper
727 */
split_kernel_mapping(unsigned long addr,unsigned long end,unsigned long size,pte_t * pte)728 static void split_kernel_mapping(unsigned long addr, unsigned long end,
729 unsigned long size, pte_t *pte)
730 {
731 unsigned long mask = ~(size - 1);
732 unsigned long aligned_start = addr & mask;
733 unsigned long aligned_end = addr + size;
734 struct change_mapping_params params;
735 bool split_region = false;
736
737 if ((end - addr) < size) {
738 /*
739 * We're going to clear the PTE, but not flushed
740 * the mapping, time to remap and flush. The
741 * effects if visible outside the processor or
742 * if we are running in code close to the
743 * mapping we cleared, we are in trouble.
744 */
745 if (overlaps_kernel_text(aligned_start, addr) ||
746 overlaps_kernel_text(end, aligned_end)) {
747 /*
748 * Hack, just return, don't pte_clear
749 */
750 WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
751 "text, not splitting\n", addr, end);
752 return;
753 }
754 split_region = true;
755 }
756
757 if (split_region) {
758 params.pte = pte;
759 params.start = addr;
760 params.end = end;
761 params.aligned_start = addr & ~(size - 1);
762 params.aligned_end = min_t(unsigned long, aligned_end,
763 (unsigned long)__va(memblock_end_of_DRAM()));
764 stop_machine(stop_machine_change_mapping, ¶ms, NULL);
765 return;
766 }
767
768 pte_clear(&init_mm, addr, pte);
769 }
770
remove_pmd_table(pmd_t * pmd_start,unsigned long addr,unsigned long end)771 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
772 unsigned long end)
773 {
774 unsigned long next;
775 pte_t *pte_base;
776 pmd_t *pmd;
777
778 pmd = pmd_start + pmd_index(addr);
779 for (; addr < end; addr = next, pmd++) {
780 next = pmd_addr_end(addr, end);
781
782 if (!pmd_present(*pmd))
783 continue;
784
785 if (pmd_huge(*pmd)) {
786 split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
787 continue;
788 }
789
790 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
791 remove_pte_table(pte_base, addr, next);
792 free_pte_table(pte_base, pmd);
793 }
794 }
795
remove_pud_table(pud_t * pud_start,unsigned long addr,unsigned long end)796 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
797 unsigned long end)
798 {
799 unsigned long next;
800 pmd_t *pmd_base;
801 pud_t *pud;
802
803 pud = pud_start + pud_index(addr);
804 for (; addr < end; addr = next, pud++) {
805 next = pud_addr_end(addr, end);
806
807 if (!pud_present(*pud))
808 continue;
809
810 if (pud_huge(*pud)) {
811 split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
812 continue;
813 }
814
815 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
816 remove_pmd_table(pmd_base, addr, next);
817 free_pmd_table(pmd_base, pud);
818 }
819 }
820
remove_pagetable(unsigned long start,unsigned long end)821 static void remove_pagetable(unsigned long start, unsigned long end)
822 {
823 unsigned long addr, next;
824 pud_t *pud_base;
825 pgd_t *pgd;
826
827 spin_lock(&init_mm.page_table_lock);
828
829 for (addr = start; addr < end; addr = next) {
830 next = pgd_addr_end(addr, end);
831
832 pgd = pgd_offset_k(addr);
833 if (!pgd_present(*pgd))
834 continue;
835
836 if (pgd_huge(*pgd)) {
837 split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
838 continue;
839 }
840
841 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
842 remove_pud_table(pud_base, addr, next);
843 }
844
845 spin_unlock(&init_mm.page_table_lock);
846 radix__flush_tlb_kernel_range(start, end);
847 }
848
radix__create_section_mapping(unsigned long start,unsigned long end)849 int __ref radix__create_section_mapping(unsigned long start, unsigned long end)
850 {
851 return create_physical_mapping(start, end);
852 }
853
radix__remove_section_mapping(unsigned long start,unsigned long end)854 int radix__remove_section_mapping(unsigned long start, unsigned long end)
855 {
856 remove_pagetable(start, end);
857 return 0;
858 }
859 #endif /* CONFIG_MEMORY_HOTPLUG */
860
861 #ifdef CONFIG_SPARSEMEM_VMEMMAP
radix__vmemmap_create_mapping(unsigned long start,unsigned long page_size,unsigned long phys)862 int __meminit radix__vmemmap_create_mapping(unsigned long start,
863 unsigned long page_size,
864 unsigned long phys)
865 {
866 /* Create a PTE encoding */
867 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
868
869 BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
870 return 0;
871 }
872
873 #ifdef CONFIG_MEMORY_HOTPLUG
radix__vmemmap_remove_mapping(unsigned long start,unsigned long page_size)874 void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
875 {
876 remove_pagetable(start, start + page_size);
877 }
878 #endif
879 #endif
880
881 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
882
radix__pmd_hugepage_update(struct mm_struct * mm,unsigned long addr,pmd_t * pmdp,unsigned long clr,unsigned long set)883 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
884 pmd_t *pmdp, unsigned long clr,
885 unsigned long set)
886 {
887 unsigned long old;
888
889 #ifdef CONFIG_DEBUG_VM
890 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
891 assert_spin_locked(&mm->page_table_lock);
892 #endif
893
894 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
895 trace_hugepage_update(addr, old, clr, set);
896
897 return old;
898 }
899
radix__pmdp_collapse_flush(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)900 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
901 pmd_t *pmdp)
902
903 {
904 pmd_t pmd;
905
906 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
907 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
908 VM_BUG_ON(pmd_devmap(*pmdp));
909 /*
910 * khugepaged calls this for normal pmd
911 */
912 pmd = *pmdp;
913 pmd_clear(pmdp);
914
915 /*FIXME!! Verify whether we need this kick below */
916 serialize_against_pte_lookup(vma->vm_mm);
917
918 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
919
920 return pmd;
921 }
922
923 /*
924 * For us pgtable_t is pte_t *. Inorder to save the deposisted
925 * page table, we consider the allocated page table as a list
926 * head. On withdraw we need to make sure we zero out the used
927 * list_head memory area.
928 */
radix__pgtable_trans_huge_deposit(struct mm_struct * mm,pmd_t * pmdp,pgtable_t pgtable)929 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
930 pgtable_t pgtable)
931 {
932 struct list_head *lh = (struct list_head *) pgtable;
933
934 assert_spin_locked(pmd_lockptr(mm, pmdp));
935
936 /* FIFO */
937 if (!pmd_huge_pte(mm, pmdp))
938 INIT_LIST_HEAD(lh);
939 else
940 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
941 pmd_huge_pte(mm, pmdp) = pgtable;
942 }
943
radix__pgtable_trans_huge_withdraw(struct mm_struct * mm,pmd_t * pmdp)944 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
945 {
946 pte_t *ptep;
947 pgtable_t pgtable;
948 struct list_head *lh;
949
950 assert_spin_locked(pmd_lockptr(mm, pmdp));
951
952 /* FIFO */
953 pgtable = pmd_huge_pte(mm, pmdp);
954 lh = (struct list_head *) pgtable;
955 if (list_empty(lh))
956 pmd_huge_pte(mm, pmdp) = NULL;
957 else {
958 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
959 list_del(lh);
960 }
961 ptep = (pte_t *) pgtable;
962 *ptep = __pte(0);
963 ptep++;
964 *ptep = __pte(0);
965 return pgtable;
966 }
967
968
radix__pmdp_huge_get_and_clear(struct mm_struct * mm,unsigned long addr,pmd_t * pmdp)969 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
970 unsigned long addr, pmd_t *pmdp)
971 {
972 pmd_t old_pmd;
973 unsigned long old;
974
975 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
976 old_pmd = __pmd(old);
977 /*
978 * Serialize against find_current_mm_pte which does lock-less
979 * lookup in page tables with local interrupts disabled. For huge pages
980 * it casts pmd_t to pte_t. Since format of pte_t is different from
981 * pmd_t we want to prevent transit from pmd pointing to page table
982 * to pmd pointing to huge page (and back) while interrupts are disabled.
983 * We clear pmd to possibly replace it with page table pointer in
984 * different code paths. So make sure we wait for the parallel
985 * find_current_mm_pte to finish.
986 */
987 serialize_against_pte_lookup(mm);
988 return old_pmd;
989 }
990
radix__has_transparent_hugepage(void)991 int radix__has_transparent_hugepage(void)
992 {
993 /* For radix 2M at PMD level means thp */
994 if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
995 return 1;
996 return 0;
997 }
998 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
999