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Searched refs:mpidr (Results 1 – 24 of 24) sorted by relevance

/arch/arm/common/
Dmcpm_platsmp.c25 unsigned int mpidr; in cpu_to_pcpu() local
27 mpidr = cpu_logical_map(cpu); in cpu_to_pcpu()
28 *pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in cpu_to_pcpu()
29 *pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in cpu_to_pcpu()
76 unsigned int mpidr, pcpu, pcluster; in mcpm_cpu_die() local
77 mpidr = read_cpuid_mpidr(); in mcpm_cpu_die()
78 pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_die()
79 pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_die()
Dmcpm_entry.c242 unsigned int mpidr, cpu, cluster; in mcpm_cpu_power_down() local
246 mpidr = read_cpuid_mpidr(); in mcpm_cpu_power_down()
247 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_power_down()
248 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_power_down()
331 unsigned int mpidr = read_cpuid_mpidr(); in mcpm_cpu_suspend() local
332 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_suspend()
333 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in mcpm_cpu_suspend()
343 unsigned int mpidr, cpu, cluster; in mcpm_cpu_powered_up() local
350 mpidr = read_cpuid_mpidr(); in mcpm_cpu_powered_up()
351 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in mcpm_cpu_powered_up()
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DbL_switcher.c127 unsigned int mpidr = read_mpidr(); in bL_switchpoint() local
128 unsigned int clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); in bL_switchpoint()
152 unsigned int mpidr, this_cpu, that_cpu; in bL_switch_to() local
239 mpidr = read_mpidr(); in bL_switch_to()
240 pr_debug("after switch: CPU %d MPIDR %#x\n", this_cpu, mpidr); in bL_switch_to()
241 BUG_ON(mpidr != ib_mpidr); in bL_switch_to()
519 int bL_switcher_get_logical_index(u32 mpidr) in bL_switcher_get_logical_index() argument
526 mpidr &= MPIDR_HWID_BITMASK; in bL_switcher_get_logical_index()
531 if ((mpidr == cpu_logical_map(cpu)) || in bL_switcher_get_logical_index()
532 (mpidr == cpu_logical_map(pairing))) in bL_switcher_get_logical_index()
/arch/arm/mach-hisi/
Dplatmcpm.c103 unsigned int mpidr, cpu, cluster; in hip04_boot_secondary() local
107 mpidr = cpu_logical_map(l_cpu); in hip04_boot_secondary()
108 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in hip04_boot_secondary()
109 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in hip04_boot_secondary()
158 unsigned int mpidr, cpu, cluster; in hip04_cpu_die() local
161 mpidr = cpu_logical_map(l_cpu); in hip04_cpu_die()
162 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in hip04_cpu_die()
163 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in hip04_cpu_die()
196 unsigned int mpidr, cpu, cluster; in hip04_cpu_kill() local
199 mpidr = cpu_logical_map(l_cpu); in hip04_cpu_kill()
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/arch/arm64/kernel/
Dtopology.c251 u64 mpidr; in store_cpu_topology() local
256 mpidr = read_cpuid_mpidr(); in store_cpu_topology()
259 if (mpidr & MPIDR_UP_BITMASK) in store_cpu_topology()
263 if (mpidr & MPIDR_MT_BITMASK) { in store_cpu_topology()
265 cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in store_cpu_topology()
266 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); in store_cpu_topology()
267 cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) | in store_cpu_topology()
268 MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8; in store_cpu_topology()
272 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in store_cpu_topology()
273 cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) | in store_cpu_topology()
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Dacpi_numa.c58 phys_cpuid_t mpidr; in acpi_numa_gicc_affinity_init() local
88 mpidr = acpi_map_madt_entry(pa->acpi_processor_uid); in acpi_numa_gicc_affinity_init()
89 if (mpidr == PHYS_CPUID_INVALID) { in acpi_numa_gicc_affinity_init()
97 early_node_cpu_hwid[cpus_in_srat].cpu_hwid = mpidr; in acpi_numa_gicc_affinity_init()
101 pxm, mpidr, node); in acpi_numa_gicc_affinity_init()
Dsleep.S38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
39 and \mpidr, \mpidr, \mask // mask out MPIDR bits
40 and \dst, \mpidr, #0xff // mask=aff0
42 and \mask, \mpidr, #0xff00 // mask = aff1
45 and \mask, \mpidr, #0xff0000 // mask = aff2
48 and \mask, \mpidr, #0xff00000000 // mask = aff3
Dsetup.c97 u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; in smp_setup_processor_id() local
98 cpu_logical_map(0) = mpidr; in smp_setup_processor_id()
106 pr_info("Booting Linux on physical CPU 0x%lx\n", (unsigned long)mpidr); in smp_setup_processor_id()
/arch/arm/kernel/
Dtopology.c253 unsigned int mpidr; in store_cpu_topology() local
259 mpidr = read_cpuid_mpidr(); in store_cpu_topology()
262 if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) { in store_cpu_topology()
268 if (mpidr & MPIDR_MT_BITMASK) { in store_cpu_topology()
270 cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in store_cpu_topology()
271 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); in store_cpu_topology()
272 cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2); in store_cpu_topology()
276 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in store_cpu_topology()
277 cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); in store_cpu_topology()
299 cpu_topology[cpuid].socket_id, mpidr); in store_cpu_topology()
Dsleep.S38 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
39 and \mpidr, \mpidr, \mask @ mask out MPIDR bits
40 and \dst, \mpidr, #0xff @ mask=aff0
43 and \mask, \mpidr, #0xff00 @ mask = aff1
47 and \mask, \mpidr, #0xff0000 @ mask = aff2
78 ldmia r0, {r1, r6-r8} @ r1 = mpidr mask (r6,r7,r8) = l[0,1,2] shifts
157 ldmia r2, { r3-r6 } @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
Ddevtree.c81 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; in arm_dt_init_cpu_maps() local
148 if (hwid == mpidr) { in arm_dt_init_cpu_maps()
Dsetup.c592 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0; in smp_setup_processor_id() local
593 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in smp_setup_processor_id()
606 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr); in smp_setup_processor_id()
/arch/arm/mach-exynos/
Dplatsmp.c55 u32 mpidr = cpu_logical_map(cpu); in platform_do_lowpower() local
56 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in platform_do_lowpower()
302 u32 mpidr = cpu_logical_map(cpu); in exynos_boot_secondary() local
303 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in exynos_boot_secondary()
410 u32 mpidr; in exynos_smp_prepare_cpus() local
414 mpidr = cpu_logical_map(i); in exynos_smp_prepare_cpus()
415 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in exynos_smp_prepare_cpus()
433 u32 mpidr = cpu_logical_map(cpu); in exynos_cpu_die() local
434 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); in exynos_cpu_die()
Dsuspend.c263 unsigned int mpidr = read_cpuid_mpidr(); in exynos5420_cpu_suspend() local
264 unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in exynos5420_cpu_suspend()
265 unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in exynos5420_cpu_suspend()
444 unsigned int mpidr, cluster; in exynos5420_prepare_pm_resume() local
446 mpidr = read_cpuid_mpidr(); in exynos5420_prepare_pm_resume()
447 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in exynos5420_prepare_pm_resume()
/arch/arm64/include/asm/
Dsmp_plat.h50 static inline int get_logical_index(u64 mpidr) in get_logical_index() argument
54 if (cpu_logical_map(cpu) == mpidr) in get_logical_index()
Dcputype.h32 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ argument
33 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
Dkvm_host.h354 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
/arch/arm/include/asm/
DbL_switcher.h58 int bL_switcher_get_logical_index(u32 mpidr);
74 static inline int bL_switcher_get_logical_index(u32 mpidr) { return -EUNATCH; } in bL_switcher_get_logical_index() argument
Dsmp_plat.h80 static inline int get_logical_index(u32 mpidr) in get_logical_index() argument
84 if (cpu_logical_map(cpu) == mpidr) in get_logical_index()
Dcputype.h61 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ argument
62 ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
Dkvm_host.h280 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
/arch/arm/mach-vexpress/
Dtc2_pm.c207 unsigned int mpidr, cpu, cluster; in tc2_pm_init() local
247 mpidr = read_cpuid_mpidr(); in tc2_pm_init()
248 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); in tc2_pm_init()
249 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); in tc2_pm_init()
/arch/arm/mach-shmobile/
Dheadsmp.S51 add r5, r5, r2 @ array of per-cpu mpidr values
/arch/arm64/kvm/
Dsys_regs.c454 u64 mpidr; in reset_mpidr() local
463 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); in reset_mpidr()
464 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); in reset_mpidr()
465 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); in reset_mpidr()
466 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr; in reset_mpidr()