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Searched refs:r16 (Results 1 – 25 of 124) sorted by relevance

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/arch/ia64/kernel/
Dminstate.h49 mov r16=IA64_KR(CURRENT); /* M */ \
59 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \
61 ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \
62 st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \
63 adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \
86 adds r16=PT(CR_IPSR),r1; \
89 st8 [r16]=r29; /* save cr.ipsr */ \
96 adds r16=PT(R8),r1; /* initialize first base pointer */ \
100 .mem.offset 0,0; st8.spill [r16]=r8,16; \
103 .mem.offset 0,0; st8.spill [r16]=r10,24; \
[all …]
Divt.S74 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
114 MOV_FROM_IFA(r16) // get address that caused the TLB miss
123 shl r21=r16,3 // shift bit 60 into sign bit
124 shr.u r17=r16,61 // get the region number into r17
242 (p6) ptc.l r16,r27 // purge translation
260 MOV_FROM_IFA(r16) // get virtual address
287 (p7) ptc.l r16,r20
304 MOV_FROM_IFA(r16) // get virtual address
331 (p7) ptc.l r16,r20
342 MOV_FROM_IFA(r16) // get address that caused the TLB miss
[all …]
Drelocate_kernel.S40 movl r16 = IA64_PSR_AC|IA64_PSR_BN|IA64_PSR_IC
49 mov cr.ipsr=r16
98 movl r16=KERNEL_START
101 ptr.i r16, r18
102 ptr.d r16, r18
108 mov r16=in3
111 ptr.i r16,r18
117 mov r16=IA64_KR(CURRENT_STACK)
119 shl r16=r16,IA64_GRANULE_SHIFT
122 add r16=r19,r16
[all …]
Djprobes.S66 movl r16=invalidate_restore_cfm
68 mov b6=r16
73 mov r16=ar.rsc
79 mov ar.rsc=r16
Dmca_asm.S100 movl r16=KERNEL_START
103 ptr.i r16, r18
104 ptr.d r16, r18
113 ld8 r16=[r2]
116 ptr.i r16,r18
121 mov r16=IA64_KR(CURRENT_STACK)
123 shl r16=r16,IA64_GRANULE_SHIFT
126 add r16=r19,r16
129 ptr.d r16,r18
174 mov r16=IA64_TR_KERNEL
[all …]
Desi_stub.S75 movl r16=PSR_BITS_TO_CLEAR
82 andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
88 mov r16=loc3 // save virtual mode psr
Defi_stub.S58 movl r16=PSR_BITS_TO_CLEAR
65 andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
78 mov r16=loc3
Dfsys.S65 add r17=IA64_TASK_GROUP_LEADER_OFFSET,r16
68 add r9=TI_FLAGS+IA64_TASK_SIZE,r16
98 add r9=TI_FLAGS+IA64_TASK_SIZE,r16
99 add r17=IA64_TASK_TGIDLINK_OFFSET,r16
107 add r18=IA64_TASK_CLEAR_CHILD_TID_OFFSET,r16
194 add r2 = TI_FLAGS+IA64_TASK_SIZE,r16
337 add r2=TI_FLAGS+IA64_TASK_SIZE,r16
339 add r3=TI_CPU+IA64_TASK_SIZE,r16
473 mov r2=r16 // A get task addr to addl-addressable register
474 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // A
[all …]
Dpal.S174 movl r16=PAL_PSR_BITS_TO_CLEAR
179 andcm r16=loc3,r16 // removes bits to clear from psr
187 mov r16=loc3 // r16= original psr
226 movl r16=PAL_PSR_BITS_TO_CLEAR
232 andcm r16=loc3,r16 // removes bits to clear from psr
245 mov r16=loc3 // r16= original psr
Dentry.S113 alloc r16=ar.pfs,8,2,6,0
117 mov loc1=r16 // save ar.pfs across do_fork
144 alloc r16=ar.pfs,8,2,6,0
148 mov loc1=r16 // save ar.pfs across do_fork
174 alloc r16=ar.pfs,1,0,0,0
315 st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs
389 ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
439 mov ar.pfs=r16
471 adds r16=PT(F6)+16,sp
474 stf.spill [r16]=f6,32
[all …]
Dhead.S228 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
229 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
230 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
231 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
232 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
233 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
234 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
235 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
244 mov r16=IA64_TR_KERNEL
254 itr.i itr[r16]=r18
[all …]
Dmca_drv_asm.S21 alloc r16=ar.pfs,0,2,3,0 // make a new frame
35 mov loc0=r16
Dgate.S211 mov.m r16=ar.bsp // sc_loadrs <- (new bsp - new bspstore) << 16
215 sub r15=r16,r15
246 adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp
249 ld8 r17=[r16]
250 ld8 r16=[r18] // get new rnat
294 mov ar.rnat=r16 // restore RNaT
332 mov r16=IA64_KR(CURRENT) // M2 (12 cyc)
/arch/powerpc/mm/
Dtlb_low_64e.S65 std r16,EX_TLB_R16(r12)
66 mfspr r16,\addr /* get faulting address */
96 ld r16,EX_TLB_R16(r12)
128 srdi r15,r16,60 /* get region */
129 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
153 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
170 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
177 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
183 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
204 clrrdi r11,r16,12 /* Clear low crap in EA */
[all …]
/arch/powerpc/include/asm/
Dexception-64e.h111 std r16,EX_TLB_R16(r12); \
112 mfspr r16,SPRN_SRR0; \
117 std r16,EX_TLB_SRR0(r12); \
141 ld r16,EX_TLB_SRR1(r12); \
149 mtspr SPRN_SRR1,r16; \
151 ld r16,EX_TLB_R16(r12); \
172 ld r16,EX_TLB_LR(r12); \
175 mtlr r16;
/arch/powerpc/crypto/
Daes-spe-keys.S28 stw r16,16(r1);
33 lwz r16,16(r1); \
89 li r16,10 /* 10 expansion rounds */
106 subi r16,r16,1
107 cmpwi r16,0
135 li r16,8 /* 8 expansion rounds */
153 subi r16,r16,1
154 cmpwi r16,0 /* last round early kick out */
189 li r16,7 /* 7 expansion rounds */
211 subi r16,r16,1
[all …]
/arch/powerpc/lib/
Dchecksum_64.S69 std r16,STK_REG(R16)(r1)
91 ld r16,56(r3)
106 adde r0,r0,r16
118 ld r16,56(r3)
126 adde r0,r0,r16
130 ld r16,STK_REG(R16)(r1)
263 std r16,STK_REG(R16)(r1)
285 source; ld r16,56(r3)
302 dest; std r16,56(r4)
309 adde r0,r0,r16
[all …]
Dcopypage_power7.S118 std r16,STK_REG(R16)(r1)
135 ld r16,88(r4)
152 std r16,88(r3)
162 ld r16,STK_REG(R16)(r1)
/arch/microblaze/kernel/
Dexceptions.c56 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16); in sw_exception()
57 flush_dcache_range(regs->r16, regs->r16 + 0x4); in sw_exception()
58 flush_icache_range(regs->r16, regs->r16 + 0x4); in sw_exception()
/arch/ia64/lib/
Dstrnlen_user.S22 .save ar.lc, r16
23 mov r16=ar.lc // preserve ar.lc
45 mov ar.lc=r16 // restore ar.lc
Dxor.S35 mov r16 = in1
44 (p[0]) ld8.nta s1[0] = [r16], 8
73 mov r16 = in1
83 (p[0]) ld8.nta s1[0] = [r16], 8
114 mov r16 = in1
125 (p[0]) ld8.nta s1[0] = [r16], 8
158 mov r16 = in1
170 (p[0]) ld8.nta s1[0] = [r16], 8
/arch/tile/kernel/
Dmcount_64.S144 moveli r16, hw2_last(ftrace_graph_entry)
148 shl16insli r16, r16, hw1(ftrace_graph_entry)
152 shl16insli r16, r16, hw0(ftrace_graph_entry)
155 ld r16, r16
156 sub r17, r16, r17
/arch/parisc/kernel/
Dentry.S131 mtsp %r16,%sr3
139 STREG %r16,PT_SR7(%r9)
153 STREG %r16,PT_SR7(%r9)
175 mfsp %sr7,%r16
848 mfctl %cr30,%r16
849 LDREG TI_TASK(%r16), %r16 /* thread_info -> task_struct */
850 ldo TASK_REGS(%r16),%r16
854 LDREG PT_IAOQ0(%r16),%r19
856 STREG %r19,PT_IAOQ0(%r16)
857 LDREG PT_IAOQ1(%r16),%r19
[all …]
/arch/tile/lib/
Dmemcpy_32.S176 EX: { move r12, r5; lw r16, r1 }
183 EX: { move r12, r6; lw r16, r1 }
190 EX: { move r12, r7; lw r16, r1 }
268 EX: { lw r13, r1; addi r1, r1, 4; move zero, r16 } /* r13 = WORD_1 */
290 EX: { sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */
291 EX: { sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */
292 EX: { sw r0, r14; addi r0, r0, 4; slt_u r16, r9, r16 } /* store(WORD_2) */
295 EX: { sw r0, r17; addi r0, r0, 4; mvz r9, r16, r13 }/* store(WORD_4) */
434 slti_u r16, r2, 64 + 32
448 { bzt r16, .Lcopy_unaligned_line; move r7, r6 }
/arch/ia64/hp/sim/boot/
Dboot_head.S118 mov r16=0xffff /* implemented PMC */
122 st8 [r29]=r16,16 /* store implemented PMC */
130 mov r16=0xf0 /* cycles count capable PMC */
136 st8 [r29]=r16,16 /* store cycles capable */

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