| /arch/sh/kernel/ |
| D | head_64.S | 190 movi MMUIR_END, r22
194 bne r21, r22, tr1
199 movi MMUDR_END, r22
203 bne r21, r22, tr1
207 movi MMUIR_TEXT_L, r22 /* PTEL first */
208 add.l r22, r63, r22 /* Sign extend */
209 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
210 movi MMUIR_TEXT_H, r22 /* PTEH last */
211 add.l r22, r63, r22 /* Sign extend */
212 putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
[all …]
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| /arch/sh/boot/compressed/ |
| D | head_64.S | 66 movi ITLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22
69 bne r21, r22, tr1
74 movi DTLB_LAST_VAR_UNRESTRICTED+TLB_STEP, r22
77 bne r21, r22, tr1
81 movi MMUIR_TEXT_L, r22 /* PTEL first */
82 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
83 movi MMUIR_TEXT_H, r22 /* PTEH last */
84 putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
88 movi MMUDR_CACHED_L, r22 /* PTEL first */
89 putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */
[all …]
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| /arch/ia64/lib/ |
| D | flush.S | 33 sub r22=in1,r0,1 // last byte address
36 shr.u r22=r22,r20 // (last byte address) / (stride size)
39 sub r8=r22,r23 // number of strides - 1
84 add r22=in1,in0
87 sub r22=r22,r0,1 // last byte address
90 shr.u r22=r22,r20 // (last byte address) / (stride size)
93 sub r8=r22,r23 // number of strides - 1
|
| D | ip_fast_csum.S | 48 ld4 r22=[in0],8
53 add r22=r22,r23
55 add r20=r20,r22
104 ld4 r22=[in0],4
112 add r17=r22,r23
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| /arch/sh/lib64/ |
| D | copy_user_memcpy.S | 163 sub r2, r7, r22
171 ldx.q r22, r6, r0
182 ! ldx.q r22, r36, r63 ! TAKum03020
183 alloco r22, 32
185 addi r22, 32, r22
186 ldx.q r22, r19, r23
187 sthi.q r22, -25, r0
188 ldx.q r22, r20, r24
189 ldx.q r22, r21, r25
190 stlo.q r22, -32, r0
[all …]
|
| D | memcpy.S | 148 sub r2, r7, r22
156 ldx.q r22, r6, r0
167 ldx.q r22, r36, r63
168 alloco r22, 32
169 addi r22, 32, r22
170 ldx.q r22, r19, r23
171 sthi.q r22, -25, r0
172 ldx.q r22, r20, r24
173 ldx.q r22, r21, r25
174 stlo.q r22, -32, r0
[all …]
|
| D | udivsi3.S | 12 addz.l r5,r63,r22
13 nsb r22,r0
14 shlld r22,r0,r25
36 mulu.l r18,r22,r20
45 mulu.l r19,r22,r20
52 sub r25,r22,r25
54 mulu.l r19,r22,r20
|
| D | udivdi3.S | 7 nsb r4,r22
8 shlld r3,r22,r6
14 sub r63,r22,r20 // r63 == 64 % 64
25 addi r22,-31,r0
93 addi r22,32,r0
|
| D | copy_page.S | 62 addi r60, 0x80, r22
71 ldx.q r2, r22, r63 ! prefetch 4 lines hence
|
| /arch/tile/lib/ |
| D | atomic_asm_32.S | 88 lh r22, r0
90 lw r22, r0
99 seq r26, r22, r24
118 move r0, r22
145 6: mfspr r22, CYCLE_LOW /* test to see if we've backed off enough */
146 sub r22, r22, r26
147 slt r22, r22, r25
148 bbst r22, 6b
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| /arch/parisc/kernel/ |
| D | pacache.S | 83 LDREG ITLB_SID_COUNT(%r1), %r22
106 addib,COND(<=),n -1, %r22, fitdone /* Outer loop count decr */
117 addib,COND(>) -1, %r22, fitoneloop /* Outer loop count decr */
126 LDREG DTLB_SID_COUNT(%r1), %r22
149 addib,COND(<=),n -1, %r22,fdtdone /* Outer loop count decr */
160 addib,COND(>) -1, %r22, fdtoneloop /* Outer loop count decr */
211 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
255 mtsm %r22 /* restore I-bit */
278 rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
323 mtsm %r22 /* restore I-bit */
[all …]
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| D | sys_parisc32.c | 20 int r22, int r21, int r20) in sys32_unimplemented() argument
|
| /arch/ia64/kernel/ |
| D | ivt.S | 126 shr.u r22=r21,3
134 (p8) shr r22=r22,r27
138 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
153 shr.u r28=r22,PUD_SHIFT // shift pud index into position
155 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
164 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
174 shr.u r19=r22,PAGE_SHIFT // shift pte index into position
183 MOV_FROM_IHA(r22) // get the VHPT address that caused the TLB miss
191 MOV_TO_IFA(r22, r24)
239 (p6) ptc.l r22,r27 // purge PTE page translation
[all …]
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| D | mca_drv_asm.S | 27 addl r22=IA64_RBS_OFFSET,r2
29 mov ar.bspstore=r22
|
| D | minstate.h | 73 (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
76 (pUStk) lfetch.fault.excl.nt1 [r22]; \
80 (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
108 (pUStk) sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \
178 .mem.offset 0,0; st8.spill [r2]=r22,16; \
217 (pUStk) sub r16=r18,r22; \
242 mov ar.bspstore=r22 \
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| D | fsys.S | 201 add r22 = IA64_GTOD_WALL_TIME_OFFSET,r20 // wall_time
207 (p15) add r22 = IA64_GTOD_MONO_TIME_OFFSET,r20 // monotonic_time
239 ld8 r9 = [r22],IA64_TIMESPEC_TV_NSEC_OFFSET // tv_sec
241 ld8 r8 = [r22],-IA64_TIMESPEC_TV_NSEC_OFFSET // tv_nsec
478 addl r22=IA64_RBS_OFFSET,r2 // A compute base of RBS
482 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch register backing-store
497 mov ar.bspstore=r22 // M2 (6 cyc) switch to kernel RBS
522 sub r22=r19,r18 // stime before leave kernel
527 add r20=r20,r22 // sum stime
538 SSM_PSR_I(p0, p6, r22) // M2 we're on kernel stacks now, reenable irqs
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| /arch/tile/kernel/ |
| D | intvec_32.S | 429 push_reg r22, r52
650 lw r22, r23
653 bbnst r22, \not_single_stepping
656 andi r22, r22, ~SINGLESTEP_STATE_MASK_IS_ENABLED
668 sw r23, r22
699 sw r23, r22
730 sw r23, r22
868 addi r22, r21, THREAD_INFO_FLAGS_OFFSET
872 lw r22, r22
875 and r1, r22, r20
[all …]
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| /arch/parisc/include/asm/ |
| D | unistd.h | 82 #define K_LOAD_ARGS_5(r26,r25,r24,r23,r22) \ argument
83 register unsigned long __r22 __asm__("r22") = (unsigned long)(r22); \
85 #define K_LOAD_ARGS_6(r26,r25,r24,r23,r22,r21) \ argument
87 K_LOAD_ARGS_5(r26,r25,r24,r23,r22)
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| D | asmregs.h | 40 arg4: .reg r22
68 r22: .reg %r22
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| /arch/microblaze/lib/ |
| D | uaccess_old.S | 111 5: lwi r22, r6, 0x0010 + offset; \
119 13: swi r22, r5, 0x0010 + offset; \
199 swi r22, r1, 24
222 lwi r22, r1, 24
242 lwi r22, r1, 24
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| /arch/alpha/include/uapi/asm/ |
| D | ptrace.h | 33 unsigned long r22; member
|
| /arch/arc/include/asm/ |
| D | unwind.h | 39 unsigned long r22; member
98 PTREGS_INFO(r22), \
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| /arch/arc/include/uapi/asm/ |
| D | ptrace.h | 45 unsigned long r25, r24, r23, r22, r21, r20; member
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| /arch/hexagon/include/uapi/asm/ |
| D | user.h | 36 unsigned long r22; member
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| /arch/hexagon/include/asm/ |
| D | processor.h | 123 unsigned long r22; member
|