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Searched refs:rn (Results 1 – 25 of 31) sorted by relevance

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/arch/powerpc/include/asm/
Dreg_8xx.h70 #define do_mtspr_cpu6(rn, rn_addr, v) \ argument
75 "mtspr " __stringify(rn) ",%2" : \
81 #define do_mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ argument
84 #define mtspr(rn, v) \ argument
86 if (rn == SPRN_IMMR) \
87 do_mtspr_cpu6(rn, 0x3d30, v); \
88 else if (rn == SPRN_IC_CST) \
89 do_mtspr_cpu6(rn, 0x2110, v); \
90 else if (rn == SPRN_IC_ADR) \
91 do_mtspr_cpu6(rn, 0x2310, v); \
[all …]
Ddcr-native.h65 #define mfdcr(rn) \ argument
67 if (__builtin_constant_p(rn) && rn < 1024) \
68 asm volatile("mfdcr %0," __stringify(rn) \
71 rval = mfdcrx(rn); \
73 rval = __mfdcr(rn); \
76 #define mtdcr(rn, v) \ argument
78 if (__builtin_constant_p(rn) && rn < 1024) \
79 asm volatile("mtdcr " __stringify(rn) ",%0" \
82 mtdcrx(rn, v); \
84 __mtdcr(rn, v); \
Dreg_fsl_emb.h12 #define mfpmr(rn) ({unsigned int rval; \ argument
13 asm volatile("mfpmr %0," __stringify(rn) \
15 #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) argument
Dreg_booke.h759 #define mftmr(rn) ({unsigned long rval; \ argument
760 asm volatile(MFTMR(rn, %0) : "=r" (rval)); rval;})
761 #define mttmr(rn, v) asm volatile(MTTMR(rn, %0) : \ argument
Dreg.h1319 #define mfspr(rn) ({unsigned long rval; \ argument
1320 asm volatile("mfspr %0," __stringify(rn) \
1323 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \ argument
1327 #define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \ argument
/arch/arm/net/
Dbpf_jit_32.h157 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument
159 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
163 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
164 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) argument
165 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
166 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument
167 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
168 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
170 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
171 #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) argument
[all …]
Dbpf_jit_32.c363 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op) in emit_udivmod() argument
371 emit(ARM_CMP_I(rn, 0), ctx); in emit_udivmod()
378 emit(ARM_UDIV(rd, rm, rn), ctx); in emit_udivmod()
380 emit(ARM_UDIV(ARM_IP, rm, rn), ctx); in emit_udivmod()
381 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx); in emit_udivmod()
395 if (rn != ARM_R1) { in emit_udivmod()
397 emit(ARM_MOV_R(ARM_R1, rn), ctx); in emit_udivmod()
414 if (rn != ARM_R1) in emit_udivmod()
544 u8 rn = sstk ? tmp[1] : src; in emit_a32_alu_r() local
547 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src)), ctx); in emit_a32_alu_r()
[all …]
/arch/arm/probes/kprobes/
Dactions-arm.c82 int rn = (insn >> 16) & 0xf; in emulate_ldrdstrd() local
87 register unsigned long rnv asm("r2") = (rn == 15) ? pc in emulate_ldrdstrd()
88 : regs->uregs[rn]; in emulate_ldrdstrd()
102 regs->uregs[rn] = rnv; in emulate_ldrdstrd()
111 int rn = (insn >> 16) & 0xf; in emulate_ldr() local
115 register unsigned long rnv asm("r2") = (rn == 15) ? pc in emulate_ldr()
116 : regs->uregs[rn]; in emulate_ldr()
132 regs->uregs[rn] = rnv; in emulate_ldr()
142 int rn = (insn >> 16) & 0xf; in emulate_str() local
147 register unsigned long rnv asm("r2") = (rn == 15) ? rnpc in emulate_str()
[all …]
Dactions-common.c25 int rn = (insn >> 16) & 0xf; in simulate_ldm1stm1() local
30 long *addr = (long *)regs->uregs[rn]; in simulate_ldm1stm1()
59 regs->uregs[rn] = (long)addr; in simulate_ldm1stm1()
134 int rn = (insn >> 16) & 0xf; in kprobe_decode_ldmstm() local
136 if (rn <= 12 && (reglist & 0xe000) == 0) { in kprobe_decode_ldmstm()
140 } else if (rn >= 2 && (reglist & 0x8003) == 0) { in kprobe_decode_ldmstm()
142 rn -= 2; in kprobe_decode_ldmstm()
146 } else if (rn >= 3 && (reglist & 0x0007) == 0) { in kprobe_decode_ldmstm()
149 rn -= 3; in kprobe_decode_ldmstm()
158 (rn << 16) | reglist); in kprobe_decode_ldmstm()
Dactions-thumb.c31 int rn = (insn >> 16) & 0xf; in t32_simulate_table_branch() local
34 unsigned long rnv = (rn == 15) ? pc : regs->uregs[rn]; in t32_simulate_table_branch()
167 int rn = (insn >> 16) & 0xf; in t32_emulate_ldrdstrd() local
171 register unsigned long rnv asm("r2") = (rn == 15) ? pc in t32_emulate_ldrdstrd()
172 : regs->uregs[rn]; in t32_emulate_ldrdstrd()
181 if (rn != 15) in t32_emulate_ldrdstrd()
182 regs->uregs[rn] = rnv; /* Writeback base register */ in t32_emulate_ldrdstrd()
192 int rn = (insn >> 16) & 0xf; in t32_emulate_ldrstr() local
196 register unsigned long rnv asm("r2") = regs->uregs[rn]; in t32_emulate_ldrstr()
206 regs->uregs[rn] = rnv; /* Writeback base register */ in t32_emulate_ldrstr()
[all …]
Dcheckers-arm.c130 unsigned int rn = (insn >> 16) & 0xf; in arm_check_regs_ldmstm() local
131 asi->register_usage_flags = reglist | (1 << rn); in arm_check_regs_ldmstm()
/arch/powerpc/boot/
Dreg.h22 #define mfspr(rn) ({unsigned long rval; \ argument
23 asm volatile("mfspr %0," __stringify(rn) \
25 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) argument
Ddcr.h5 #define mfdcr(rn) \ argument
8 asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
11 #define mtdcr(rn, val) \ argument
12 asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
13 #define mfdcrx(rn) \ argument
16 asm volatile("mfdcrx %0,%1" : "=r"(rval) : "r"(rn)); \
19 #define mtdcrx(rn, val) \ argument
21 asm volatile("mtdcrx %0,%1" : : "r"(rn), "r" (val)); \
/arch/unicore32/mm/
Dproc-macros.S41 .macro vma_vm_mm, rd, rn argument
42 ldw \rd, [\rn+], #VMA_VM_MM
48 .macro vma_vm_flags, rd, rn argument
49 ldw \rd, [\rn+], #VMA_VM_FLAGS
52 .macro tsk_mm, rd, rn argument
53 ldw \rd, [\rn+], #TI_TASK
70 .macro mmid, rd, rn argument
71 ldw \rd, [\rn+], #MM_CONTEXT_ID
77 .macro asid, rd, rn argument
78 and \rd, \rn, #255
Dalignment.c292 unsigned int rd, rn, pc_correction, reg_correction, nr_regs, regbits; in do_alignment_ldmstm() local
303 rn = RN_BITS(instr); in do_alignment_ldmstm()
304 newaddr = eaddr = regs->uregs[rn]; in do_alignment_ldmstm()
344 regs->uregs[rn] = newaddr; in do_alignment_ldmstm()
/arch/arm/mm/
Dabort-lv4t.S37 /* 0 */ b .data_arm_lateldrhpost @ ldrh rd, [rn], #m/rm
38 /* 1 */ b .data_arm_lateldrhpre @ ldrh rd, [rn, #m/rm]
41 /* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
42 /* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
43 /* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
44 /* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
45 /* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
46 /* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
49 /* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
50 /* d */ b do_DataAbort @ ldc rd, [rn, #m]
Dproc-macros.S18 .macro vma_vm_mm, rd, rn argument
19 ldr \rd, [\rn, #VMA_VM_MM]
25 .macro vma_vm_flags, rd, rn argument
26 ldr \rd, [\rn, #VMA_VM_FLAGS]
46 .macro mmid, rd, rn argument
48 ldr \rd, [\rn, #MM_CONTEXT_ID + 4 ]
50 ldr \rd, [\rn, #MM_CONTEXT_ID]
57 .macro asid, rd, rn argument
58 and \rd, \rn, #255
/arch/sh/kernel/
Dtraps_32.c92 unsigned long *rm, *rn; in handle_unaligned_ins() local
97 rn = &regs->regs[index]; in handle_unaligned_ins()
118 dst = (unsigned char *)rn; in handle_unaligned_ins()
134 dstu = (unsigned char __user *)*rn; in handle_unaligned_ins()
145 dstu = (unsigned char __user *)*rn; in handle_unaligned_ins()
155 *rn -= count; in handle_unaligned_ins()
157 dstu = (unsigned char __user *)*rn; in handle_unaligned_ins()
169 dst = (unsigned char *)rn; in handle_unaligned_ins()
181 dst = (unsigned char*) rn; in handle_unaligned_ins()
229 dst = (unsigned char *)rn; in handle_unaligned_ins()
[all …]
Ddisassemble.c304 int rn = 0; in print_sh_insn() local
364 rn = nibs[n]; in print_sh_insn()
370 rn = (nibs[n] & 0xc) >> 2; in print_sh_insn()
396 printk("r%d", rn); in print_sh_insn()
399 printk("@r%d+", rn); in print_sh_insn()
402 printk("@-r%d", rn); in print_sh_insn()
405 printk("@r%d", rn); in print_sh_insn()
408 printk("@(%d,r%d)", imm, rn); in print_sh_insn()
435 printk("@(r0,r%d)", rn); in print_sh_insn()
484 printk("fr%d", rn); in print_sh_insn()
[all …]
/arch/arm/mach-tegra/
Dsleep.h54 .macro wait_until, rn, base, tmp
55 add \rn, \rn, #1
57 cmp \tmp, \rn
/arch/arm/probes/uprobes/
Dactions-arm.c169 int rn = (insn >> 16) & 0xf; in uprobe_decode_ldmstm() local
171 unsigned used = reglist | (1 << rn); in uprobe_decode_ldmstm()
173 if (rn == 15) in uprobe_decode_ldmstm()
/arch/arm64/kernel/
Dentry-ftrace.S59 .macro mcount_adjust_addr rd, rn argument
60 sub \rd, \rn, #AARCH64_INSN_SIZE
Darmv8_deprecated.c382 int rn, rt2, res = 0; in swp_handler() local
401 rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET); in swp_handler()
404 address = (u32)regs->user_regs.regs[rn]; in swp_handler()
409 rn, address, destreg, in swp_handler()
/arch/powerpc/lib/
Dsstep.c39 extern void get_fpr(int rn, double *p);
40 extern void put_fpr(int rn, const double *p);
41 extern void get_vr(int rn, __vector128 *p);
42 extern void put_vr(int rn, __vector128 *p);
463 int err, rn, nb; in do_fp_load() local
476 rn = op->reg; in do_fp_load()
495 put_fpr(rn, &u.d[0]); in do_fp_load()
497 current->thread.TS_FPR(rn) = u.l[0]; in do_fp_load()
500 rn |= 1; in do_fp_load()
502 put_fpr(rn, &u.d[1]); in do_fp_load()
[all …]
/arch/arm64/include/asm/
Dassembler.h289 .macro vma_vm_mm, rd, rn
290 ldr \rd, [\rn, #VMA_VM_MM]
296 .macro mmid, rd, rn
297 ldr \rd, [\rn, #MM_CONTEXT_ID]

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