/arch/x86/kvm/ |
D | mmutrace.h | 14 __field(__u32, role) \ 21 __entry->role = sp->role.word; \ 30 union kvm_mmu_page_role role; \ 32 role.word = __entry->role; \ 37 __entry->gfn, role.level, \ 38 role.cr4_pae ? " pae" : "", \ 39 role.quadrant, \ 40 role.direct ? " direct" : "", \ 41 access_str[role.access], \ 42 role.invalid ? " invalid" : "", \ [all …]
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D | mmu_audit.c | 141 slots = kvm_memslots_for_spte_role(kvm, rev_sp->role); in inspect_spte_has_rmap() 153 rmap_head = __gfn_to_rmap(gfn, rev_sp->role.level, slot); in inspect_spte_has_rmap() 182 if (sp->role.level != PT_PAGE_TABLE_LEVEL) in check_mappings_rmap() 201 if (sp->role.direct || sp->unsync || sp->role.invalid) in audit_write_protection() 204 slots = kvm_memslots_for_spte_role(kvm, sp->role); in audit_write_protection() 212 sp->gfn, sp->role.word); in audit_write_protection()
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D | mmu.c | 285 return sp->role.ad_disabled; in sp_ad_disabled() 1035 if (!sp->role.direct) in kvm_mmu_page_get_gfn() 1038 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); in kvm_mmu_page_get_gfn() 1043 if (!sp->role.direct) { in kvm_mmu_page_set_gfn() 1100 slots = kvm_memslots_for_spte_role(kvm, sp->role); in account_shadowed() 1104 if (sp->role.level > PT_PAGE_TABLE_LEVEL) in account_shadowed() 1130 slots = kvm_memslots_for_spte_role(kvm, sp->role); in unaccount_shadowed() 1132 if (sp->role.level > PT_PAGE_TABLE_LEVEL) in unaccount_shadowed() 1356 slots = kvm_memslots_for_spte_role(kvm, sp->role); in gfn_to_rmap() 1358 return __gfn_to_rmap(gfn, sp->role.level, slot); in gfn_to_rmap() [all …]
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D | paging_tmpl.h | 511 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); in FNAME() 570 if (sp->role.level > PT_PAGE_TABLE_LEVEL) in FNAME() 573 if (sp->role.direct) in FNAME() 866 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); in FNAME() 869 offset = sp->role.quadrant << PT64_LEVEL_BITS; in FNAME() 988 BUG_ON(sp->role.direct); in FNAME() 1019 pte_access = sp->role.access; in FNAME()
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/arch/arm/mach-omap2/ |
D | omap_hwmod_54xx_data.c | 355 { .role = "32khz_clk", .clk = "dss_32khz_clk" }, 356 { .role = "sys_clk", .clk = "dss_sys_clk" }, 357 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, 402 { .role = "sys_clk", .clk = "dss_sys_clk" }, 451 { .role = "sys_clk", .clk = "dss_sys_clk" }, 472 { .role = "sys_clk", .clk = "dss_sys_clk" }, 512 { .role = "sys_clk", .clk = "dss_sys_clk" }, 553 { .role = "ick", .clk = "l3_iclk_div" }, 648 { .role = "dbclk", .clk = "gpio1_dbclk" }, 670 { .role = "dbclk", .clk = "gpio2_dbclk" }, [all …]
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D | omap_hwmod_7xx_data.c | 582 { .role = "dss_clk", .clk = "dss_dss_clk" }, 583 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" }, 584 { .role = "32khz_clk", .clk = "dss_32khz_clk" }, 585 { .role = "video2_clk", .clk = "dss_video2_clk" }, 586 { .role = "video1_clk", .clk = "dss_video1_clk" }, 587 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" }, 588 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" }, 677 { .role = "sys_clk", .clk = "dss_hdmi_clk" }, 836 { .role = "dbclk", .clk = "gpio1_dbclk" }, 859 { .role = "dbclk", .clk = "gpio2_dbclk" }, [all …]
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D | omap_hwmod_44xx_data.c | 577 { .role = "sys_clk", .clk = "dss_sys_clk" }, 578 { .role = "tv_clk", .clk = "dss_tv_clk" }, 579 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, 689 { .role = "sys_clk", .clk = "dss_sys_clk" }, 723 { .role = "sys_clk", .clk = "dss_sys_clk" }, 777 { .role = "sys_clk", .clk = "dss_sys_clk" }, 778 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, 832 { .role = "ick", .clk = "l3_div_ck" }, 863 { .role = "tv_clk", .clk = "dss_tv_clk" }, 1162 { .role = "dbclk", .clk = "gpio1_dbclk" }, [all …]
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D | omap_hwmod_3xxx_data.c | 540 { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, 580 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 581 { .role = "tv_clk", .clk = "dss_tv_fck" }, 583 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 686 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 706 { .role = "ick", .clk = "dss_ick" }, 727 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 847 { .role = "dbclk", .clk = "gpio1_dbck", }, 871 { .role = "dbclk", .clk = "gpio2_dbck", }, 895 { .role = "dbclk", .clk = "gpio3_dbck", }, [all …]
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D | omap_hwmod_2430_data.c | 259 { .role = "pad_fck", .clk = "mcbsp_clks" }, 260 { .role = "prcm_fck", .clk = "func_96m_ck" }, 372 { .role = "dbck", .clk = "mmchsdb1_fck" }, 400 { .role = "dbck", .clk = "mmchsdb2_fck" },
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D | omap_hwmod_33xx_data.c | 199 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" }, 200 { .role = "dbg_clka", .clk = "dbg_clka_ck" }, 238 { .role = "dbclk", .clk = "gpio0_dbclk" },
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D | omap_hwmod_2420_data.c | 190 { .role = "pad_fck", .clk = "mcbsp_clks" }, 191 { .role = "prcm_fck", .clk = "func_96m_ck" },
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D | omap_hwmod_2xxx_ipblock_data.c | 545 { .role = "tv_clk", .clk = "dss_54m_fck" }, 546 { .role = "sys_clk", .clk = "dss2_fck" }, 586 { .role = "ick", .clk = "dss_ick" },
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D | omap_hwmod_43xx_data.c | 93 { .role = "dbclk", .clk = "gpio0_dbclk" }, 274 { .role = "dbclk", .clk = "gpio4_dbclk" }, 295 { .role = "dbclk", .clk = "gpio5_dbclk" },
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D | omap_hwmod_33xx_43xx_ipblock_data.c | 547 { .role = "dbclk", .clk = "gpio1_dbclk" }, 568 { .role = "dbclk", .clk = "gpio2_dbclk" }, 589 { .role = "dbclk", .clk = "gpio3_dbclk" },
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D | omap_hwmod_81xx_data.c | 497 { .role = "dbclk", .clk = "sysclk18_ck" }, 524 { .role = "dbclk", .clk = "sysclk18_ck" }, 1026 { .role = "dbck", .clk = "sysclk18_ck", },
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D | omap_hwmod.h | 222 const char *role; member
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D | omap_device.c | 119 _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk); in _add_hwmod_clocks_clkdev()
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D | omap_hwmod.c | 946 pr_debug("omap_hwmod: enable %s:%s\n", oc->role, in _enable_optional_clocks() 961 pr_debug("omap_hwmod: disable %s:%s\n", oc->role, in _disable_optional_clocks()
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/arch/arm/boot/dts/ |
D | dove-cm-a510.dtsi | 66 * U2: 2 dual-role USB2.0 ports
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D | imx51-digi-connectcore-som.dtsi | 203 /* Device role is not known, keep status disabled */
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D | am57xx-beagle-x15-common.dtsi | 496 * as "host" or "dual-role". If so, provide
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/arch/x86/include/asm/ |
D | kvm_host.h | 287 union kvm_mmu_page_role role; member 1361 #define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm) argument
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