1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 /*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26 #if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
36 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
37 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
38 #ifdef CONFIG_X86_64
39 #define PT_MAX_FULL_LEVELS 4
40 #define CMPXCHG cmpxchg
41 #else
42 #define CMPXCHG cmpxchg64
43 #define PT_MAX_FULL_LEVELS 2
44 #endif
45 #elif PTTYPE == 32
46 #define pt_element_t u32
47 #define guest_walker guest_walker32
48 #define FNAME(name) paging##32_##name
49 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
50 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
51 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
52 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
53 #define PT_LEVEL_BITS PT32_LEVEL_BITS
54 #define PT_MAX_FULL_LEVELS 2
55 #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
56 #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
57 #define PT_HAVE_ACCESSED_DIRTY(mmu) true
58 #define CMPXCHG cmpxchg
59 #elif PTTYPE == PTTYPE_EPT
60 #define pt_element_t u64
61 #define guest_walker guest_walkerEPT
62 #define FNAME(name) ept_##name
63 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
64 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
65 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
66 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
67 #define PT_LEVEL_BITS PT64_LEVEL_BITS
68 #define PT_GUEST_DIRTY_SHIFT 9
69 #define PT_GUEST_ACCESSED_SHIFT 8
70 #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
71 #define CMPXCHG cmpxchg64
72 #define PT_MAX_FULL_LEVELS 4
73 #else
74 #error Invalid PTTYPE value
75 #endif
76
77 #define PT_GUEST_DIRTY_MASK (1 << PT_GUEST_DIRTY_SHIFT)
78 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
79
80 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
81 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
82
83 /*
84 * The guest_walker structure emulates the behavior of the hardware page
85 * table walker.
86 */
87 struct guest_walker {
88 int level;
89 unsigned max_level;
90 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
91 pt_element_t ptes[PT_MAX_FULL_LEVELS];
92 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
93 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
94 pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
95 bool pte_writable[PT_MAX_FULL_LEVELS];
96 unsigned pt_access;
97 unsigned pte_access;
98 gfn_t gfn;
99 struct x86_exception fault;
100 };
101
gpte_to_gfn_lvl(pt_element_t gpte,int lvl)102 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
103 {
104 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
105 }
106
FNAME(protect_clean_gpte)107 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
108 unsigned gpte)
109 {
110 unsigned mask;
111
112 /* dirty bit is not supported, so no need to track it */
113 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
114 return;
115
116 BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
117
118 mask = (unsigned)~ACC_WRITE_MASK;
119 /* Allow write access to dirty gptes */
120 mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
121 PT_WRITABLE_MASK;
122 *access &= mask;
123 }
124
FNAME(is_present_gpte)125 static inline int FNAME(is_present_gpte)(unsigned long pte)
126 {
127 #if PTTYPE != PTTYPE_EPT
128 return pte & PT_PRESENT_MASK;
129 #else
130 return pte & 7;
131 #endif
132 }
133
FNAME(cmpxchg_gpte)134 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
135 pt_element_t __user *ptep_user, unsigned index,
136 pt_element_t orig_pte, pt_element_t new_pte)
137 {
138 int npages;
139 pt_element_t ret;
140 pt_element_t *table;
141 struct page *page;
142
143 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
144 /* Check if the user is doing something meaningless. */
145 if (unlikely(npages != 1))
146 return -EFAULT;
147
148 table = kmap_atomic(page);
149 ret = CMPXCHG(&table[index], orig_pte, new_pte);
150 kunmap_atomic(table);
151
152 kvm_release_page_dirty(page);
153
154 return (ret != orig_pte);
155 }
156
FNAME(prefetch_invalid_gpte)157 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
158 struct kvm_mmu_page *sp, u64 *spte,
159 u64 gpte)
160 {
161 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
162 goto no_present;
163
164 if (!FNAME(is_present_gpte)(gpte))
165 goto no_present;
166
167 /* if accessed bit is not supported prefetch non accessed gpte */
168 if (PT_HAVE_ACCESSED_DIRTY(&vcpu->arch.mmu) && !(gpte & PT_GUEST_ACCESSED_MASK))
169 goto no_present;
170
171 return false;
172
173 no_present:
174 drop_spte(vcpu->kvm, spte);
175 return true;
176 }
177
178 /*
179 * For PTTYPE_EPT, a page table can be executable but not readable
180 * on supported processors. Therefore, set_spte does not automatically
181 * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
182 * to signify readability since it isn't used in the EPT case
183 */
FNAME(gpte_access)184 static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
185 {
186 unsigned access;
187 #if PTTYPE == PTTYPE_EPT
188 access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
189 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
190 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
191 #else
192 BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
193 BUILD_BUG_ON(ACC_EXEC_MASK != 1);
194 access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
195 /* Combine NX with P (which is set here) to get ACC_EXEC_MASK. */
196 access ^= (gpte >> PT64_NX_SHIFT);
197 #endif
198
199 return access;
200 }
201
FNAME(update_accessed_dirty_bits)202 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
203 struct kvm_mmu *mmu,
204 struct guest_walker *walker,
205 int write_fault)
206 {
207 unsigned level, index;
208 pt_element_t pte, orig_pte;
209 pt_element_t __user *ptep_user;
210 gfn_t table_gfn;
211 int ret;
212
213 /* dirty/accessed bits are not supported, so no need to update them */
214 if (!PT_HAVE_ACCESSED_DIRTY(mmu))
215 return 0;
216
217 for (level = walker->max_level; level >= walker->level; --level) {
218 pte = orig_pte = walker->ptes[level - 1];
219 table_gfn = walker->table_gfn[level - 1];
220 ptep_user = walker->ptep_user[level - 1];
221 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
222 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
223 trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
224 pte |= PT_GUEST_ACCESSED_MASK;
225 }
226 if (level == walker->level && write_fault &&
227 !(pte & PT_GUEST_DIRTY_MASK)) {
228 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
229 #if PTTYPE == PTTYPE_EPT
230 if (kvm_arch_write_log_dirty(vcpu))
231 return -EINVAL;
232 #endif
233 pte |= PT_GUEST_DIRTY_MASK;
234 }
235 if (pte == orig_pte)
236 continue;
237
238 /*
239 * If the slot is read-only, simply do not process the accessed
240 * and dirty bits. This is the correct thing to do if the slot
241 * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
242 * are only supported if the accessed and dirty bits are already
243 * set in the ROM (so that MMIO writes are never needed).
244 *
245 * Note that NPT does not allow this at all and faults, since
246 * it always wants nested page table entries for the guest
247 * page tables to be writable. And EPT works but will simply
248 * overwrite the read-only memory to set the accessed and dirty
249 * bits.
250 */
251 if (unlikely(!walker->pte_writable[level - 1]))
252 continue;
253
254 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
255 if (ret)
256 return ret;
257
258 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
259 walker->ptes[level - 1] = pte;
260 }
261 return 0;
262 }
263
FNAME(gpte_pkeys)264 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
265 {
266 unsigned pkeys = 0;
267 #if PTTYPE == 64
268 pte_t pte = {.pte = gpte};
269
270 pkeys = pte_flags_pkey(pte_flags(pte));
271 #endif
272 return pkeys;
273 }
274
275 /*
276 * Fetch a guest pte for a guest virtual address
277 */
FNAME(walk_addr_generic)278 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
279 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
280 gva_t addr, u32 access)
281 {
282 int ret;
283 pt_element_t pte;
284 pt_element_t __user *uninitialized_var(ptep_user);
285 gfn_t table_gfn;
286 u64 pt_access, pte_access;
287 unsigned index, accessed_dirty, pte_pkey;
288 unsigned nested_access;
289 gpa_t pte_gpa;
290 bool have_ad;
291 int offset;
292 u64 walk_nx_mask = 0;
293 const int write_fault = access & PFERR_WRITE_MASK;
294 const int user_fault = access & PFERR_USER_MASK;
295 const int fetch_fault = access & PFERR_FETCH_MASK;
296 u16 errcode = 0;
297 gpa_t real_gpa;
298 gfn_t gfn;
299
300 trace_kvm_mmu_pagetable_walk(addr, access);
301 retry_walk:
302 walker->level = mmu->root_level;
303 pte = mmu->get_cr3(vcpu);
304 have_ad = PT_HAVE_ACCESSED_DIRTY(mmu);
305
306 #if PTTYPE == 64
307 walk_nx_mask = 1ULL << PT64_NX_SHIFT;
308 if (walker->level == PT32E_ROOT_LEVEL) {
309 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
310 trace_kvm_mmu_paging_element(pte, walker->level);
311 if (!FNAME(is_present_gpte)(pte))
312 goto error;
313 --walker->level;
314 }
315 #endif
316 walker->max_level = walker->level;
317 ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
318
319 /*
320 * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
321 * by the MOV to CR instruction are treated as reads and do not cause the
322 * processor to set the dirty flag in any EPT paging-structure entry.
323 */
324 nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
325
326 pte_access = ~0;
327 ++walker->level;
328
329 do {
330 gfn_t real_gfn;
331 unsigned long host_addr;
332
333 pt_access = pte_access;
334 --walker->level;
335
336 index = PT_INDEX(addr, walker->level);
337 table_gfn = gpte_to_gfn(pte);
338 offset = index * sizeof(pt_element_t);
339 pte_gpa = gfn_to_gpa(table_gfn) + offset;
340
341 BUG_ON(walker->level < 1);
342 walker->table_gfn[walker->level - 1] = table_gfn;
343 walker->pte_gpa[walker->level - 1] = pte_gpa;
344
345 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
346 nested_access,
347 &walker->fault);
348
349 /*
350 * FIXME: This can happen if emulation (for of an INS/OUTS
351 * instruction) triggers a nested page fault. The exit
352 * qualification / exit info field will incorrectly have
353 * "guest page access" as the nested page fault's cause,
354 * instead of "guest page structure access". To fix this,
355 * the x86_exception struct should be augmented with enough
356 * information to fix the exit_qualification or exit_info_1
357 * fields.
358 */
359 if (unlikely(real_gfn == UNMAPPED_GVA))
360 return 0;
361
362 real_gfn = gpa_to_gfn(real_gfn);
363
364 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
365 &walker->pte_writable[walker->level - 1]);
366 if (unlikely(kvm_is_error_hva(host_addr)))
367 goto error;
368
369 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
370 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
371 goto error;
372 walker->ptep_user[walker->level - 1] = ptep_user;
373
374 trace_kvm_mmu_paging_element(pte, walker->level);
375
376 /*
377 * Inverting the NX it lets us AND it like other
378 * permission bits.
379 */
380 pte_access = pt_access & (pte ^ walk_nx_mask);
381
382 if (unlikely(!FNAME(is_present_gpte)(pte)))
383 goto error;
384
385 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
386 errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
387 goto error;
388 }
389
390 walker->ptes[walker->level - 1] = pte;
391 } while (!is_last_gpte(mmu, walker->level, pte));
392
393 pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
394 accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
395
396 /* Convert to ACC_*_MASK flags for struct guest_walker. */
397 walker->pt_access = FNAME(gpte_access)(vcpu, pt_access ^ walk_nx_mask);
398 walker->pte_access = FNAME(gpte_access)(vcpu, pte_access ^ walk_nx_mask);
399 errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
400 if (unlikely(errcode))
401 goto error;
402
403 gfn = gpte_to_gfn_lvl(pte, walker->level);
404 gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
405
406 if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
407 gfn += pse36_gfn_delta(pte);
408
409 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
410 if (real_gpa == UNMAPPED_GVA)
411 return 0;
412
413 walker->gfn = real_gpa >> PAGE_SHIFT;
414
415 if (!write_fault)
416 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
417 else
418 /*
419 * On a write fault, fold the dirty bit into accessed_dirty.
420 * For modes without A/D bits support accessed_dirty will be
421 * always clear.
422 */
423 accessed_dirty &= pte >>
424 (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
425
426 if (unlikely(!accessed_dirty)) {
427 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
428 if (unlikely(ret < 0))
429 goto error;
430 else if (ret)
431 goto retry_walk;
432 }
433
434 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
435 __func__, (u64)pte, walker->pte_access, walker->pt_access);
436 return 1;
437
438 error:
439 errcode |= write_fault | user_fault;
440 if (fetch_fault && (mmu->nx ||
441 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
442 errcode |= PFERR_FETCH_MASK;
443
444 walker->fault.vector = PF_VECTOR;
445 walker->fault.error_code_valid = true;
446 walker->fault.error_code = errcode;
447
448 #if PTTYPE == PTTYPE_EPT
449 /*
450 * Use PFERR_RSVD_MASK in error_code to to tell if EPT
451 * misconfiguration requires to be injected. The detection is
452 * done by is_rsvd_bits_set() above.
453 *
454 * We set up the value of exit_qualification to inject:
455 * [2:0] - Derive from the access bits. The exit_qualification might be
456 * out of date if it is serving an EPT misconfiguration.
457 * [5:3] - Calculated by the page walk of the guest EPT page tables
458 * [7:8] - Derived from [7:8] of real exit_qualification
459 *
460 * The other bits are set to 0.
461 */
462 if (!(errcode & PFERR_RSVD_MASK)) {
463 vcpu->arch.exit_qualification &= 0x180;
464 if (write_fault)
465 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
466 if (user_fault)
467 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
468 if (fetch_fault)
469 vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
470 vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
471 }
472 #endif
473 walker->fault.address = addr;
474 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
475
476 trace_kvm_mmu_walker_error(walker->fault.error_code);
477 return 0;
478 }
479
FNAME(walk_addr)480 static int FNAME(walk_addr)(struct guest_walker *walker,
481 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
482 {
483 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
484 access);
485 }
486
487 #if PTTYPE != PTTYPE_EPT
FNAME(walk_addr_nested)488 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
489 struct kvm_vcpu *vcpu, gva_t addr,
490 u32 access)
491 {
492 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
493 addr, access);
494 }
495 #endif
496
497 static bool
FNAME(prefetch_gpte)498 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
499 u64 *spte, pt_element_t gpte, bool no_dirty_log)
500 {
501 unsigned pte_access;
502 gfn_t gfn;
503 kvm_pfn_t pfn;
504
505 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
506 return false;
507
508 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
509
510 gfn = gpte_to_gfn(gpte);
511 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
512 FNAME(protect_clean_gpte)(&vcpu->arch.mmu, &pte_access, gpte);
513 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
514 no_dirty_log && (pte_access & ACC_WRITE_MASK));
515 if (is_error_pfn(pfn))
516 return false;
517
518 /*
519 * we call mmu_set_spte() with host_writable = true because
520 * pte_prefetch_gfn_to_pfn always gets a writable pfn.
521 */
522 mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
523 true, true);
524
525 kvm_release_pfn_clean(pfn);
526 return true;
527 }
528
FNAME(update_pte)529 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
530 u64 *spte, const void *pte)
531 {
532 pt_element_t gpte = *(const pt_element_t *)pte;
533
534 FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
535 }
536
FNAME(gpte_changed)537 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
538 struct guest_walker *gw, int level)
539 {
540 pt_element_t curr_pte;
541 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
542 u64 mask;
543 int r, index;
544
545 if (level == PT_PAGE_TABLE_LEVEL) {
546 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
547 base_gpa = pte_gpa & ~mask;
548 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
549
550 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
551 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
552 curr_pte = gw->prefetch_ptes[index];
553 } else
554 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
555 &curr_pte, sizeof(curr_pte));
556
557 return r || curr_pte != gw->ptes[level - 1];
558 }
559
FNAME(pte_prefetch)560 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
561 u64 *sptep)
562 {
563 struct kvm_mmu_page *sp;
564 pt_element_t *gptep = gw->prefetch_ptes;
565 u64 *spte;
566 int i;
567
568 sp = page_header(__pa(sptep));
569
570 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
571 return;
572
573 if (sp->role.direct)
574 return __direct_pte_prefetch(vcpu, sp, sptep);
575
576 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
577 spte = sp->spt + i;
578
579 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
580 if (spte == sptep)
581 continue;
582
583 if (is_shadow_present_pte(*spte))
584 continue;
585
586 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
587 break;
588 }
589 }
590
591 /*
592 * Fetch a shadow pte for a specific level in the paging hierarchy.
593 * If the guest tries to write a write-protected page, we need to
594 * emulate this operation, return 1 to indicate this case.
595 */
FNAME(fetch)596 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
597 struct guest_walker *gw,
598 int write_fault, int hlevel,
599 kvm_pfn_t pfn, bool map_writable, bool prefault,
600 bool lpage_disallowed)
601 {
602 struct kvm_mmu_page *sp = NULL;
603 struct kvm_shadow_walk_iterator it;
604 unsigned direct_access, access = gw->pt_access;
605 int top_level, ret;
606 gfn_t gfn, base_gfn;
607
608 direct_access = gw->pte_access;
609
610 top_level = vcpu->arch.mmu.root_level;
611 if (top_level == PT32E_ROOT_LEVEL)
612 top_level = PT32_ROOT_LEVEL;
613 /*
614 * Verify that the top-level gpte is still there. Since the page
615 * is a root page, it is either write protected (and cannot be
616 * changed from now on) or it is invalid (in which case, we don't
617 * really care if it changes underneath us after this point).
618 */
619 if (FNAME(gpte_changed)(vcpu, gw, top_level))
620 goto out_gpte_changed;
621
622 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
623 goto out_gpte_changed;
624
625 for (shadow_walk_init(&it, vcpu, addr);
626 shadow_walk_okay(&it) && it.level > gw->level;
627 shadow_walk_next(&it)) {
628 gfn_t table_gfn;
629
630 clear_sp_write_flooding_count(it.sptep);
631 drop_large_spte(vcpu, it.sptep);
632
633 sp = NULL;
634 if (!is_shadow_present_pte(*it.sptep)) {
635 table_gfn = gw->table_gfn[it.level - 2];
636 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
637 false, access);
638 }
639
640 /*
641 * Verify that the gpte in the page we've just write
642 * protected is still there.
643 */
644 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
645 goto out_gpte_changed;
646
647 if (sp)
648 link_shadow_page(vcpu, it.sptep, sp);
649 }
650
651 /*
652 * FNAME(page_fault) might have clobbered the bottom bits of
653 * gw->gfn, restore them from the virtual address.
654 */
655 gfn = gw->gfn | ((addr & PT_LVL_OFFSET_MASK(gw->level)) >> PAGE_SHIFT);
656 base_gfn = gfn;
657
658 trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
659
660 for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
661 clear_sp_write_flooding_count(it.sptep);
662
663 /*
664 * We cannot overwrite existing page tables with an NX
665 * large page, as the leaf could be executable.
666 */
667 disallowed_hugepage_adjust(it, gfn, &pfn, &hlevel);
668
669 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
670 if (it.level == hlevel)
671 break;
672
673 validate_direct_spte(vcpu, it.sptep, direct_access);
674
675 drop_large_spte(vcpu, it.sptep);
676
677 if (!is_shadow_present_pte(*it.sptep)) {
678 sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
679 it.level - 1, true, direct_access);
680 link_shadow_page(vcpu, it.sptep, sp);
681 if (lpage_disallowed)
682 account_huge_nx_page(vcpu->kvm, sp);
683 }
684 }
685
686 ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
687 it.level, base_gfn, pfn, prefault, map_writable);
688 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
689 ++vcpu->stat.pf_fixed;
690 return ret;
691
692 out_gpte_changed:
693 return RET_PF_RETRY;
694 }
695
696 /*
697 * To see whether the mapped gfn can write its page table in the current
698 * mapping.
699 *
700 * It is the helper function of FNAME(page_fault). When guest uses large page
701 * size to map the writable gfn which is used as current page table, we should
702 * force kvm to use small page size to map it because new shadow page will be
703 * created when kvm establishes shadow page table that stop kvm using large
704 * page size. Do it early can avoid unnecessary #PF and emulation.
705 *
706 * @write_fault_to_shadow_pgtable will return true if the fault gfn is
707 * currently used as its page table.
708 *
709 * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
710 * since the PDPT is always shadowed, that means, we can not use large page
711 * size to map the gfn which is used as PDPT.
712 */
713 static bool
FNAME(is_self_change_mapping)714 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
715 struct guest_walker *walker, int user_fault,
716 bool *write_fault_to_shadow_pgtable)
717 {
718 int level;
719 gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
720 bool self_changed = false;
721
722 if (!(walker->pte_access & ACC_WRITE_MASK ||
723 (!is_write_protection(vcpu) && !user_fault)))
724 return false;
725
726 for (level = walker->level; level <= walker->max_level; level++) {
727 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
728
729 self_changed |= !(gfn & mask);
730 *write_fault_to_shadow_pgtable |= !gfn;
731 }
732
733 return self_changed;
734 }
735
736 /*
737 * Page fault handler. There are several causes for a page fault:
738 * - there is no shadow pte for the guest pte
739 * - write access through a shadow pte marked read only so that we can set
740 * the dirty bit
741 * - write access to a shadow pte marked read only so we can update the page
742 * dirty bitmap, when userspace requests it
743 * - mmio access; in this case we will never install a present shadow pte
744 * - normal guest page fault due to the guest pte marked not present, not
745 * writable, or not executable
746 *
747 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
748 * a negative value on error.
749 */
FNAME(page_fault)750 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
751 bool prefault)
752 {
753 int write_fault = error_code & PFERR_WRITE_MASK;
754 int user_fault = error_code & PFERR_USER_MASK;
755 struct guest_walker walker;
756 int r;
757 kvm_pfn_t pfn;
758 int level = PT_PAGE_TABLE_LEVEL;
759 unsigned long mmu_seq;
760 bool map_writable, is_self_change_mapping;
761 bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) &&
762 is_nx_huge_page_enabled();
763 bool force_pt_level = lpage_disallowed;
764
765 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
766
767 r = mmu_topup_memory_caches(vcpu);
768 if (r)
769 return r;
770
771 /*
772 * If PFEC.RSVD is set, this is a shadow page fault.
773 * The bit needs to be cleared before walking guest page tables.
774 */
775 error_code &= ~PFERR_RSVD_MASK;
776
777 /*
778 * Look up the guest pte for the faulting address.
779 */
780 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
781
782 /*
783 * The page is not mapped by the guest. Let the guest handle it.
784 */
785 if (!r) {
786 pgprintk("%s: guest page fault\n", __func__);
787 if (!prefault)
788 inject_page_fault(vcpu, &walker.fault);
789
790 return RET_PF_RETRY;
791 }
792
793 if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
794 shadow_page_table_clear_flood(vcpu, addr);
795 return RET_PF_EMULATE;
796 }
797
798 vcpu->arch.write_fault_to_shadow_pgtable = false;
799
800 is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
801 &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
802
803 if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
804 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
805 if (likely(!force_pt_level)) {
806 level = min(walker.level, level);
807 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
808 }
809 } else
810 force_pt_level = true;
811
812 mmu_seq = vcpu->kvm->mmu_notifier_seq;
813 smp_rmb();
814
815 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
816 &map_writable))
817 return RET_PF_RETRY;
818
819 if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r))
820 return r;
821
822 /*
823 * Do not change pte_access if the pfn is a mmio page, otherwise
824 * we will cache the incorrect access into mmio spte.
825 */
826 if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
827 !is_write_protection(vcpu) && !user_fault &&
828 !is_noslot_pfn(pfn)) {
829 walker.pte_access |= ACC_WRITE_MASK;
830 walker.pte_access &= ~ACC_USER_MASK;
831
832 /*
833 * If we converted a user page to a kernel page,
834 * so that the kernel can write to it when cr0.wp=0,
835 * then we should prevent the kernel from executing it
836 * if SMEP is enabled.
837 */
838 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
839 walker.pte_access &= ~ACC_EXEC_MASK;
840 }
841
842 r = RET_PF_RETRY;
843 spin_lock(&vcpu->kvm->mmu_lock);
844 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
845 goto out_unlock;
846
847 kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
848 if (make_mmu_pages_available(vcpu) < 0)
849 goto out_unlock;
850 if (!force_pt_level)
851 transparent_hugepage_adjust(vcpu, walker.gfn, &pfn, &level);
852 r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
853 level, pfn, map_writable, prefault, lpage_disallowed);
854 kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
855
856 out_unlock:
857 spin_unlock(&vcpu->kvm->mmu_lock);
858 kvm_release_pfn_clean(pfn);
859 return r;
860 }
861
FNAME(get_level1_sp_gpa)862 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
863 {
864 int offset = 0;
865
866 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
867
868 if (PTTYPE == 32)
869 offset = sp->role.quadrant << PT64_LEVEL_BITS;
870
871 return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
872 }
873
FNAME(invlpg)874 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
875 {
876 struct kvm_shadow_walk_iterator iterator;
877 struct kvm_mmu_page *sp;
878 int level;
879 u64 *sptep;
880
881 vcpu_clear_mmio_info(vcpu, gva);
882
883 /*
884 * No need to check return value here, rmap_can_add() can
885 * help us to skip pte prefetch later.
886 */
887 mmu_topup_memory_caches(vcpu);
888
889 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
890 WARN_ON(1);
891 return;
892 }
893
894 spin_lock(&vcpu->kvm->mmu_lock);
895 for_each_shadow_entry(vcpu, gva, iterator) {
896 level = iterator.level;
897 sptep = iterator.sptep;
898
899 sp = page_header(__pa(sptep));
900 if (is_last_spte(*sptep, level)) {
901 pt_element_t gpte;
902 gpa_t pte_gpa;
903
904 if (!sp->unsync)
905 break;
906
907 pte_gpa = FNAME(get_level1_sp_gpa)(sp);
908 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
909
910 if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
911 kvm_flush_remote_tlbs(vcpu->kvm);
912
913 if (!rmap_can_add(vcpu))
914 break;
915
916 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
917 sizeof(pt_element_t)))
918 break;
919
920 FNAME(update_pte)(vcpu, sp, sptep, &gpte);
921 }
922
923 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
924 break;
925 }
926 spin_unlock(&vcpu->kvm->mmu_lock);
927 }
928
FNAME(gva_to_gpa)929 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
930 struct x86_exception *exception)
931 {
932 struct guest_walker walker;
933 gpa_t gpa = UNMAPPED_GVA;
934 int r;
935
936 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
937
938 if (r) {
939 gpa = gfn_to_gpa(walker.gfn);
940 gpa |= vaddr & ~PAGE_MASK;
941 } else if (exception)
942 *exception = walker.fault;
943
944 return gpa;
945 }
946
947 #if PTTYPE != PTTYPE_EPT
FNAME(gva_to_gpa_nested)948 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
949 u32 access,
950 struct x86_exception *exception)
951 {
952 struct guest_walker walker;
953 gpa_t gpa = UNMAPPED_GVA;
954 int r;
955
956 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
957
958 if (r) {
959 gpa = gfn_to_gpa(walker.gfn);
960 gpa |= vaddr & ~PAGE_MASK;
961 } else if (exception)
962 *exception = walker.fault;
963
964 return gpa;
965 }
966 #endif
967
968 /*
969 * Using the cached information from sp->gfns is safe because:
970 * - The spte has a reference to the struct page, so the pfn for a given gfn
971 * can't change unless all sptes pointing to it are nuked first.
972 *
973 * Note:
974 * We should flush all tlbs if spte is dropped even though guest is
975 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
976 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
977 * used by guest then tlbs are not flushed, so guest is allowed to access the
978 * freed pages.
979 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
980 */
FNAME(sync_page)981 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
982 {
983 int i, nr_present = 0;
984 bool host_writable;
985 gpa_t first_pte_gpa;
986
987 /* direct kvm_mmu_page can not be unsync. */
988 BUG_ON(sp->role.direct);
989
990 first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
991
992 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
993 unsigned pte_access;
994 pt_element_t gpte;
995 gpa_t pte_gpa;
996 gfn_t gfn;
997
998 if (!sp->spt[i])
999 continue;
1000
1001 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1002
1003 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1004 sizeof(pt_element_t)))
1005 return 0;
1006
1007 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1008 /*
1009 * Update spte before increasing tlbs_dirty to make
1010 * sure no tlb flush is lost after spte is zapped; see
1011 * the comments in kvm_flush_remote_tlbs().
1012 */
1013 smp_wmb();
1014 vcpu->kvm->tlbs_dirty++;
1015 continue;
1016 }
1017
1018 gfn = gpte_to_gfn(gpte);
1019 pte_access = sp->role.access;
1020 pte_access &= FNAME(gpte_access)(vcpu, gpte);
1021 FNAME(protect_clean_gpte)(&vcpu->arch.mmu, &pte_access, gpte);
1022
1023 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1024 &nr_present))
1025 continue;
1026
1027 if (gfn != sp->gfns[i]) {
1028 drop_spte(vcpu->kvm, &sp->spt[i]);
1029 /*
1030 * The same as above where we are doing
1031 * prefetch_invalid_gpte().
1032 */
1033 smp_wmb();
1034 vcpu->kvm->tlbs_dirty++;
1035 continue;
1036 }
1037
1038 nr_present++;
1039
1040 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1041
1042 set_spte(vcpu, &sp->spt[i], pte_access,
1043 PT_PAGE_TABLE_LEVEL, gfn,
1044 spte_to_pfn(sp->spt[i]), true, false,
1045 host_writable);
1046 }
1047
1048 return nr_present;
1049 }
1050
1051 #undef pt_element_t
1052 #undef guest_walker
1053 #undef FNAME
1054 #undef PT_BASE_ADDR_MASK
1055 #undef PT_INDEX
1056 #undef PT_LVL_ADDR_MASK
1057 #undef PT_LVL_OFFSET_MASK
1058 #undef PT_LEVEL_BITS
1059 #undef PT_MAX_FULL_LEVELS
1060 #undef gpte_to_gfn
1061 #undef gpte_to_gfn_lvl
1062 #undef CMPXCHG
1063 #undef PT_GUEST_ACCESSED_MASK
1064 #undef PT_GUEST_DIRTY_MASK
1065 #undef PT_GUEST_DIRTY_SHIFT
1066 #undef PT_GUEST_ACCESSED_SHIFT
1067 #undef PT_HAVE_ACCESSED_DIRTY
1068