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Searched refs:CP_INT_CNTL_RING0 (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c1574 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
1575 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
1576 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
1577 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
3843 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state()
3913 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_reg_fault_state()
3932 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_inst_fault_state()
Dgfx_v8_0.c3807 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3808 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3809 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
3810 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v8_0_enable_gui_idle_interrupt()
6463 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()
6523 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, in gfx_v8_0_set_priv_reg_fault_state()
6534 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE, in gfx_v8_0_set_priv_inst_fault_state()
Dsid.h1305 #define CP_INT_CNTL_RING0 0x306A macro
/drivers/gpu/drm/radeon/
Dsi.c5144 u32 tmp = RREG32(CP_INT_CNTL_RING0); in si_enable_gui_idle_interrupt()
5152 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5949 tmp = RREG32(CP_INT_CNTL_RING0) & in si_disable_interrupt_state()
5951 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
6067 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set()
6099 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
Dsid.h1276 #define CP_INT_CNTL_RING0 0xC1A8 macro
Dcik.c5806 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt()
5812 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
6917 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state()
6919 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
7094 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7213 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
Dcikd.h1333 #define CP_INT_CNTL_RING0 0xC1A8 macro